Do you think we can split the patch intended to fix PR46779
> PR target/46779
> * config/avr/avr.c (avr_hard_regno_mode_ok): Rewrite.
> In particular, allow 8-bit values in r28 and r29.
> (avr_hard_regno_scratch_ok): Disallow any register that might be
> part of the f
This patch will put progmem strings into a mergeable strings section.
progmem_section is globally renamed to progmem_sw_table_section as
it's only used for switch_case jumptables.
The code that attached the explicit section name ".progmem" in
avr_insert_attributes is removed.
Instead, avr_init_s
Hans-Peter Nilsson schrieb:
> On Mon, 13 Jun 2011, Georg-Johann Lay wrote:
>> [In CCing Richard Henderson]
>> Denis Chertykov schrieb:
>>> 2011/6/10 Georg-Johann Lay :
>
>>>> Then I observed trouble with DI patterns during libgcc build and had
>&
Denis Chertykov schrieb:
2011/6/24 Richard Henderson :
On 06/23/2011 01:15 PM, Denis Chertykov wrote:
textdata bss dec hex filename
10032 25 0 100572749 bld-avr-orig/gcc/z.o
5816 25 0584116d1 bld-avr-new/gcc/z.o
Richard, can you send me
Denis Chertykov wrote:
> 2011/6/26 Georg-Johann Lay :
>> Denis Chertykov schrieb:
>>> 2011/6/24 Richard Henderson :
>>>
>>>> On 06/23/2011 01:15 PM, Denis Chertykov wrote:
>>>>
>>>>>> textdata bss dec hex filen
vision 0)
@@ -0,0 +1,61 @@
+/* Copyright (C) 2011
+ Free Software Foundation, Inc.
+ Contributed by Georg-Johann Lay (a...@gjlay.de)
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as publis
Denis Chertykov wrote:
> 2011/6/27 Georg-Johann Lay :
>> This patch removes ELF dependencies from avr.h and redundancies from
>> avr.h and avr.c
>>
>> The AVR BE defines many things that are readily available in elfos.h.
>> ELF is the only target supported by
Denis Chertykov schrieb:
2011/6/27 Georg-Johann Lay:
http://gcc.gnu.org/ml/gcc-patches/2011-06/msg02011.html
[...]
Is there a specific reason not to emit .ident?
If not, I would remove the #undefs of IDENT_ASM_OP and
ASM_OUTPUT_IDENT from avr/elf.h.
Sorry, I forgot.
Denis.
It's j
This implements "mulhisi3" and "umulhisi3" widening multiplication
insns if AVR_HAVE_MUL.
I chose the interface as r25:r22 = r19:r18 * r21:r20 which is ok
because only avr-gcc BE will call respective __* support functions in
libgcc.
Tested without regression and hand-tested assembler code.
Johan
http://gcc.gnu.org/ml/gcc-patches/2011-06/msg01462.html
Georg-Johann Lay wrote:
> PR34734 produces annoying, false warnings if __attribute__((progmem))
> is used in conjunction with C++. DECL_INITIAL is not yet set up in
> avr_handle_progmem_attribute.
>
> Johann
>
>
Denis Chertykov wrote:
> 2011/6/28 Georg-Johann Lay :
>> http://gcc.gnu.org/ml/gcc-patches/2011-06/msg01462.html
>>
>> Georg-Johann Lay wrote:
>>> PR34734 produces annoying, false warnings if __attribute__((progmem))
>>> is used in conjunction with
Denis Chertykov wrote:
> 2011/6/29 Georg-Johann Lay :
>> Denis Chertykov wrote:
>>> 2011/6/28 Georg-Johann Lay :
>>>> http://gcc.gnu.org/ml/gcc-patches/2011-06/msg01462.html
>>>>
>>>> Georg-Johann Lay wrote:
>>>>> PR34734 produc
This patch is mostly mechanical:
Add some comment, break long lines, use CONST_INT_P instead of
CONST_INT == GET_CODE().
The targetm initializer is moved down in the file similar to m32c,
s390, alpha, etc. back ends.
That way a hook can be defined on the fly:
static foo_t
foo_hook (foo_args)
{
avr_insert_attributes uses TREE_READONLY on get readonlyness of node.
That does not work for C++ arrays: it gives false error
"variable must be const in order to be put into read-only section by
means of '__attribute__((progmem))'".
This patch peels arrays and uses TYPE_READONLY.
I did not open
The new count leading signs is not implemented for HI:
builtin-bitops-1.c:(.text+0xd1e): undefined reference to `__clrsbhi2'
FAIL: gcc.c-torture/execute/builtin-bitops-1.c compilation, -O0
Extended clz/ctz support in longlong.h
With the patch testcase passes.
Johann
libgcc/
* config/a
Weddington, Eric wrote:
>> -Original Message-
>>> You can backport it if you want.
>>>
>>> I'm usually didn't backport such patches.
>>>
>>> Denis.
>> Ok, maybe Eric or Anatoly have some preference for 4.5/4.6.
>
> I would like it for the 4.6 series, if possible. I think that the
> next
Some runtime and checks for error/warning for C/C++.
Is
./testsuite/gcc.target/avr/
realm of avr port maintainers?
Johann
testsuite/
* gcc.target/avr/avr.exp: Run over cpp files, too.
* gcc.target/avr/torture/avr-torture.exp: Ditto.
* gcc.target/avr/progmem-error-1.c: N
Georg-Johann Lay schrieb:
Some runtime and checks for error/warning for C/C++.
...
testsuite/
* gcc.target/avr/torture/progmem.h: New file.
* gcc.target/avr/torture/exit-abort.h: New file.
maybe it's better to have the .h files one level up like so?
* gcc.targe
Georg-Johann Lay wrote:
> Some runtime and checks for error/warning for C/C++.
Note that some tests fail because of pending
http://gcc.gnu.org/ml/gcc-patches/2011-06/msg02318.html
Johann
testsuite/
* gcc.target/avr/avr.exp: Run over cpp files, too.
* gcc.target/avr/torture/
Georg-Johann Lay wrote:
http://gcc.gnu.org/ml/gcc-patches/2011-06/msg02318.html
> avr_insert_attributes uses TREE_READONLY on get readonlyness of node.
>
> That does not work for C++ arrays: it gives false error
> "variable must be const in order to be put into read-only sect
The current implementation of __builtin_avr_fmul/fmuls/fmulsu has a
gap if no hardware multiplier is available.
This patch closes that gap by providing libgcc implementations named
__fmul, __fmuls resp. __fmulsu.
The implementations yield the same result as respective FMUL*
instructions and have
There are still testcase that break on targets with int < 32 bits.
CCed contributors.
Johann
* gcc.dg/pr44023.c: Add dg-require-effective-target int32plus
* gcc.dg/pr43402.c: Ditto.
Index: gcc.dg/pr43402.c
===
--- gc
There is a testcase that fails if no openmp is available.
This patch fixed that.
CCed contributor.
Johann
* gcc.dg/cpp/pragma-3.c: Add dg-require-effective-target fopenmp.
Index: gcc.dg/cpp/pragma-3.c
===
--- gcc.dg/cpp/pr
Mike Stump wrote:
> On Jul 5, 2011, at 3:07 AM, Georg-Johann Lay wrote:
>> There is a testcase that fails if no openmp is available.
>>
>> This patch fixed that.
>>
>> CCed contributor.
>
> Not quite sure what this means.
>
> So, on patches you
For loading a 32-bit constant in a register, there is room for
improvement:
* SF can be handled the same way as SI and therefore the patch
adds a peep2 to produce a *reload_insf analogon to *reload_insi.
* If the destination register overlaps NO_LD_REGS, values already
loaded into some other
AVR tests will fail if -fprofile-generate is given because that is not
(yet) implemented.
CCed avr port maintainer in the case they have objections.
Ok to commit?
Johann
* lib/target-supports.exp (check_profiling_available): Disable
profiling with -fprofile-generate for target a
Rainer Orth wrote:
> Georg-Johann Lay writes:
>
>> Index: lib/target-supports.exp
>> ===
>> --- lib/target-supports.exp (revision 175811)
>> +++ lib/target-supports.exp (working copy
Denis Chertykov wrote:
> 2011/7/6 Georg-Johann Lay :
>> For loading a 32-bit constant in a register, there is room for
>> improvement:
>>
>> * SF can be handled the same way as SI and therefore the patch
>> adds a peep2 to produce a *reload_insf analogo
Hi, I am struggling against hundreds of fails in the testsuite because
many cases are not carefully written, e.g. stull like shifting an int
by 19 bits if int is only 16 bits wide.
This patch adds some additional tests to avoid FAILs that are confusing.
Sorry for gathering it in one patch, other
Denis Chertykov wrote:
> 2011/7/6 Georg-Johann Lay :
>> Denis Chertykov wrote:
>>> 2011/7/6 Georg-Johann Lay :
>>>> For loading a 32-bit constant in a register, there is room for
>>>> improvement:
>>>>
>>>> * SF can be handle
Denis Chertykov wrote:
> I have asked about example of *d instead of !d.
> Just svn GCC with *d vs svn GCC !d.
>
> Denis.
Is the patch ok with the original !d instead of *d ?
It still improves and the !d vs. *d don't matter because there's
always r I think.
Johann
Georg-Johann Lay wrote:
> Hi, I am struggling against hundreds of fails in the testsuite because
> many cases are not carefully written, e.g. stull like shifting an int
> by 19 bits if int is only 16 bits wide.
>
> This patch adds some additional tests to avoid FAILs tha
Denis Chertykov wrote:
> 2011/6/27 Georg-Johann Lay:
>> Denis Chertykov wrote:
>>> The main problem for me is that the new addressing mode produce a
>>> worse code in many tests.
>> You have an example source?
>
> In attachment.
>
> Denis.
Hi
CCed Eric and Bernd.
Denis Chertykov wrote:
>> Did you decide about the fix for PR46779?
>>
>> http://gcc.gnu.org/ml/gcc-patches/2011-06/msg00810.html
>>
>> Is it ok to commit?
>
> I forgot about testsuite regressions for this patch.
>
> Denis.
There were no new regressions:
http://gcc.gnu.o
Denis Chertykov wrote:
> 2011/7/8 Georg-Johann Lay :
>> CCed Eric and Bernd.
>>
>> Denis Chertykov wrote:
>>>> Did you decide about the fix for PR46779?
>>>>
>>>> http://gcc.gnu.org/ml/gcc-patches/2011-06/msg00810.html
>>>>
>&
http://gcc.gnu.org/viewcvs?view=revision&revision=176041
Committed this patchlet as pre-approved by Denis.
Johann
* config/avr/avr.c (output_reload_insisf): Use 'REG_Z+1' instead
of magic '31'.
--- trunk/gcc/config/avr/avr.c 2011/07/08 13:03:38 176040
+++ trunk/gcc/config/
There are tests in suite that set -fschedule-insns[2] and FAIL because of
warning: instruction scheduling not supported on this target machine
[enabled by default]
As there is no individual switch do disable the warning, the patch
disables some test cases so reduce the overall "noise of false tes
These tests are too big for AVR: .text (128 KiB) overflows and ld
complains.
Ok to commit?
Johann
* gcc.dg/compat/struct-by-value-16_main.c: Skip AVR.
* gcc.dg/compat/struct-by-value-17_main.c: Skip AVR.
* gcc.dg/compat/struct-by-value-18_main.c: Skip AVR.
* g++.d
char >> 7 is compiled to
LSL reg
SBC reg,reg
which leaves cc0 in a mess because Z-flag is not set by SBC, it's
propagated from LSL.
Patch as obvious, new testcase pass and contains *cmpqi.
Ok to commit?
Johann
gcc/
PR target/39633
* config/avr/avr.c (notice_update_cc): For as
Mike Stump wrote:
> On Jul 8, 2011, at 7:57 AM, Georg-Johann Lay wrote:
>> These tests are too big for AVR: .text (128 KiB) overflows and ld
>> complains.
>>
>> Ok to commit?
>
> Ok. If people feel they have a nice design for `too big', let us
> know..
Backported to 4.6:
http://gcc.gnu.org/viewcvs?view=revision&revision=176143
Backported fix for PR46779 to 4.6:
http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=176055
For widening multiply there is room for optimization, e.g.:
* (mult:HI (extend:HI(QI)) HI) is better than
(extend:HI(QI)) and (mult:HI HI HI)
* For mult with power of 2 sometimes a mult is
better than a shift left.
* Support MULSU instruction, i.e.
(mult:HI (sign_extend:HI(QI))
Andrew Stubbs wrote:
> On 12/07/11 11:35, Georg-Johann Lay wrote:
>> +(define_insn "*mulsu"
>> + [(set (match_operand:HI 0
>> "register_operand" "=r")
>> +(mult:HI (sign_extend:HI (match_operand:QI 1
>>
Bernd Schmidt wrote:
> On 07/12/11 13:04, Andrew Stubbs wrote:
>> On 12/07/11 11:35, Georg-Johann Lay wrote:
>>> +(define_insn "*mulsu"
>>> + [(set (match_operand:HI 0
>>> "register_operand" "=
This is a patch to fix PR49487.
As Denis will be off-line for some time, it'd be great if
a global reviewer would review it. It appears that he is
the only AVR maintainer who approves patches.
The reason for the ICE is as explained in the PR:
Rotate pattern use "X" as constraint for an operand
Richard Guenther wrote:
> On Wed, Jul 13, 2011 at 3:13 PM, Andreas Krebbel
> wrote:
>> Hi,
>>
>> the widening_mul pass might increase the number of multiplications in
>> the code by transforming
>>
>> a = b * c
>> d = a + 2
>> e = a + 3
>>
>> into:
>>
>> d = b * c + 2
>> e = b * c + 3
>>
>> under
This patch removes some special treatment from avr/elf.h
which is actually not needed. The only target supported
by avr is ELF and the defaults for READONLY_DATA_SECTION_ASM_OP,
TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, and TARGET_ASM_SELECT_SECTION
are fine.
Using default for TARGET_ASM_SELECT_SECTIO
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01036.html
Georg-Johann Lay wrote:
> This is a patch to fix PR49487.
Forgot to attach it. Here it is.
> As Denis will be off-line for some time, it'd be great if
> a global reviewer would review it. It appears that he is
> the on
This patchlet fixes two test cases:
* gcc.dg/pr32912-2.c: TImode is overkill for AVR.
* gcc.dg/pr44674.c: Test if -fprofile-generate is available.
Ok to commit?
Johann
testsuite/
* gcc.dg/pr32912-2.c: Skip for AVR.
* gcc.dg/pr44674.c: Add dg-require-profiling.
Index: gcc.dg/pr
This patch improves 16=8*8 and 16*16*8 multiplication.
mulhi3 is extended to care for small, signed 9-bit constants
that can be handled more efficiently than loading the constants
and performing a 16-bit multiplication.
Some combine patterns are added to match if one operand is a small
constant w
Richard Henderson wrote:
> On 07/18/2011 08:41 AM, Georg-Johann Lay wrote:
>> +(define_insn_and_split "*muluqihi3.uconst"
>> + [(set (match_operand:HI 0 "register_operand" "=r")
>> +(mult:HI (zero_exte
Richard Henderson schrieb:
On 07/18/2011 11:05 AM, Georg-Johann Lay wrote:
What's bad with pre-reload splits?
The only weak point is in target-independent code because there
is nothing like split1_completed and other missing information
for better pass-awareness.
Nothing's wron
Vladimir Makarov wrote:
> On 07/18/2011 04:14 PM, Richard Henderson wrote:
>> On 07/18/2011 12:15 PM, Georg-Johann Lay wrote:
>>>> However, what you've done is try very hard to work around reload
>>>> doing the Right Thing with constant spilling, namely re-
Richard Henderson wrote:
> On 07/18/2011 12:15 PM, Georg-Johann Lay wrote:
>> Moreover, I wonder why target-independent code does not already
>> catch the situation because the pattern to be generated is just
>> an ordinary umulqihi3 widening multiplication.
>
> Yes,
Richard Henderson wrote:
> On 07/18/2011 08:41 AM, Georg-Johann Lay wrote:
>> +(define_insn_and_split "*muluqihi3.uconst"
>> + [(set (match_operand:HI 0 "register_operand" "=r")
>> +(mult:HI (zero_exte
Vladimir Makarov wrote:
> On 07/19/2011 04:13 AM, Georg-Johann Lay wrote:
>> Vladimir Makarov wrote:
>>> On 07/18/2011 04:14 PM, Richard Henderson wrote:
>>>> On 07/18/2011 12:15 PM, Georg-Johann Lay wrote:
>>>>>> However, what you've done is
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01411.html
Richard Henderson wrote:
> On 07/18/2011 08:41 AM, Georg-Johann Lay wrote:
>> +(define_insn_and_split "*muluqihi3.uconst"
>> + [(set (match_operand:HI 0 "register_operand" "=
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01166.html
Georg-Johann Lay wrote:
> This patchlet fixes two test cases:
>
> * gcc.dg/pr32912-2.c: TImode is overkill for AVR.
> * gcc.dg/pr44674.c: Test if -fprofile-generate is available.
>
> Ok to commit?
>
&g
This is a mini-patch to fix rtx_costs for SYMBOL_REF.
The cost of a SYMBOL_REF is the same as a CONST_INT because it can be
used the same way. I observed small performance regression in my code
and found that the reason is too high cost for SYMBOL_REF.
char x[10];
char getx2 (unsigned char i, u
Richard Henderson wrote:
> On 07/20/2011 07:16 AM, Georg-Johann Lay wrote:
>> case CONST_INT:
>> case CONST_DOUBLE:
>> +case SYMBOL_REF:
>>/* Immediate constants are as cheap as registers. */
>>*total = 0;
>>return true;
This patch fixes the debug output of rtx_costs as enabled with -mdeb.
rtx_costs are typically computed for SET_SRC of patters, not of pattern/insn
as a whole resp for SETs.
This patch yields more accurate dumps of rtx_costs in asm file.
Ok?
Johann
* config/avr/avr.c (final_prescan_insn
This is the second part for a better widening multiply for AVR,
namely widening to 32 bit when a MUL instructions are available.
This as a bit more complicated than the 16-bit case because the
multiplications are emit as implicit libgcc calls and involve
hard registers. Thus, all splits and expan
This is a fix for pathological, variable shift offset shifts of
the form x << x resp. x >> x.
Such shifts need a shift register which might overlap with the
shift operand.
unsigned char shift (unsigned int x)
{
return x << x;
}
Without patch, note r24 is part of operand and used in loop:
s
Weddington, Eric wrote:
>
>> Eric, can you review the assembler routines and say if such reuse is ok or
>> if you'd prefer a
>> speed-optimized version of __mulsi3 like in the current libgcc?
>
> Hi Johann,
>
> Typically a penalty on speed is preferred over a penalty on code size. Do you
> alr
This is an optimization for 8-bit shifts if the high part is unused.
Variable shift offset shifts are tedious on AVR because these devices
can just shift by 1.
If the high part of a shift is unused, the high part need not to be
computed, i.e. the 16-bit shift can be mapped to a 8-bit shift.
Most
Eric Weddington a écrit:
__umulhisi3 reads:
DEFUN __umulhisi3
mul A0, B0
movwC0, r0
mul A1, B1
movwC2, r0
mul A0, B1
add C1, r0
adc C2, r1
clr __zero_reg__
adc C3, __zero_reg__
mul A1, B0
add C1, r0
adc C2, r1
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02186.html
Richard Henderson wrote:
> On 07/25/2011 10:30 AM, Georg-Johann Lay wrote:
>> PR target/29560
>> * config/avr/avr.md: Add peephole2 to map ashlhi3 to ashlqi3 if
>> high part of shift target is unused.
>
Georg-Johann Lay wrote:
> I found that too painful, and on devices with >= 8k flash the
> self-tail-call will just save 4 bytes.
That' not correct: even on devices >= 8k an rcall will always reach
the destination, so that the self tail-call always saves 6 bytes.
Johann
Richard Henderson wrote:
> On 07/26/2011 02:48 AM, Georg-Johann Lay wrote:
>> Moreover, the original peep2 is not fully correct because it
>> maps a 16-bit shift to a 8-bit one. The correct mapping is
>>
>> (set (match_dup 2)
>> (subreg:QI (ashif
Richard Henderson wrote:
> On 07/26/2011 10:26 AM, Georg-Johann Lay wrote:
>> If -mint8 (word_mode = QImode) ever returns resp. is turned
>> functional again, then the QI version is undefined for
>> offsets >= 8 whereas the HI version is only undefined for
>> offsets
Joseph S. Myers wrote:
> On Tue, 26 Jul 2011, Georg-Johann Lay wrote:
>
>> I once ran into trouble because there seems to be no clear
>> separation between undefinedness in C and undefinedness in RTL
>>
>> Starting thread from here,
>> http://gcc.gnu.o
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02113.html
Weddington, Eric wrote:
>
>> -Original Message-
>> From: Georg-Johann Lay
>>
>> This means that a pure __mulsi3 will have 30+30+20 = 80 bytes (+18).
>>
>> If all functions are used they
Richard Henderson wrote:
> On 07/27/2011 06:21 AM, Georg-Johann Lay wrote:
>> +(define_insn_and_split "*mulsi3"
>> + [(set (match_operand:SI 0 "pseudo_register_operand"
>> "=r")
>> +(mult:SI (match_o
This patch is to finalize the work on PR49313, i.e. better libgcc
implementation of some functions like bswap, counting zeros,
parity and popcount.
These functions are already implemented in libgcc.
This patch now provides a better integration of these functions:
the calls are no more emit as ord
Richard Henderson wrote:
>> +;; "*ashluqihiqi3.mem"
>> +;; "*ashlsqihiqi3.mem"
>> +(define_insn_and_split "*ashlqihiqi3.mem"
>> + [(set (match_operand:QI 0 "memory_operand" "=m")
>> +(subreg:QI (ashift:HI (any_extend:HI (match_operand:QI 1
>> "register_operand" "r"))
>> +
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02391.html
Richard Henderson schrieb:
On 07/27/2011 08:57 AM, Georg-Johann Lay wrote:
You'll probably end up with quite a few register classes
out of this, but hopefully reload can do a better job than
you can manually...
Agreed.
insns
Weddington, Eric wrote:
>> Subject: Re: [Patch,AVR]: PR49687 (better widening 32-bit mul)
>>
>>> I didn't review the asm code, but the rest of the patch look ok to me.
>>>
>>> r~
>> Thanks, Eric will review the asm part :-)
>
> LOL
> I trust you on the asm stuff. Ok by me.
Ok, I installed it. D
6835 from trunk
2011-07-27 Georg-Johann Lay
Index: config/avr/libgcc.S
===
--- config/avr/libgcc.S (revision 176864)
+++ config/avr/libgcc.S (working copy)
@@ -1074,15 +1074,9 @@ ENDF __ffssi2
;; clobbers: r26
DEFUN __ff
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02424.html
Richard Henderson wrote:
> On 07/27/2011 09:12 AM, Georg-Johann Lay wrote:
>> PR target/49313
>> * config/avr/libgcc.S (__ffshi2): Don't skip 2-word instruction.
>> (__ctzsi2): Result for 0 may be un
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02391.html
(reg:DI 18) does not cover (reg:HI 26) which also contributes to
the register footprint of implicit libgcc calls.
I should return to elementary school and learn counting again...
Installed as obvious, passed without regressions.
http://gcc
Richard Henderson wrote:
> On 07/27/2011 06:21 AM, Georg-Johann Lay wrote:
>> +(define_insn_and_split "*mulsi3"
>> + [(set (match_operand:SI 0 "pseudo_register_operand"
>> "=r")
>> +(mult:SI (match_o
Richard Henderson wrote:
> On 07/27/2011 10:00 AM, Georg-Johann Lay wrote:
>> Richard Henderson wrote:
>>>> +;; "*ashluqihiqi3.mem"
>>>> +;; "*ashlsqihiqi3.mem"
>>>> +(define_insn_and_split "*ashlqihiqi3.mem"
>&g
This is Denis' work from http://codereview.appspot.com/4674046/
updated to current trunk in order to resume work on that PR.
I removed some changes from the patch (which originated in my original patch)
that are avr backend cleanups and don't deal with this fake X addressing PR.
Likewise the fix
Some AVR devices have the skip bug, i.e. they must not use any skip
instruction to bypass a 2-word instruction.
Affected devices are AT90S8515 (core avr2) and ATmega103 (core avr31).
For information see the new file errata.txt.
This patch supplies new built-in macros so that a user can test if t
Some files had wrong svn:executable property, I fixed that.
http://gcc.gnu.org/viewcvs?view=revision&revision=177039
Johann
* config/avr/avr-devices.c: Delete SVN property svn:executable.
* config/avr/predicates.md: Ditto.
* config/avr/driver-avr.c: Ditto.
* confi
Weddington, Eric wrote:
>> -Original Message-
>> From: Georg-Johann Lay [mailto:a...@gjlay.de]
>> Sent: Monday, August 01, 2011 8:38 AM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Anatoly Sokolov; Denis Chertykov; Weddington, Eric
>> Subject: [Patch,AVR]: Sup
Richard Henderson schrieb:
This is related primarily to PR49864 but also to PR49879.
The fundamental problem in the first test case is that the
AVR target cannot perform
(set (stack-pointer-rtx)
(plus (stack-pointer-rtx) (const_int large)))
where "large" is in fact really quite smal
Richard Henderson wrote:
> Dang, forgot to add gcc-patches...
>
> Original Message
> Subject: [AVR] Fix PR49881
>
> The following iteration fixes the two regressions reported
> in comment 7 of the PR.
>
> These were ICEs due to emit_push_insn_single being "helpful"
> with pushi
Added myself to MAINTAINERS.
Please update your MAINTAINERS file.
Johann
Index: ChangeLog
===
--- ChangeLog (Revision 172381)
+++ ChangeLog (Revision 172382)
@@ -1,3 +1,7 @@
+2011-04-13 Georg-Johann Lay
PR target/45263
* config/avr/libgcc.S (__do_global_ctors, __do_global_dtors): Don't use
r20 around calls of __tablejump_elpm__
http://gcc.gnu.org/viewcvs?view=revision&revision=172384
http://gcc.gnu.org/viewcvs?view=revision&revision=172385
Index: config/avr/libgcc.S
==
Georg-Johann Lay
* gcc.target/avr/trivial.c: Fix line endings. Make PROGMEM
variables const.
* gcc.target/avr/torture/trivial.c: Ditto.
Index: gcc.target/avr/torture/trivial.c
===
--- gcc.target/avr/torture
testsuite:
gcc.target/avr/torture/pr41885.c generates these patterns
Johann
2011-04-14 Georg-Johann Lay
* config/avr/avr.md ("rotlhi3", "rotlsi3", "rotldi3"): Fix
expanders operand 3 from match_operand to match
This tests are intended to reveal the respective PRs because the test
case is more stable under slight variations in code (both of
application or compiler).
This test case migh also be helpful for older versions of avr-gcc, in
particular if PR41894 is actually fixed.
2011-04-14 Georg-Johann Lay
This patchlet adds -finline-limit=0 to dg-options in
testsuite/gcc.target/avr/torture/pr41885.c
because otherwise optimizers will fold all tests and actually no test
function is called when optimization is on. The test case still passes
all tests.
testsuite/
2011-04-14 Georg-Johann Lay
Denis Chertykov schrieb:
> 2011/4/14 Georg-Johann Lay :
>> This tests are intended to reveal the respective PRs because the test
>> case is more stable under slight variations in code (both of
>> application or compiler).
>>
>> This test case migh also be helpful
Denis Chertykov schrieb:
> 2011/4/14 Georg-Johann Lay :
>> The "rotl3" expanders (mode \in {HI,SI,DI}) violates synopsis by
>> using 4 operands instead of 3. This runs in ICE in top of
>> optabs.c:maybe_gen_insn.
>>
>> The right way to do this is to use
Richard Guenther schrieb:
> On Thu, Apr 14, 2011 at 8:14 PM, Denis Chertykov wrote:
>> 2011/4/14 Georg-Johann Lay :
>>> This patchlet adds -finline-limit=0 to dg-options in
>>>
>>> testsuite/gcc.target/avr/torture/pr41885.c
>>>
>>> because ot
Denis Chertykov schrieb:
> 2011/4/14 Georg-Johann Lay :
>> Denis Chertykov schrieb:
>>> 2011/4/14 Georg-Johann Lay :
>>>> The "rotl3" expanders (mode \in {HI,SI,DI}) violates synopsis by
>>>> using 4 operands instead of 3. This runs in ICE i
Denis Chertykov schrieb:
> 2011/4/17 Denis Chertykov :
>> 2011/4/15 Georg-Johann Lay :
>>> Finally, I exposed alternative #3 of the insns to the register
>>> allocator, because it is not possible to distinguish between
>>> overlapping or non-overlapping
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