On 9/7/2023 6:19 AM, Jeff Law wrote:
On 9/6/23 11:50, Edwin Lu wrote:
This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
And this is fine. But hold off
/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs
Edwin Lu (5):
RISC-V: Update Types for Vector Instructions
RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Remove
: Edwin Lu
---
Changes in V2:
- Add types to insns missed by prev version
---
gcc/config/riscv/autovec-opt.md | 72 ++---
gcc/config/riscv/autovec.md | 52
2 files changed, 83 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv
This patch adds types to the untyped zc instructions. Creates a new
types "pushpop" and "mvpair" for now
gcc/ChangeLog:
* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types
Signed-off-by: Edwin Lu
---
Changes in V2:
- Chan
On 9/10/2023 8:37 AM, Jeff Law via Gcc-patches wrote:
On 8/31/23 11:36, Edwin Lu wrote:
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left
without a type
On 9/8/2023 4:56 PM, Jeff Law via Gcc-patches wrote:
On 9/8/23 12:16, Edwin Lu wrote:
This patch adds types to vector instructions that were added after or
were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
gcc/ChangeLog:
* config/riscv
On 9/7/2023 6:17 AM, Jeff Law via Gcc-patches wrote:
On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:
Looks okay to me but will need to resolve merge conflicts after commit
af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
'Zicond' support").
Sure. We allow trival updates t
On 9/6/2023 4:23 PM, Kito Cheng via Gcc-patches wrote:
LGTM
Edwin Lu 於 2023年9月7日 週四 01:52 寫道：
This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
gcc/ChangeLog:
* config
Updates autovec instruction that was added after last patch and turns on the
assert statement to ensure all new instructions have a type.
* config/riscv/autovec-opt.md: Update type
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
Signed-off-by: Edwin Lu
-align-4.c: ditto
* gcc.target/riscv/predef-align-5.c: ditto
* gcc.target/riscv/predef-align-6.c: ditto
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv-c.cc | 6 +++---
gcc/testsuite/gcc.target/riscv/attribute-1.c| 10 +-
gcc/testsuite/gcc.target
Committed!
On 11/15/2023 11:34 PM, Kito Cheng wrote:
ohhh, thanks for fixing that, LGTM!
On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu wrote:
Fix __riscv_unaligned_fast/slow/avoid macro name to
__riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec
gcc/ChangeLog
On 9/11/2023 5:49 PM, Jeff Law via Gcc-patches wrote:
On 9/11/23 16:52, Edwin Lu wrote:
Updates autovec instruction that was added after last patch and turns
on the
assert statement to ensure all new instructions have a type.
* config/riscv/autovec-opt.md: Update type
* config/riscv
Hi Juzhe,
I was testing this patch and found it introduced a gfortran regression
in gfortran.dg/host_assoc_function_7.f90. More info here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545
Edwin
On 9/20/2023 7:17 PM, Juzhe-Zhong wrote:
Support INT <-> FP VLS auto-vectorization patterns.
Support for recognizing B as the collection of zba, zbb, zbs extensions
https://github.com/riscv/riscv-b/tags
Edwin Lu (2):
RISC-V: Add support for B standard extension
RISC-V: Update testsuite to use b
gcc/testsuite/ChangeLog:
gcc/common/config/riscv/riscv-common.cc | 6
extension
* config/riscv/arch-canonicalize: Ditto
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 6 ++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 7 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch
Signed-off-by: Edwin Lu
---
gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C | 2
Support for recognizing B as the collection of zba, zbb, zbs extensions
https://github.com/riscv/riscv-b/tags
V2: add b to riscv_combine_info
Edwin Lu (2):
RISC-V: Add support for B standard extension
RISC-V: Update testsuite to use b
gcc/common/config/riscv/riscv-common.cc
extension
* config/riscv/arch-canonicalize: Ditto
Signed-off-by: Edwin Lu
---
V2: Add b to riscv_combine_info
---
gcc/common/config/riscv/riscv-common.cc | 7 +++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv
riscv/synthesis-7.c: Ditto
* gcc.target/riscv/synthesis-8.c: Ditto
* gcc.target/riscv/zba_zbs_and-1.c: Ditto
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch
Signed-off-by: Edwin Lu
---
V2: no change
---
gcc/testsuite/g++.target/
Committed!
Edwin
On 7/9/2024 12:07 PM, Jeff Law wrote:
On 7/9/24 11:44 AM, Edwin Lu wrote:
This patch adds support for recognizing the B standard extension to
be the
collection of Zba, Zbb, Zbs extensions for consistency and
conciseness across
toolchains
* https://github.com/riscv/riscv
Hi Pan,
This patch appears to be tripping up our postcommit for building linux
with vector https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1325.
FAIL: gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c
execution test
Looking at the logs, the test fails due to the __builtin
/binop/vec_sat_binary_vx.h:
initialize variable
Signed-off-by: Edwin Lu
---
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h | 1 +
1 file changed, 1 insertion(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
b/gcc/testsuite/gcc.target
Committed!
Edwin
On 7/12/2024 3:40 PM, Jeff Law wrote:
On 7/12/24 12:37 PM, Edwin Lu wrote:
The following testcase was not properly testing anything due to an
uninitialized variable. As a result, the loop was not iterating through
the testing data, but instead on undefined values which
The C + F extentions implies the zcf extension on rv32. Add missing zcf
extension for the rv32 target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr-16.c: Update expected assembly
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
1 file
Committed! Thanks!
Edwin
On 7/17/2024 1:14 AM, Kito Cheng wrote:
LGTM :)
On Wed, Jul 17, 2024 at 9:15 AM Edwin Lu wrote:
The C + F extentions implies the zcf extension on rv32. Add missing zcf
extension for the rv32 target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr
Some testcases still had --param=riscv-autovec-preference=_,
update to use -mrvv-vector-bits=_. Also add missing period
in riscv.opt which caused a compiler driver error.
gcc/ChangeLog:
* config/riscv/riscv.opt: Add missing period
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/
Thanks!
Edwin
On 8/8/2024 12:24 AM, Robin Dapp wrote:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index d150f20b5d9..02814183dbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
+++ b/gcc/
The testcase has been modified to include the -fwrapv flag which now
causes the test to pass. Remove the xfail exception
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: Remove riscv xfail exception
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 -
1 file changed, 1
Thanks!
Edwin
On 8/19/2024 1:17 PM, Jeff Law wrote:
On 8/19/24 2:14 PM, Edwin Lu wrote:
The testcase has been modified to include the -fwrapv flag which now
causes the test to pass. Remove the xfail exception
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: Remove riscv xfail exception
Hi,
Just wanted to ping this for more guidance.
Edwin
On 7/24/2024 12:03 PM, Edwin Lu wrote:
On 7/24/2024 3:52 AM, Richard Biener wrote:
On Wed, Jul 24, 2024 at 1:31 AM Edwin Lu wrote:
On 7/23/2024 11:20 AM, Richard Sandiford wrote:
Edwin Lu writes:
On 7/23/2024 4:56 AM, Richard
On 8/22/2024 5:35 AM, Richard Biener wrote:
On Thu, Aug 22, 2024 at 1:03 AM Edwin Lu wrote:
Hi,
Just wanted to ping this for more guidance.
It's difficult for me as long as I cannot investigate this with a testcase. Can
we go ahead with the other parts so the testcase can be added an
bug and also robustify our emit_insn by making an assertion
check unconditional
I'm not sure if this ICE warrants its own separate testcase since it is
already being tested. I do have a minimal testcase on hand if we would
like to add one.
Edwin Lu (2):
RISC-V: Fix vwsll combine on rv32 ta
/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
gcc/config/riscv/autovec-opt.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6a2eabbd854..b9e5ccfe
that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.
Make the assert unconditional
gcc/ChangeLog:
* config/riscv/riscv-v.cc: Move assert out of conditional block
Signed-off-by: Edwin Lu
---
gcc/co
Hi Robin,
I did a test run without the subreg condition and it also appears to
work when running on rv32gcv and rv64gcv newlib. Would it be better to
remove the subreg?
Edwin
On 6/12/2024 12:42 AM, Robin Dapp wrote:
Hi Edwin,
this is OK but did you check if we can get rid of the subreg
con
On 6/12/2024 12:39 AM, Robin Dapp wrote:
Hi Edwin,
this LGTM but I just remembered I intended to turn the assert
into a more descriptive error.
The attached patch has been sitting on my local branch for a
while. Maybe we should rather fold yours into it?
That's fine with me! Having more desc
ernal error
Edwin Lu (2):
RISC-V: Fix vwsll combine on rv32 targets
RISC-V: Move mode assertion out of conditional branch in emit_insn
gcc/config/riscv/autovec-opt.md | 3 +--
gcc/config/riscv/riscv-v.cc | 25 +++--
2 files changed, 20 insertions(+), 8 dele
/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: Remove subreg check
---
gcc/config/riscv/autovec-opt.md | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/ris
ert out of conditional block
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: change assert to internal error
---
gcc/config/riscv/riscv-v.cc | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/
ernal error
V3: Update the _trunc_scalar splitter as well
Edwin Lu (2):
RISC-V: Fix vwsll combine on rv32 targets
RISC-V: Move mode assertion out of conditional branch in emit_insn
gcc/config/riscv/autovec-opt.md | 6 ++
gcc/config/riscv/riscv-v.cc | 25 +++--
2
v32/64 gcv newlib. Letting CI perform additional testing
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: Remove subreg check
V3: Update _trunc_scalar splitter as well
---
gcc/config/riscv/autovec-opt.md | 6
ert out of conditional block
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: change assert to internal error
V3: No change
---
gcc/config/riscv/riscv-v.cc | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/
Committed. Thanks!
Edwin
On 6/17/2024 5:31 PM, Jeff Law wrote:
On 6/17/24 12:33 PM, Edwin Lu wrote:
On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI
Thanks!
Edwin
On 6/17/2024 5:33 PM, Jeff Law wrote:
On 6/17/24 12:33 PM, Edwin Lu wrote:
When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does n
Hi Kito,
On 7/22/2024 8:19 AM, Kito Cheng wrote:
Corresponding implementation in compiler-rt already merged in LLVM
side, so I plan to merge this into trunk tomorrow if no strong
objections.
NOTE: This has been tested with clang/llvm within our internal CI.
On Mon, Jul 22, 2024 at 10:16 PM
On 7/23/2024 4:56 AM, Richard Biener wrote:
On Tue, Jul 23, 2024 at 1:03 AM Edwin Lu wrote:
Hi Richard,
On 5/31/2024 1:48 AM, Richard Biener wrote:
On Thu, May 30, 2024 at 2:11 AM Patrick O'Neill wrote:
From: Greg McGary
Still a NACK. If remain ends up zero
On 7/23/2024 11:20 AM, Richard Sandiford wrote:
Edwin Lu writes:
On 7/23/2024 4:56 AM, Richard Biener wrote:
On Tue, Jul 23, 2024 at 1:03 AM Edwin Lu wrote:
Hi Richard,
On 5/31/2024 1:48 AM, Richard Biener wrote:
On Thu, May 30, 2024 at 2:11 AM Patrick O'Neill wrote:
From: Greg M
On 7/24/2024 3:52 AM, Richard Biener wrote:
On Wed, Jul 24, 2024 at 1:31 AM Edwin Lu wrote:
On 7/23/2024 11:20 AM, Richard Sandiford wrote:
Edwin Lu writes:
On 7/23/2024 4:56 AM, Richard Biener wrote:
On Tue, Jul 23, 2024 at 1:03 AM Edwin Lu wrote:
Hi Richard,
On 5/31/2024 1:48 AM
On 7/24/2024 3:03 AM, Robin Dapp wrote:
Thanks for the explanation! I have a few clarification questions about this.
If I understand correctly, B would represent the number of elements the
vector can have (for 128b vector operating on 32b elements, B == 4, but if
operating on 64b elements B ==
On 7/24/2024 3:03 AM, Robin Dapp wrote:
Thanks for the explanation! I have a few clarification questions about this.
If I understand correctly, B would represent the number of elements the
vector can have (for 128b vector operating on 32b elements, B == 4, but if
operating on 64b elements B ==
b in march string
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add B assembler check
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 8 +++
gcc/config.in | 6 +
gcc/conf
Thanks! Committed
Edwin
On 7/29/2024 6:37 AM, Kito Cheng wrote:
LGTM, although I said no binutils check for zacas and zabha, but B is
a different situation since GCC will add that if zba, zbb and zbs are
all present.
On Thu, Jul 25, 2024 at 7:51 AM Edwin Lu wrote:
Binutils 2.42 and before
-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index d150f20b5d9..02814183dbb 100644
From: Greg McGary
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes,
vec_mask_len_store_lanes):
.
* g++.target/riscv/rvv/base/bug-6.C: Ditto.
* g++.target/riscv/rvv/base/bug-7.C: Ditto.
* g++.target/riscv/rvv/base/bug-8.C: Ditto.
* g++.target/riscv/rvv/base/bug-9.C: Ditto.
Signed-off-by: Edwin Lu
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C | 1 -
gcc/testsuite
I took a look at the CI errors today since I remember Jeff checking the
CI output. I don't remember if the errors were the main things blocking
the patch or if there just wasn't any follow up.
I'll look into having the CI output some additional test log information
to make understanding failur
Committed!
Edwin
On 11/11/2024 11:02 AM, Jeff Law wrote:
On 11/11/24 11:16 AM, Edwin Lu wrote:
Since r15-4981-g5c34f02ba7e these tests have been failing on vector
targets with excess errors due to the new deprecation warning message.
Remove the header.
gcc/testsuite/ChangeLog:
* g
.
Signed-off-by: Edwin Lu
---
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr117595.c: Restrict to non vector targets.
Signed-off-by: Edwin
Pushed.
Edwin
On 11/19/2024 1:11 PM, Jeff Law wrote:
On 11/19/24 2:08 PM, Edwin Lu wrote:
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite
: Fix selector.
* gcc.target/riscv/crc-builtin-zbc64.c: Ditto.
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c | 2 +-
gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite
Thanks! Committed.
Edwin
On 1/9/2025 1:04 PM, Jeff Law wrote:
On 1/9/25 11:33 AM, Edwin Lu wrote:
The effective-target selector for riscv on sync_char_short did not
check to see if atomics were enabled. As a result, these test cases were
ran on targets without the a extension. Add
: Fix effective target sync_char_short
for riscv*-*-*
Signed-off-by: Edwin Lu
---
gcc/testsuite/lib/target-supports.exp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index a89f531f887
On 2/13/2025 4:12 AM, Vineet Gupta wrote:
On 2/13/25 14:17, Robin Dapp wrote:
Other thoughts?
The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
we can't/don't model in the pipeline, but I have no idea how to model
the VL=0 case there.
Maybe so, but what Edwin is doing
LATE_INSN): Implement.
* config/riscv/riscv.opt: Add temporary opt.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Signed-off-by: Edwin Lu
---
V2: add testcase
V3: add opt flag to test performance
---
gcc/config/riscv/riscv.cc
igned-off-by: Edwin Lu
---
Changes in V2:
- Add testcase
---
gcc/config/riscv/riscv.cc | 20 +++
.../gcc.target/riscv/rvv/vsetvl/pr117974.c| 16 +++
2 files changed, 36 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl
cessarily updating the vinfo at the end of a basic block.
PR/117974
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_can_speculate_insn):
(TARGET_SCHED_CAN_SPECULATE_INSN): Implement.
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 20 +++
tcase ?
juzhe.zh...@rivai.ai
*From:* Edwin Lu <mailto:e...@rivosinc.com>
*Date:* 2025-02-13 07:27
*To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* gnu-toolchain <mailto:gnu-toolch...@rivosinc.com>; vineetg
<mailto:vine...@rivosinc.com>; juzhe.zhong
): Define Hook.
* config/riscv/riscv.opt: New flag.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Signed-off-by: Edwin Lu
Co-authored-by: Palmer Dabbelt
---
gcc/config/riscv/riscv.cc | 103 ++
gcc/config/r
On 2/24/2025 4:34 PM, Jeff Law wrote:
On 2/24/25 5:07 PM, Edwin Lu wrote:
See [1] thread for original patch which spawned this one.
We are currently seeing the following code where we perform a vsetvl
before a branching instruction against the avl.
vsetvli a5,a1,e32,m1,tu,ma
When the dg brackets were added, they forgot to add the brackets for the
scan-assembler-times directive.
Committed as obvious.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Fix typo
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls
-cst.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv.opt| 2 +
gcc
-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.
Signed-off-by: Edwin Lu
---
v2: fix ztso mappings
- Removed .aq annotation on load acquire
- Removed .rl annotation on store release
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config
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