Oops I made a mental note to add one and then completely forgot. I'll
run the testsuite again with the testcase before sending it up as v2.
Edwin
On 2/12/2025 3:38 PM, 钟居哲 wrote:
Could you add PR117974 testcase ?
------------------------------------------------------------------------
juzhe.zh...@rivai.ai
*From:* Edwin Lu <mailto:e...@rivosinc.com>
*Date:* 2025-02-13 07:27
*To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* gnu-toolchain <mailto:gnu-toolch...@rivosinc.com>; vineetg
<mailto:vine...@rivosinc.com>; juzhe.zhong
<mailto:juzhe.zh...@rivai.ai>; Edwin Lu <mailto:e...@rivosinc.com>
*Subject:* [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5 <-- a1 potentially set to 0
sh2add a0,a5,a0
vfmacc.vv v1,v2,v2
vsetvli a5,a1,e32,m1,tu,ma <-- incompatible vinfo. update
vl to 0
beq a1,zero,.L12 <-- check if avl is 0
This patch would essentially delay the vsetvl update to after the
branch
to prevent unnecessarily updating the vinfo at the end of a basic
block.
PR/117974
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_can_speculate_insn):
(TARGET_SCHED_CAN_SPECULATE_INSN): Implement.
Signed-off-by: Edwin Lu <e...@rivosinc.com>
---
gcc/config/riscv/riscv.cc | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6e14126e3a4..24450bae517 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10209,6 +10209,23 @@ riscv_sched_adjust_cost (rtx_insn *, int,
rtx_insn *insn, int cost,
return new_cost;
}
+/* Implement TARGET_SCHED_CAN_SPECULATE_INSN hook. Return true if
insn can
+ can be scheduled for speculative execution. Reject vsetvl
instructions to
+ prevent the scheduler from hoisting them out of basic blocks
without
+ checking for data dependencies PR117974. */
+static bool
+riscv_sched_can_speculate_insn (rtx_insn *insn)
+{
+ switch (get_attr_type (insn))
+ {
+ case TYPE_VSETVL:
+ case TYPE_VSETVL_PRE:
+ return false;
+ default:
+ return true;
+ }
+}
+
/* Auxiliary function to emit RISC-V ELF attribute. */
static void
riscv_emit_attribute ()
@@ -14055,6 +14072,9 @@ bool need_shadow_stack_push_pop_p ()
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost
+#undef TARGET_SCHED_CAN_SPECULATE_INSN
+#define TARGET_SCHED_CAN_SPECULATE_INSN
riscv_sched_can_speculate_insn
+
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
--
2.43.0
