[1] https://github.com/riscv/riscv-zalasr
[2] https://sourceware.org/pipermail/binutils/2025-March/140065.html
Add minimal support for the zalasr (load-acquire/store-release)
extension
Currently there is no toggle to opt into the abi-breaking note 3
mappings in the PSABI doc so support for that has been omitted from this
patch.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Recognize zalasr.
* config/riscv/riscv.opt: Ditto.
* config/riscv/sync-rvwmo.md: Add check for zalasr.
* config/riscv/sync-ztso.md: Ditto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo/a-rvwmo-fence.c: Disable zalasr from
march if exists.
* gcc.target/riscv/amo/a-rvwmo-load-acquire.c: Ditto.
* gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: Ditto.
* gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: Ditto.
* gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Ditto.
* gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Ditto.
* gcc.target/riscv/amo/a-rvwmo-store-release.c: Ditto.
* gcc.target/riscv/amo/a-ztso-fence.c: Ditto.
* gcc.target/riscv/amo/a-ztso-load-acquire.c:
* gcc.target/riscv/amo/a-ztso-load-relaxed.c: Ditto.
* gcc.target/riscv/amo/a-ztso-load-seq-cst.c: Ditto.
* gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Ditto.
* gcc.target/riscv/amo/a-ztso-store-relaxed.c: Ditto.
* gcc.target/riscv/amo/a-ztso-store-release.c: Ditto.
* gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: Ditto.
* gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: Ditto.
* gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: Ditto.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c:
Ditto.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c:
Ditto.
*
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c:
Ditto.
*
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc:
Ditto.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: Ditto.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: Ditto.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c:
Ditto.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c: Ditto.
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c:
Ditto.
* lib/target-supports.exp: Add zalasr checks.
* gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c: New test.
* gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c: New test.
* gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c: New test.
* gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-rvwmo-store-release.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-load-acquire.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.
Signed-off-by: Edwin Lu <[email protected]>
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/sync-rvwmo.md | 17 +++--
gcc/config/riscv/sync-ztso.md | 17 +++--
.../gcc.target/riscv/amo/a-rvwmo-fence.c | 1 +
.../riscv/amo/a-rvwmo-load-acquire.c | 1 +
.../riscv/amo/a-rvwmo-load-relaxed.c | 1 +
.../riscv/amo/a-rvwmo-load-seq-cst.c | 1 +
.../riscv/amo/a-rvwmo-store-compat-seq-cst.c | 1 +
.../riscv/amo/a-rvwmo-store-relaxed.c | 1 +
.../riscv/amo/a-rvwmo-store-release.c | 1 +
.../gcc.target/riscv/amo/a-ztso-fence.c | 1 +
.../riscv/amo/a-ztso-load-acquire.c | 1 +
.../riscv/amo/a-ztso-load-relaxed.c | 1 +
.../riscv/amo/a-ztso-load-seq-cst.c | 1 +
.../riscv/amo/a-ztso-store-compat-seq-cst.c | 1 +
.../riscv/amo/a-ztso-store-relaxed.c | 1 +
.../riscv/amo/a-ztso-store-release.c | 1 +
.../riscv/amo/zaamo-ztso-amo-add-int.c | 1 +
.../riscv/amo/zabha-ztso-amo-add-char.c | 1 +
.../riscv/amo/zabha-ztso-amo-add-short.c | 1 +
...zacas-ztso-compare-exchange-char-seq-cst.c | 1 +
.../amo/zacas-ztso-compare-exchange-char.c | 1 +
...-exchange-compatability-mapping-no-fence.c | 1 +
...-compare-exchange-compatability-mapping.cc | 1 +
.../zacas-ztso-compare-exchange-int-seq-cst.c | 1 +
.../amo/zacas-ztso-compare-exchange-int.c | 1 +
...acas-ztso-compare-exchange-short-seq-cst.c | 1 +
.../amo/zacas-ztso-compare-exchange-short.c | 1 +
.../riscv/amo/zalasr-rvwmo-load-acquire.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-rvwmo-load-relaxed.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-rvwmo-load-seq-cst.c | 72 +++++++++++++++++++
.../amo/zalasr-rvwmo-store-compat-seq-cst.c | 63 ++++++++++++++++
.../riscv/amo/zalasr-rvwmo-store-relaxed.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-rvwmo-store-release.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-ztso-load-acquire.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-ztso-load-relaxed.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-ztso-load-seq-cst.c | 67 +++++++++++++++++
.../amo/zalasr-ztso-store-compat-seq-cst.c | 63 ++++++++++++++++
.../riscv/amo/zalasr-ztso-store-relaxed.c | 62 ++++++++++++++++
.../riscv/amo/zalasr-ztso-store-release.c | 62 ++++++++++++++++
.../riscv/amo/zalrsc-ztso-amo-add-int.c | 1 +
...tso-compare-exchange-int-acquire-release.c | 1 +
...zalrsc-ztso-compare-exchange-int-acquire.c | 1 +
...zalrsc-ztso-compare-exchange-int-consume.c | 1 +
...zalrsc-ztso-compare-exchange-int-relaxed.c | 1 +
...zalrsc-ztso-compare-exchange-int-release.c | 1 +
...tso-compare-exchange-int-seq-cst-relaxed.c | 1 +
...zalrsc-ztso-compare-exchange-int-seq-cst.c | 1 +
...zalrsc-ztso-subword-amo-add-char-acq-rel.c | 1 +
...zalrsc-ztso-subword-amo-add-char-acquire.c | 1 +
...zalrsc-ztso-subword-amo-add-char-relaxed.c | 1 +
...zalrsc-ztso-subword-amo-add-char-release.c | 1 +
...zalrsc-ztso-subword-amo-add-char-seq-cst.c | 1 +
gcc/testsuite/lib/target-supports.exp | 28 ++++++--
55 files changed, 851 insertions(+), 14 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index b34409adf39..6cd9ea93cdc 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -295,6 +295,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
{"zacas", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zalasr", ISA_SPEC_CLASS_NONE, 0, 3},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1620,6 +1621,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("zalrsc", x_riscv_za_subext, MASK_ZALRSC),
RISCV_EXT_FLAG_ENTRY ("zabha", x_riscv_za_subext, MASK_ZABHA),
RISCV_EXT_FLAG_ENTRY ("zacas", x_riscv_za_subext, MASK_ZACAS),
+ RISCV_EXT_FLAG_ENTRY ("zalasr", x_riscv_za_subext, MASK_ZALASR),
RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA),
RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB),
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7515c8ea13d..1b19413d03d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -270,6 +270,8 @@ Mask(ZABHA) Var(riscv_za_subext)
Mask(ZACAS) Var(riscv_za_subext)
+Mask(ZALASR) Var(riscv_za_subext)
+
Mask(ZA64RS) Var(riscv_za_subext)
Mask(ZA128RS) Var(riscv_za_subext)
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index c523dde0226..43192946fac 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -61,11 +61,15 @@ (define_insn "atomic_load_rvwmo<mode>"
return "fence\trw,rw\;"
"<load>\t%0,%1\;"
"fence\tr,rw";
+
+ if (TARGET_ZALASR && model == MEMMODEL_ACQUIRE)
+ return "<load>.aq\t%0,%1";
+
if (model == MEMMODEL_ACQUIRE)
return "<load>\t%0,%1\;"
"fence\tr,rw";
- else
- return "<load>\t%0,%1";
+
+ return "<load>\t%0,%1";
}
[(set_attr "type" "multi")
(set (attr "length")
@@ -86,15 +90,20 @@ (define_insn "atomic_store_rvwmo<mode>"
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
model = memmodel_base (model);
+ if (TARGET_ZALASR
+ && (model == MEMMODEL_RELEASE || model == MEMMODEL_SEQ_CST))
+ return "<store>.rl\t%z1,%0";
+
if (model == MEMMODEL_SEQ_CST)
return "fence\trw,w\;"
"<store>\t%z1,%0\;"
"fence\trw,rw";
+
if (model == MEMMODEL_RELEASE)
return "fence\trw,w\;"
"<store>\t%z1,%0";
- else
- return "<store>\t%z1,%0";
+
+ return "<store>\t%z1,%0";
}
[(set_attr "type" "multi")
(set (attr "length")
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 254accbac40..43a9a1bac73 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -54,8 +54,13 @@ (define_insn "atomic_load_ztso<mode>"
if (model == MEMMODEL_SEQ_CST)
return "fence\trw,rw\;"
"<load>\t%0,%1";
- else
- return "<load>\t%0,%1";
+
+ /* Ignoring RCsc atomic load-acquire on MEMMODEL_SEQ_CST due to
+ Note 3 abi break. */
+ if (TARGET_ZALASR && model == MEMMODEL_ACQUIRE)
+ return "<load>.aq\t%0,%1";
+
+ return "<load>\t%0,%1";
}
[(set_attr "type" "multi")
(set (attr "length")
@@ -74,11 +79,15 @@ (define_insn "atomic_store_ztso<mode>"
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
model = memmodel_base (model);
+ if (TARGET_ZALASR
+ && (model == MEMMODEL_SEQ_CST || model == MEMMODEL_RELEASE))
+ return "<store>.rl\t%z1,%0";
+
if (model == MEMMODEL_SEQ_CST)
return "<store>\t%z1,%0\;"
"fence\trw,rw";
- else
- return "<store>\t%z1,%0";
+
+ return "<store>\t%z1,%0";
}
[(set_attr "type" "multi")
(set (attr "length")
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
index 6803bf92aa3..3947923e6ea 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
@@ -2,6 +2,7 @@
/* Verify that fence mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
index 93a0c68ae8a..810e7959508 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
@@ -2,6 +2,7 @@
/* Verify that load mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
index 2403d53c131..01a1e3c5c86 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
@@ -2,6 +2,7 @@
/* Verify that load mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
index 31b35cf9f6a..ee728675155 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
@@ -2,6 +2,7 @@
/* Verify that load mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
index 45c9abb1425..b3ec4e1061b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
@@ -3,6 +3,7 @@
mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
index 4b321b2b75f..2f224f993de 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
@@ -2,6 +2,7 @@
/* Verify that store mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
index a2a617c4d15..6daca225d24 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
@@ -2,6 +2,7 @@
/* Verify that store mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
index 153f6ef8a3d..d432cdc2ffc 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
@@ -2,6 +2,7 @@
/* Verify that fence mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
index 76a12059f39..f221169def9 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
@@ -2,6 +2,7 @@
/* Verify that load mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
index c4ee56e2cc0..2ee094679eb 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
@@ -2,6 +2,7 @@
/* Verify that load mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
index 7163311433c..8ad64e6579c 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
@@ -2,6 +2,7 @@
/* Verify that load mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
index 2f4c9124aaf..a1cefbb1109 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
@@ -3,6 +3,7 @@
mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
index d469bf348d9..939ad757462 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
@@ -2,6 +2,7 @@
/* Verify that store mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
index 3a275740401..bb97b8a6d52 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
@@ -2,6 +2,7 @@
/* Verify that store mappings match the PSABI doc's recommended mapping. */
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
index 8ebdc61992e..56122bc1f05 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
@@ -3,6 +3,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_zaamo } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
index bcd7477c673..f3c1a26166f 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
@@ -3,6 +3,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
/* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
index c4e8c9cf3ef..b632094acfe 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
@@ -3,6 +3,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_ztso } */
/* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c
index e219bd14b15..0ab231de94d 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c
@@ -4,6 +4,7 @@
/* { dg-add-options riscv_zabha } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tlr\.w" } } */
/* { dg-final { scan-assembler-not "\tsc\.w" } } */
/* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
index 183dc4020c7..9ede267eea2 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
@@ -4,6 +4,7 @@
/* { dg-add-options riscv_zabha } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tlr\.w" } } */
/* { dg-final { scan-assembler-not "\tsc\.w" } } */
/* { dg-final { scan-assembler-times "amocas\.b\t" 8 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
index 2712eff5107..65b6e392fcf 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
@@ -7,6 +7,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tfence" } } */
void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int
qux)
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
index 560172bfbed..8556837793c 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
+++
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
@@ -7,6 +7,7 @@
/* { dg-options "-O3 -std=c++17" } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { check-function-bodies "**" "" } } */
/*
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
index 1ee6cc20218..766ae162253 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tlr\.w" } } */
/* { dg-final { scan-assembler-not "\tsc\.w" } } */
/* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
index 2c332623a95..6d2a17f9199 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
@@ -3,6 +3,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tlr\.w" } } */
/* { dg-final { scan-assembler-not "\tsc\.w" } } */
/* { dg-final { scan-assembler-times "amocas\.w\t" 8 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
index 1938448183c..7ab8ce0e98f 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
@@ -4,6 +4,7 @@
/* { dg-add-options riscv_zabha } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tlr\.w" } } */
/* { dg-final { scan-assembler-not "\tsc\.w" } } */
/* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
index 69fe5ae3eac..3089e68ab71 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
@@ -4,6 +4,7 @@
/* { dg-add-options riscv_zabha } */
/* { dg-add-options riscv_zacas } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-final { scan-assembler-not "\tlr\.w" } } */
/* { dg-final { scan-assembler-not "\tsc\.w" } } */
/* { dg-final { scan-assembler-times "amocas\.h\t" 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
new file mode 100644
index 00000000000..aea6bc6822a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_acquire:
+** l[wd].aq\t[atx][0-9]+,0\(a0\)
+** s[wd]\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_long_acquire (long* bar, long* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_int_acquire:
+** lw.aq\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_int_acquire (int* bar, int* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_short_acquire:
+** lh.aq\t[atx][0-9]+,0\(a0\)
+** sh\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_short_acquire (short* bar, short* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_char_acquire:
+** lb.aq\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_char_acquire (char* bar, char* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_bool_acquire:
+** lb.aq\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_bool_acquire (_Bool* bar, _Bool* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
new file mode 100644
index 00000000000..eee5f8d5bb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_relaxed:
+** l[wd]\t[atx][0-9]+,0\(a0\)
+** s[wd]\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_long_relaxed (long* bar, long* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_int_relaxed:
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_int_relaxed (int* bar, int* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_short_relaxed:
+** lh\t[atx][0-9]+,0\(a0\)
+** sh\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_short_relaxed (short* bar, short* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_char_relaxed:
+** lb\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_char_relaxed (char* bar, char* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_bool_relaxed:
+** lb\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
new file mode 100644
index 00000000000..54ad19b1071
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_seq_cst:
+** fence\trw,rw
+** l[wd]\t[atx][0-9]+,0\(a0\)
+** fence\tr,rw
+** s[wd]\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_long_seq_cst (long* bar, long* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_int_seq_cst:
+** fence\trw,rw
+** lw\t[atx][0-9]+,0\(a0\)
+** fence\tr,rw
+** sw\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_int_seq_cst (int* bar, int* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_short_seq_cst:
+** fence\trw,rw
+** lh\t[atx][0-9]+,0\(a0\)
+** fence\tr,rw
+** sh\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_short_seq_cst (short* bar, short* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_char_seq_cst:
+** fence\trw,rw
+** lb\t[atx][0-9]+,0\(a0\)
+** fence\tr,rw
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_char_seq_cst (char* bar, char* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_bool_seq_cst:
+** fence\trw,rw
+** lb\t[atx][0-9]+,0\(a0\)
+** fence\tr,rw
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
new file mode 100644
index 00000000000..7f40d443bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended compatibility
+ mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_seq_cst:
+** l[wd]\t[atx][0-9]+,0\(a1\)
+** s[wd].rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_long_seq_cst (long* bar, long* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_int_seq_cst:
+** lw\t[atx][0-9]+,0\(a1\)
+** sw.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_int_seq_cst (int* bar, int* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_short_seq_cst:
+** lhu\t[atx][0-9]+,0\(a1\)
+** sh.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_short_seq_cst (short* bar, short* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_char_seq_cst:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_char_seq_cst (char* bar, char* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_bool_seq_cst:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
new file mode 100644
index 00000000000..d0127e53baa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_relaxed:
+** l[wd]\t[atx][0-9]+,0\(a1\)
+** s[wd]\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_long_relaxed (long* bar, long* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_int_relaxed:
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_int_relaxed (int* bar, int* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_short_relaxed:
+** lhu\t[atx][0-9]+,0\(a1\)
+** sh\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_short_relaxed (short* bar, short* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_char_relaxed:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_char_relaxed (char* bar, char* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_bool_relaxed:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
new file mode 100644
index 00000000000..6174718fe2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_release:
+** l[wd]\t[atx][0-9]+,0\(a1\)
+** s[wd].rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_long_release (long* bar, long* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_int_release:
+** lw\t[atx][0-9]+,0\(a1\)
+** sw.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_int_release (int* bar, int* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_short_release:
+** lhu\t[atx][0-9]+,0\(a1\)
+** sh.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_short_release (short* bar, short* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_char_release:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_char_release (char* bar, char* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_bool_release:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_bool_release (_Bool* bar, _Bool* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
new file mode 100644
index 00000000000..db0895d75ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_acquire:
+** l[wd].aq\t[atx][0-9]+,0\(a0\)
+** s[wd]\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_long_acquire (long* bar, long* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_int_acquire:
+** lw.aq\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_int_acquire (int* bar, int* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_short_acquire:
+** lh.aq\t[atx][0-9]+,0\(a0\)
+** sh\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_short_acquire (short* bar, short* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_char_acquire:
+** lb.aq\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_char_acquire (char* bar, char* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_bool_acquire:
+** lb.aq\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_bool_acquire (_Bool* bar, _Bool* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
new file mode 100644
index 00000000000..ce2c41563a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_relaxed:
+** l[wd]\t[atx][0-9]+,0\(a0\)
+** s[wd]\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_long_relaxed (long* bar, long* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_int_relaxed:
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_int_relaxed (int* bar, int* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_short_relaxed:
+** lh\t[atx][0-9]+,0\(a0\)
+** sh\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_short_relaxed (short* bar, short* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_char_relaxed:
+** lb\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_char_relaxed (char* bar, char* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_bool_relaxed:
+** lb\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
new file mode 100644
index 00000000000..70038f81c13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_seq_cst:
+** fence\trw,rw
+** l[wd]\t[atx][0-9]+,0\(a0\)
+** s[wd]\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_long_seq_cst (long* bar, long* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_int_seq_cst:
+** fence\trw,rw
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_int_seq_cst (int* bar, int* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_short_seq_cst:
+** fence\trw,rw
+** lh\t[atx][0-9]+,0\(a0\)
+** sh\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_short_seq_cst (short* bar, short* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_char_seq_cst:
+** fence\trw,rw
+** lb\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_char_seq_cst (char* bar, char* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_bool_seq_cst:
+** fence\trw,rw
+** lb\t[atx][0-9]+,0\(a0\)
+** sb\t[atx][0-9]+,0\(a1\)
+** ret
+*/
+void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
new file mode 100644
index 00000000000..085f94e5d42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended compatibility
+ mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_seq_cst:
+** l[wd]\t[atx][0-9]+,0\(a1\)
+** s[wd].rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_long_seq_cst (long* bar, long* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_int_seq_cst:
+** lw\t[atx][0-9]+,0\(a1\)
+** sw.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_int_seq_cst (int* bar, int* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_short_seq_cst:
+** lhu\t[atx][0-9]+,0\(a1\)
+** sh.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_short_seq_cst (short* bar, short* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_char_seq_cst:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_char_seq_cst (char* bar, char* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_bool_seq_cst:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
new file mode 100644
index 00000000000..cb68849291b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_relaxed:
+** l[wd]\t[atx][0-9]+,0\(a1\)
+** s[wd]\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_long_relaxed (long* bar, long* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_int_relaxed:
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_int_relaxed (int* bar, int* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_short_relaxed:
+** lhu\t[atx][0-9]+,0\(a1\)
+** sh\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_short_relaxed (short* bar, short* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_char_relaxed:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_char_relaxed (char* bar, char* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_bool_relaxed:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
new file mode 100644
index 00000000000..18082ce75df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping. */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_release:
+** l[wd]\t[atx][0-9]+,0\(a1\)
+** s[wd].rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_long_release (long* bar, long* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_int_release:
+** lw\t[atx][0-9]+,0\(a1\)
+** sw.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_int_release (int* bar, int* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_short_release:
+** lhu\t[atx][0-9]+,0\(a1\)
+** sh.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_short_release (short* bar, short* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_char_release:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_char_release (char* bar, char* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_bool_release:
+** lbu\t[atx][0-9]+,0\(a1\)
+** sb.rl\t[atx][0-9]+,0\(a0\)
+** ret
+*/
+void atomic_store_bool_release (_Bool* bar, _Bool* baz)
+{
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
index 3fb16c01191..2cbf70ea69f 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
@@ -3,6 +3,7 @@
/* { dg-options "-O3" } */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zaamo } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
index 496af8bfd7d..05cc14ba747 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
@@ -3,6 +3,7 @@
/* Mixed mappings need to be unioned. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
index 737e3eb3d68..4f1b6972203 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
@@ -2,6 +2,7 @@
/* Verify that compare exchange mappings match the PSABI doc's recommended
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
index 51b3b5a8dc7..60d1b9f4b2e 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
@@ -2,6 +2,7 @@
/* Verify that compare exchange mappings match the PSABI doc's recommended
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
index 9a41410a57b..9b83c9d0b8b 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
@@ -2,6 +2,7 @@
/* Verify that compare exchange mappings match the PSABI doc's recommended
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
index ee778a760d1..d81f84f2b9f 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
@@ -2,6 +2,7 @@
/* Verify that compare exchange mappings match the PSABI doc's recommended
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
index 6fbe943b316..d209aa23407 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
@@ -3,6 +3,7 @@
/* Mixed mappings need to be unioned. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
index a361c10086d..15fd94aecbb 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
@@ -2,6 +2,7 @@
/* Verify that compare exchange mappings match the PSABI doc's recommended
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zacas } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
index 7c9187e52b5..b77e04b587a 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
@@ -2,6 +2,7 @@
/* Verify that subword atomic op mappings match the PSABI doc's suggested
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zabha } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
index 675043f9c61..24fe4ea3278 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
@@ -2,6 +2,7 @@
/* Verify that subword atomic op mappings match the PSABI doc's suggested
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zabha } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
index 7bf9eb0a7f7..4b375f09d47 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
@@ -2,6 +2,7 @@
/* Verify that subword atomic op mappings match the PSABI doc's suggested
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zabha } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
index 6b78ce74b00..f329eb46440 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
@@ -2,6 +2,7 @@
/* Verify that subword atomic op mappings match the PSABI doc's suggested
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zabha } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
index 14fadf1e3fe..eda61411781 100644
---
a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
+++
b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
@@ -2,6 +2,7 @@
/* Verify that subword atomic op mappings match the PSABI doc's suggested
mapping. */
/* { dg-add-options riscv_zalrsc } */
/* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
/* { dg-remove-options riscv_zabha } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ee4138aa697..2522e3ecf58 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2006,6 +2006,14 @@ proc check_effective_target_riscv_zacas { } {
}]
}
+proc check_effective_target_riscv_zalasr { } {
+ return [check_no_compiler_messages riscv_ext_zalasr assembly {
+ #ifndef __riscv_zalasr
+ #error "Not __riscv_zalasr"
+ #endif
+ }]
+}
+
# Return 1 if the target arch supports the double precision floating point
# extension, 0 otherwise. Cache the result.
@@ -2368,7 +2376,7 @@ proc check_effective_target_riscv_v_misalign_ok { } {
proc riscv_get_arch { } {
set gcc_march ""
# ??? do we neeed to add more extensions to the list below?
- foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbkb zbkc
zbs zvbb zvfh ztso zaamo zalrsc zabha zacas } {
+ foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbkb zbkc
zbs zvbb zvfh ztso zaamo zalrsc zabha zacas zalasr } {
if { [check_no_compiler_messages riscv_ext_$ext assembly [string map
[list DEF __riscv_$ext] {
#ifndef DEF
#error "Not DEF"
@@ -2583,6 +2591,14 @@ proc remove_options_for_riscv_zacas { flags } {
return [remove_options_for_riscv_z_ext zacas $modified_flags]
}
+proc add_options_for_riscv_zalasr { flags } {
+ return [add_options_for_riscv_z_ext zalasr $flags]
+}
+
+proc remove_options_for_riscv_zalasr { flags } {
+ return [remove_options_for_riscv_z_ext zalasr $flags]
+}
+
proc add_options_for_riscv_zfh { flags } {
return [add_options_for_riscv_z_ext zfh $flags]
}
@@ -6073,7 +6089,7 @@ foreach { armfunc armflag armdefs } {
# /* { dg-add-options arm_cpu_xscale } */
# /* { dg-require-effective-target arm_xscale_multilib } */
-# NOTE: -mcpu does not override -mtune, so to ensure the tuning is consistent
+# NOTE: -mcpu does not override -mtune, so to ensure the tuning is consistent
# for tests using these flags all entries should set -mcpu and -mtune
explicitly
# This table should only be used to set -mcpu= (and associated
@@ -13213,7 +13229,7 @@ proc check_effective_target_autoincdec { } {
#
proc check_effective_target_supports_stack_clash_protection { } {
- if { [check_effective_target_x86]
+ if { [check_effective_target_x86]
|| [istarget powerpc*-*-*] || [istarget rs6000*-*-*]
|| [istarget aarch64*-**] || [istarget s390*-*-*]
|| [istarget loongarch64*-**] || [istarget riscv64*-**] } {
@@ -14181,7 +14197,7 @@ proc check_nvptx_default_ptx_isa_version_at_least {
major minor } {
"#error unsupported" \
"#endif"]
set src [join $src "\n"]
-
+
set res [check_no_compiler_messages $name assembly $src ""]
return $res
@@ -14216,7 +14232,7 @@ proc
check_nvptx_default_ptx_isa_target_architecture_at_least { ta } {
"#error unsupported" \
"#endif"]
set src [join $src "\n"]
-
+
set res [check_no_compiler_messages $name assembly $src ""]
return $res
@@ -14331,7 +14347,7 @@ proc check_effective_target_alarm { } {
#include <stdlib.h>
#include <unistd.h>
void do_exit(int i) { exit (0); }
- int main (void) {
+ int main (void) {
struct sigaction s;
sigemptyset (&s.sa_mask);
s.sa_handler = exit;
--
2.43.0
