Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

Bill: On Thu, 2020-08-13 at 13:38 -0500, Bill Schmidt wrote: > Hi Carl, > > Thanks for cleaning up the consistency issue. The new names and > related > adjustments LGTM. > > Are there no affected test cases that need adjusting? That > surprises > me. For example, didn't __builtin_altivec_xx

Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

Bill: On Thu, 2020-08-13 at 14:48 -0500, Bill Schmidt wrote: > OK, but that was just meant as an example. We have a fair number of > things that changed names, so I was somewhat surprised. It could be > that all of these are likewise hidden via the overload mechanism. > Just > checking to b

RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

On Fri, 2020-08-14 at 16:33 -0500, Segher Boessenkool wrote: > Hi Carl, > > On Thu, Aug 13, 2020 at 09:12:48AM -0700, Carl Love wrote: > > The macro expansion for the bfloat convert intrinsics XVCVBF16SP > > and > > XVCVSPBF16 need to be restricted to P10. > >

RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

Segher, Bill, Peter: On Fri, 2020-08-14 at 19:42 -0500, Segher Boessenkool wrote: > > > Do the names agree with the (future) documentation now? > > > > Did not double check on the documentation. > > Someone should... Looking at the box document "Proposed function Prototypes for P10". There are

RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

Bill: On Mon, 2020-08-17 at 13:09 -0500, Bill Schmidt wrote: > > > > There are three prototypes __builtin_cfuged, __builtin_pdepd, > > __builtin_pextd defined in the document. > > > > The corresponding builtin definitions in GCC are: > > > > __builtin_altivec_cfuged, __builtin_altivec_pdep

RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote: > On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote: > > On 8/14/20 7:42 PM, Segher Boessenkool wrote: > > > I think your current code is fine; I hadn't considered Bill's > > > upcoming > > > rewrite. It is more important to

RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

icted to Power 10 by adding the needed Power 10 macro definition. This is a whole new patch so I figure it needs to be reviewed to make sure we want to make this change to GCC 10. I did run the regression tests again using a Power 9 machine to verify it complies and there a

RE: [Patch 3/5] rs6000, Add TI to TD (128-bit DFP) and TD to TI support

Segher: On Wed, 2020-08-19 at 20:29 -0500, Segher Boessenkool wrote: > Hi! > > On Tue, Aug 11, 2020 at 12:22:59PM -0700, Carl Love wrote: > > +(define_insn "floattitd2" > > + [(set (match_operand:TD 0 "gpc_reg_operand" "=d") > &g

RE: [Patch 4/5] rs6000, Test 128-bit shifts for just the int128 type.

Segher: On Thu, 2020-08-20 at 16:50 -0500, Segher Boessenkool wrote: > Hi! > > On Tue, Aug 11, 2020 at 12:23:05PM -0700, Carl Love wrote: > > +;; 128-bit int modes > > +(define_mode_iterator VEC_I128 [V1TI TI]) > > We already have VSX_TI for this (in vsx.md).

Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

GCC maintainers: The following patch has been updated based on the comments from Will and Segher. The patch is a subset of the mainline commit: commit 07d456bb80a16405723c98c2ab74ccc2a5a23898 Author: Carl Love

[PATCH] rs6000, vec_popcntd is improperly defined in altivec.h

. Carl Love -- vec_popcntd is improperly defined in altivec.h gcc/ChangeLog 2020-08-27 Carl Love PR target/85830 * config/rs6000/altivec.h (vec_popcntub, vec_popcntuh, vec_popcntuw, vec_popcntud): Remove

Re: [PATCH] rs6000, vec_popcntd is improperly defined in altivec.h

table for mainline. Carl Love - rs6000, fix improperly defined in builtins. gcc/ChangeLog 2020-08-31 Carl Love PR target/85830 * config/rs6000/altivec.h (vec_popcntb, vec_popcnth, vec_popcntw, ve

[PATCH,rs6000] Add command line and builtin compatibility

incompatible with the -mno-fprnd option. Please let me know if the patch looks OK for mainline. Thanks. Carl Love --- rs6000: Add command line and builtin compatibility check PR/target 87583 gcc/ChangeLog

Re: [PATCH,rs6000] Add command line and builtin compatibility

uiltin_vsx_xsrdpip’ is incompatible with ‘-mno-fprnd’ option 146 | z[i][0] = __builtin_vsx_xsrdpip (z[i][1]); i++; | ^ The updated patch is below. Please let me know if there are any additional things needing fi

Re: Re: [PATCH,rs6000] Add command line and builtin compatibility

Segher: > > From the GCC manual: > > -mmfcrfp4 2.01 > -mpopcntb p5 2.02 > -mfprndp5+ 2.04 ("info gcc" says 2.03, that's wrong? But the > ISA > says this is 2.02 even? Now what!) > -mcmpb p6 2.05 > -mpopcntd p7 2.06 > > (and there are more,

Re: Re: Re: [PATCH, rs6000] Add command line and builtin compatibility

el supported by the processor so went with the processor number in the patch. Thoughts? gcc -mno-fprnd -g -mcpu=power7 -c vsx-builtin-3.c cc1: error: ‘-mno-fprnd’ not compatible with Power 7 and newer Carl Love -------

[PATCH v3] RS6000, add VSX mask manipulation support

know if the patch is acceptable for mainline. Thanks for your time and previous reviews of the patch. Carl Love - version 3 Changes rebased onto mainline 7/7/2020 Change FUTURE to P10 in code and ChangeLog. ChangeLog

[PATCH ver 4] RS6000, add VSX mask manipulation support

Will, Segher: I fixed up the patch based on Will's comments. I thought I had made and committed the fixes that Will caught, but no Sorry about that. I will get this right yet. Carl Love --- Version 4 vec_mt

[PATCH 0/6 ver 4] ] Permute Class Operations

Segher: The following is version 4 of the series of patches for the permute class operations. Per your request, I will send each patch as a reply to this message so they are all in the same thread in your email box. Patches 1, 2,3 and 4 just have minor fixes per your earlier comments. Howeve

Re: [PATCH 0/6 ver 4] ] Permute Class Operations

. Thanks. Carl Love -- gcc/ChangeLog 2020-07-06 Carl Love * config/rs6000/altivec.md: (UNSPEC_EXTRACTL, UNSPEC_EXTRACTR) (vextractl, vextractr) (vextractl_internal, vextractr_internal for mode VI2

Re: [PATCH 0/6 ver 4] ] Permute Class Operations

powerpc64le-unknown-linux-gnu (Power 9 LE) and mambo with no regression errors. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love -- gcc/ChangeLog 2020-07-02 Carl Love

Re: [PATCH 0/6 ver 4] ] Permute Class Operations

The patch has been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) and Mambo with no regression errors. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love --- gc

Re: [PATCH 0/6 ver 4] ] Permute Class Operations

. The patch has been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) and mambo with no regression errors. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love

Re: [PATCH 0/6 ver 4] ] Permute Class Operations

r 9 LE) with no regression errors. The test cases were compiled on a Power 9 system and then tested on Mambo. Carl Love --- rs6000 RFC2609 vector blend, permute instructions gcc/ChangeLog 2020-07-06 Carl L

Re: [PATCH 0/6 ver 4] ] Permute Class Operations

on Mambo. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love ---- gcc/ChangeLog 2020-07-06 Carl Love * config/rs6000/altivec.h (vec_splati, vec_splatid, vec_splati_ins):

Re: [PATCH ver 4] RS6000, add VSX mask manipulation support

wing patch adds support for builtins vec_genbm(), vec_genhm(), vec_genwm(), vec_gendm(), vec_genqm(), vec_cntm(), vec_expandm(), vec_extractm(). Support for instructions mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, cntm, vexpandm, vextractm. The test has been tested on: powerpc64le-unknown

[PATCH 0/6 ver 5] ] Permute Class Operations

Segher: I fixed the comments to patch 5 in the series. Patch 6 has yet to be reviewed. I made all the minor changes to patches 1 to 4 that you and Will mentioned. Those patches were approved with the minor changes so I will not bother to repost them. I will just be reposting patches 5 and 6.

[PATCH 5/6 ver 5] rs6000, Add vector splat builtin support

PATCH 6/6 ver 5] rs6000 Add vector blend, permute builtin support

E) with no regression errors. The test cases were compiled on a Power 9 system and then tested on Mambo. Carl Love --- rs6000 RFC2609 vector blend, permute instructions gcc/ChangeLog 2020-07-13 Carl Love

Re: [PATCH 5/6 ver 5] rs6000, Add vector splat builtin support

On Tue, 2020-07-21 at 10:27 -0700, Carl Love wrote: > Patch didn't seem to come thru. - >From d2d534d7b4a0caf77d362094ca8e3b53559ce80f Mon Sep 17 00:00:00 2001 From: Carl Love Date: Wed, 27 May 2020 10:07:44 -0500 Subject: [PATCH 5/6] rs6000,

[PATCH] rs6000, Fix header comment for intrinsic function

and backporting as appropriate. Thanks. Carl Love --- rs6000, Fix header comment for intrinsic function _mm_movemask_epi8 gcc/ChangeLog 2020-04-22 Carl Love * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment for

[PATCH] rs6000, fix vec_first_match_index for nulls

. Carl Love -- gcc/ChangeLog 2020-04-30 Carl Love PR target/94833 * config/rs6000/vsx.md (define_expand): Fix instruction generation for first_match_index_. * testsuite/gcc.target/powerpc/builtins-8-p9

[PATCH] rs6000, pr 94833: fix vec_first_match_index for nulls

tain zeros rather then a zero length vector. Carl Love -- GCC maintainers: The following patch fixes PR94833, vec_first_match_index does not function as described in its description. The builtin does not handle vector elements whic

[PATCH resend] rs6000, pr 94833: fix vec_first_match_index for nulls

ne and for backporting as needed. Thanks. Carl Love -- gcc/ChangeLog 2020-04-30 Carl Love PR target/94833 * config/rs6000/vsx.md (define_expand): Fix instruction generation for first_ma

[PATCH] RS6000, add VSX mask manipulation support

on: powerpc64le-unknown-linux-gnu (Power 9 LE) and mambo with no regression errors. Please let me know if this patch is acceptable for mainline. Thanks. Carl Love --- RS6000 RFC 2629, add VSX mask manipulation

Re: [PATCH v2] RS6000, add VSX mask manipulation support

- vsx_mask-runnable.c: divided it up into four smaller test cases, vsx_mask-count-runnable.c, vsx_mask-expane-runnable.c, vsx_mask-extract-runnable.c, vsx_mask-move-runnable.c. Please let me know if there are additional concerns. Thanks.

[PATCH 0/6] Permute Class Operations

, vector blend builtin support. Carl Love

[PATCH 4/6] rs6000, Add vector shift double builtin support

branch. Thanks. Carl Love --- gcc/ChangeLog 2020-05-30 Carl Love * config/rs6000/altivec.h: Add define for vec_sldb and vec_srdb. * config/rs6000/altivec.md: Add unspec definitions UNSPEC_SLDB and

[PATCH 2/6] rs6000 Add vector insert builtin support

. Carl Love -- gcc/ChangeLog 2020-05-30 Carl Love * config/rs6000/altivec.h: Add define vec_insertl, vec_inserth. * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_3): Add definition for

[PATCH 5/6] rs6000, Add vector splat builtin support

. Thanks. Carl Love gcc/ChangeLog 2020-05-30 Carl Love * config/rs6000/altivec.h: Add define for vec_splati, vec_splatid and vec_splati_ins. * config/rs6000/vsx.md: Add UNSPEC_XXSPLTIW

[PATCH 1/6] rs6000, Update support for vec_extract

names and descriptions. The patch does not make any functional changes. Please let me know if the changes are acceptable for the mainline branch. Thanks. Carl Love -- gcc/ChangeLog 2020-05-30 Carl Love * config

[PATCH 6/6] rs6000 Add vector blend, permute builtin support

let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love --- rs6000 RFC2609 vector blend, permute instructions gcc/ChangeLog 2020-05-30 Carl Love * config/rs6000/altivec.h

[PATCH 3/6] rs6000, Add vector replace builtin support

mainline branch. Thanks. Carl Love --- gcc/ChangeLog 2020-05-30 Carl Love * config/rs6000/altivec.h: Add define for vec_replace_elt and vec_replace_unaligned. * config/rs6000/vsx.md: Add unspec

Re: [PATCH v4] rs6000, vector integer multiply/divide/modulo instructions

Segher, Will: Just wanted to ping you both on this patch. It has been out there for awhile. Carl On Mon, 2020-12-07 at 16:31 -0800, Carl Love wrote: > Will: > > I have addressed you comments with regards to the Change Log > entries. > > The extra

[PATCH v5] rs6000, vector integer multiply/divide/modulo instructions

table for mainline. Thanks. Carl Love --- 2021-01-12 Carl Love gcc/ * config/rs6000/altivec.h (vec_mulh, vec_div, vec_dive, vec_mod): New defines. * config/rs6000/altivec.md (VIlong):

[PATCH 1/6 ver 3] rs6000, Fix arguments in altivec_vrlwmi and altivec_rlwdi builtins

(Power 10 LE) Please let me know if the patch is acceptable for mainline. Carl Love -- gcc/ChangeLog 2021-01-12 Carl Love gcc/ * config/rs6000/altivec.md (altivec_vrlmi): Fix bug in argument

[PATCH 5/6 ver 3] rs6000, Add test 128-bit shifts for just the int128 type.

VEC_TI in vector.md. The uses of VEC_TI are also updated. version 3: No additional functional changes. Tested on Power 8BE, Power 9, Power 10. version 2: Re-tested the patch on Power 9 with no regression errors. Carl Love

[PATCH 2/6 ver 3] RS6000 Add 128-bit Binary Integer sign extend operations

*-*-linux instead of powerpc*-*-linux. Tested on Power 8BE, Power9, Power10. version 2: Removed the blank line per Will's latest feedback. Retested the patch on Power 9 with no regression errors.

[PATCH 4/6 ver 3] Add TI to TD (128-bit DFP) and TD to TI support

the patch on Power 9 with no regression errors. Carl --- gcc/ChangeLog 2021-01-12 Carl Love * config/rs6000/dfp.md (floattitd2, fixtdti2): New define_insns. * config/rs6000/rs6000

[PATCH 3/6 ver 3] RS6000 add 128-bit Integer Operations part 1

errors. Carl Love -- gcc/ChangeLog 2021-01-12 Carl Love * config/rs6000/altivec.h (vec_signextq, vec_dive, vec_mod): Add define for new builtins. * config/rs6000/altivec.md

[PATCH 6/6 ver 3] Conversions between 128-bit integer and floating point values.

Power 8BE, Power9, Power10. version 2: Fixed a typo in the ChangeLog noted by Will. Removed the target ppc_native_128bit from the test case as we no longer have the 128-bit flag. Re-tested the patch on Power 9 with no regression errors. Carl Love

[PATCH 0/6 ver3] RS6000 add 128-bit Integer Operations

to get the 128-bit conversion support to use the new hardware instrucitons on Power 10. The existing software support is used for Power 9 and earlier platforms. Carl Love

RE: [PATCH 5/6] rs6000, Add vector splat builtin support

Segher: So I have been looking at the predicate definitions that I had created. On Fri, 2020-06-05 at 16:28 -0500, Segher Boessenkool wrote: > > +;; Return 1 if op is a 32-bit constant signed integer > > +(define_predicate "s32bit_cint_operand" > > + (and (match_code "const_int") > > + (ma

RE: [PATCH resend] rs6000, pr 94833: fix vec_first_match_index for nulls

et me know how you would like me to handle this issue. Carl Love On Thu, 2020-05-14 at 11:53 -0500, Segher Boessenkool wrote: > Hi! > > On Wed, May 13, 2020 at 10:14:24AM -0700, Carl Love wrote: > > The following patch fixes PR94833, vec_first_match_index does not >

RE: [PATCH 5/6] rs6000, Add vector splat builtin support

On Wed, 2020-06-10 at 10:46 -0500, will schmidt wrote: > > On Fri, 2020-06-05 at 16:28 -0500, Segher Boessenkool wrote: > > > > +;; Return 1 if op is a 32-bit constant signed integer > > > > +(define_predicate "s32bit_cint_operand" > > > > + (and (match_code "const_int") > > > > + (match_t

[PATCH 2/6 ver 2] rs6000 Add vector insert builtin support

mainline branch. Thanks. Carl Love -- gcc/ChangeLog 2020-06-15 Carl Love * config/rs6000/altivec.h (vec_insertl, vec_inserth): New defines. * config/rs6000/rs6000-builtin.def (VINSERTGPRBL

[PATCH 1/6 ver 2] rs6000, Update support for vec_extract

. The patch does not make any functional changes. Please let me know if the changes are acceptable. Thanks. Carl Love -- gcc/ChangeLog 2020-06-15 Carl Love * config/rs6000/altivec.md: (UNSPEC_EXTRACTL

[PATCH 0/6] ] Permute Class Operations

Version 2. The patches in this series have been updated per the comments from Segher. I have put at the top of each patch a short summary of the version 2 changes. Hopefully the summaries will make the re-review easier and faster. Most of the changes were ChangeLog fixes with a few functional

[PATCH 3/6 ver 2] rs6000, Add vector replace builtin support

is acceptable for the pu branch. Thanks. Carl Love --- gcc/ChangeLog 2020-06-15 Carl Love * config/rs6000/altivec.h: Add define for vec_replace_elt and vec_replace_unaligned. * config/rs6000

[PATCH 6/6 ver 2] rs6000 Add vector blend, permute builtin support

ing patch adds support for the vec_blendv and vec_permx builtins. The patch has been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) with no regression errors. The test cases were compiled on a Power 9 system and then tested on Mambo.

[PATCH 4/6 ver 2] rs6000, Add vector shift double builtin support

been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) and Mambo with no regression errors. Please let me know if this patch is acceptable for the pu branch. Thanks. Carl Love --- gcc/ChangeLog

[PATCH 5/6 ver 2] rs6000, Add vector splat builtin support

patch is acceptable for the pu branch. Thanks. Carl Love gcc/ChangeLog 2020-06-15 Carl Love * config/rs6000/altivec.h (vec_splati, vec_splatid, vec_splati_ins): Add defines. * config/rs6000

[PATCH 2/6 ver 3] rs6000 Add vector insert builtin support

adds support for vec_insertl and vec_inserth builtins. The patch has been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) and mambo with no regression errors. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love

[PATCH 0/6 ver 3] ] Permute Class Operations

the latest description of the builtins with a few minor edits to address typos in the descriptions. Carl Love

[PATCH 1/6 ver 3] rs6000, Update support for vec_extract

make any functional changes. Please let me know if the changes are acceptable for mainline. Thanks. Carl Love -- gcc/ChangeLog 2020-06-18 Carl Love * config/rs6000/altivec.md: (UNSPEC_EXTRACTL, UNSPEC_EXTRACTR

[PATCH 6/6 ver 3] rs6000 Add vector blend, permute builtin support

support for the vec_blendv and vec_permx builtins. The patch has been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) with no regression errors. The test cases were compiled on a Power 9 system and then tested on Ma

[PATCH 3/6 ver 3] rs6000, Add vector replace builtin support

has been compiled and tested on powerpc64le-unknown-linux-gnu (Power 9 LE) and mambo with no regression errors. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love --- gcc

[PATCH 4/6 ver 3] rs6000, Add vector shift double builtin support

regression errors. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love --- gcc/ChangeLog 2020-06-18 Carl Love * config/rs6000/altivec.h (vec_sldb, vec_srdb): New defines

[PATCH 5/6 ver 3] rs6000, Add vector splat builtin support

case was compiled on a Power 9 system and then tested on Mambo. Please let me know if this patch is acceptable for the mainline branch. Thanks. Carl Love gcc/ChangeLog 2020-06-18 Carl Love * config/rs6000

RE: [PATCH 5/6 ver 3] rs6000, Add vector splat builtin support

Segher: On Thu, 2020-06-25 at 17:39 -0500, Segher Boessenkool wrote: > > +;; Return 1 if op is a constant 32-bit floating point value > > +(define_predicate "f32bit_const_operand" > > + (match_code "const_double") > > +{ > > + if (GET_MODE (op) == SFmode) > > +return 1; > > + > > + else if

RE: [PATCH 5/6 ver 3] rs6000, Add vector splat builtin support

On Mon, 2020-06-29 at 16:58 -0500, Segher Boessenkool wrote: > On Mon, Jun 29, 2020 at 02:29:54PM -0700, Carl Love wrote: > > Segher: > > > > On Thu, 2020-06-25 at 17:39 -0500, Segher Boessenkool wrote: > > > > +;; Return 1 if op is a con

RE: [PATCH 5/6 ver 3] rs6000, Add vector splat builtin support

On Wed, 2020-07-01 at 12:00 -0500, Segher Boessenkool wrote: > Hi! > > On Mon, Jun 29, 2020 at 03:31:48PM -0700, Carl Love wrote: > > On Mon, 2020-06-29 at 16:58 -0500, Segher Boessenkool wrote: > > > On Mon, Jun 29, 2020 at 02:29:54PM -0700, Carl Love wrote: > > &

[PATCH v2] rs6000, vector integer multiply/divide/modulo instructions

with no regressions. Additionally the new test case was compiled and executed by hand on Mambo to verify the test case passes. Please let me know if this patch is acceptable for mainline. Thanks. Carl Love ------- 2020-11-

Re: [PATCH v2] rs6000, vector integer multiply/divide/modulo instructions

Segher, Pat: I have updated the patch to address the comments below. On Wed, 2020-11-25 at 20:30 -0600, Segher Boessenkool wrote: > On Tue, Nov 24, 2020 at 08:34:51PM -0600, Pat Haugen wrote: > > On 11/24/20 8:17 PM, Pat Haugen via Gcc-patches wrote: > > > On 11/24/20 12:59 PM,

[PATCH v4] rs6000, vector integer multiply/divide/modulo instructions

. Carl Love - >From 15f9c090106c62af83cc405414466ad03d1a4c55 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Fri, 4 Sep 2020 19:24:22 -0500 Subject: [PATCH] rs6000, vector integer multiply/divide/modulo instructions 2020-12-07 Carl L

Re: [PATCH 2a/5] rs6000, vec_rlnm builtin fix arguments

test. Re-tested the patch on Power 9 with no regression errors. Carl - gcc/ChangeLog 2020-10-08 Carl Love * config/rs6000/altivec.h (vec_rlnm): Fix bug in argument generation. --- gcc/config/rs6000

Re: [PATCH 3/5] Add TI to TD (128-bit DFP) and TD to TI support

. Carl --- gcc/ChangeLog 2020-10-12 Carl Love * config/rs6000/dfp.md (floattitd2, fixtdti2): New define_insns. * config/rs6000/rs6000-call.c (P10V_BUILTIN_VCMPNET_P, P10V_BUILTIN_VCMPAET_P): New overloaded

Re: [PATCH 2b/5] RS6000 add 128-bit Integer Operations

Power 9 with no regression errors. Carl -- gcc/ChangeLog 2020-10-08 Carl Love * config/rs6000/altivec.h (vec_signextq, vec_dive, vec_mod): Add define for new builtins. * config/rs6000

Re: [PATCH 4/5] Test 128-bit shifts for just the int128 type.

. Carl gcc/ChangeLog 2020-10-12 Carl Love * config/rs6000/altivec.md (altivec_vslq, altivec_vsrq): Rename to altivec_vslq_, altivec_vsrq_, mode VEC_TI. * config/rs6000/vector.md (VEC_TI): Was named VSX_TI in

Re: [PATCH 5/5] Conversions between 128-bit integer and floating point values.

case as we no longer have the 128-bit flag. Re-tested the patch on Power 9 with no regression errors. Carl -- gcc/ChangeLog 2020-10-12 Carl Love * config/rs6000/rs6000.md (floatti2, floatunsti2

Re: [PATCH 1/5] RS6000 Add 128-bit Binary Integer sign extend operations

Carl -- gcc/ChangeLog 2020-10-08 Carl Love * config/rs6000/altivec.h (vec_signextll, vec_signexti): Add define for new builtins. * config/rs6000/rs6000-builtin.def (VSIGNEXTI, VSIGNEXTLL): Add overloaded builtin definitions. (VSIGNEXTSB2W, VSIGNEX

RE: [PATCH 1/5] RS6000 Add 128-bit Binary Integer sign extend operations

On Mon, 2020-10-12 at 15:43 -0500, Segher Boessenkool wrote: > Hi! > > On Wed, Oct 07, 2020 at 04:08:12PM -0500, will schmidt wrote: > > On Mon, 2020-10-05 at 11:51 -0700, Carl Love wrote: > > > +/* Sign extend builtins that work on ISA 3.0, but not defined > > &

Re: [RS6000] VSX_MM_SUFFIX

On Thu, 2020-10-22 at 17:21 +1030, Alan Modra wrote: > gcc.target/powerpc/vsx_mask-count-runnable.c and others > Assembler messages: > Error: unrecognized opcode: `vcntmb' > > I'm applying this one as obvious. Ref > https://gcc.gnu.org/pipermail/gcc-patches/2020-July/549757.html > > * con

Re: [RS6000] Power10 vec-splati-runnable multiple test failures

On Thu, 2020-10-22 at 17:26 +1030, Alan Modra wrote: > FAIL: gcc.target/powerpc/vec-splati-runnable.c 1 blank line(s) in > output > FAIL: gcc.target/powerpc/vec-splati-runnable.c (test for excess > errors) > Excess errors: > rs6000_emit_xxspltidp_v2df called ... > > and running the test fails. As

[PATCH] rs6000, Power 10 testsuite fixes

work correctly. Please let me know if this patch is acceptable for mainline. Thanks. Carl Love --- gcc/ChangeLog 2020-10-22 Carl Love * config/testsuite/gcc.targetpc/vec-blend-runnable.c: Change

[PATCH] rs6000, Add bcd builtings listed in appendix B of the ABI

e know if this patch is acceptable for mainline. Thanks. Carl Love -- gcc/ChangeLog 2020-10-22 Carl Love * config/rs6000/altivec.h (__builtin_bcdadd, __builtin_bcdadd_lt, __builtin_bcdadd_eq, __builtin_bcdadd_gt,

Re: [PATCH] rs6000, Add bcd builtings listed in appendix B of the ABI

. Please let me know if this patch is acceptable for mainline. Thanks. Carl Love - 2020-10-29 Carl Love gcc/ PR target/93449 * config/rs6000/altivec.h (__builtin_bcdadd, __builtin_bcdadd_lt,

RE: [PATCH] rs6000, Add bcd builtings listed in appendix B of the ABI

rather then just using internal names. The patch was compiled and tested on: powerpc64le-unknown-linux-gnu (Power 9 LE) with no regressions. Please let me know if this patch is acceptable for mainline. Thanks. Carl Love -

[PATCH] rs6000, vector integer multiply/divide/modulo instructions

-unknown-linux-gnu (Power 9 LE) with no regressions. Additionally the new test case was compiled and executed by hand on Mambo to verify the test case passes. Please let me know if this patch is acceptable for mainline. Thanks. Carl Love

RE: [PATCH] rs6000, vector integer multiply/divide/modulo instructions

On Fri, 2020-10-30 at 17:05 -0400, David Edelsohn wrote: > On Fri, Oct 30, 2020 at 4:07 PM Carl Love wrote: > > > diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p10- > > runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-p10- > > runnable.c > >

[PATCH] rs6000: Add builtins for IEEE 128-bit floating point values

patch is acceptable for mainline. Thanks. Carl -- >From a20cc81f98cce1140fc95775a7c25b55d1ca7cba Mon Sep 17 00:00:00 2001 From: Carl Love Date: Wed, 12 Apr 2023 17:46:37 -0400 Subject: [PATCH] rs6000: Add builtins for IEEE 128-bit floating point values Add supp

[PATCH] rs6000: vec_cmpne confusing implementation

GCC maintainers: The following patch cleans up the definition for the __builtin_altivec_vcmpnet. The current implementation implies that the builtin is only supported on Power 9 since it is defined under the Power 9 stanza. However the builtin has no ISA restrictions as stated in the Power Vecto

[PATCH] Fix for vcmpequt builtin

is acceptable for mainline. Carl Love --- The vcmpequt builtin define eqvv1ti3 points to the eqv define instruction for the eqv instruction. The vcmpequt builtin define should point to the altivec_eqv1ti instruction

[PATCH] rs6000: Fix test int_128bit-runnable.c instruction counts

GCC maintainers: The following fix updates the expected instruction counts for the test int_128bit-runnable.c test. The counts changed as a result of a commit to support 128-bit integer divide and modulus. The change resulted in two of the tests using vdivsq instructions rather than the vextsd

[PATCH] rs6000: Fix test gc.target/powerpc/rs600-fpint.c test options

GCC maintainers: The following patch fixes the dg-options for test powerpc/rs600- fpint.c. The test now works correctly on Power 10. The patch has been tested on Power10 with no regressions. Please let me know if the patch is acceptable for mainline. Thanks. Carl -

[PATCH] rs6000: Add buildin for mffscrn instructions

GCC maintainers: The following patch adds an overloaded builtin. There are two possible arguments for the builtin. The builtin definitions are: double __builtin_mffscrn (unsigned long int); double __builtin_mffscrn (double); The patch has been tested on Power 10 with no regressions. P

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