[PATCH GCC][4/4]Simplify (cond (cmp x c1) (op x c2) c3) -> (op (minmax x c1) c2)

add w2, w2, 1 cmp w0, w2 uminv0.8h, v1.8h, v2.8h add v0.8h, v0.8h, v2.8h str q0, [x3, x1] add x1, x1, 16 bhi .L4 Bootstrap and test on x86_64 and AArch64 for whole patch set. Any comments? Thanks, bin 2016-10-21

[PATCH GCC][2/4]Simplify (cond (cmp (convert (x), c1), x, c2)) into (minmax (x, c))

t; FAIL: gcc.dg/vect/vect-pr69848.c scan-tree-dump vect "vectorized 1 loops" Again, these failures reveal a defect in vectorizer that operand swapping is not supported for COND_REDUCTION. I will send another two patches independent to this patch set resolving these failures. Is this OK? Than

[PATCH VECT]Swap operands for cond_reduction when necessary

pd patches. In addition, couple cases are XPASSed on AArch64 now, which means more loops are vectorized. I will send following patch addressing those XPASS tests. Bootstrap and test on x86_64 and AArch64 ongoing, is it OK? Thanks, bin 2016-10-25 Bin Cheng * tree-v

[PATCH VECT]Support operand swapping for cond_expr in vect_slp

s are resolved. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2016-10-25 Bin Cheng * tree-vect-slp.c (vect_get_and_check_slp_defs): New parameter SWAP. Check slp defs for COND_EXPR by swapping/inverting operands if indicated by the new parameter

[PATCH VECT]Skip unnecessary data dependence check after visited store stmt in slp

of code. This is unnecessary no matter the last store stmt is encountered or not. This patch fixes the issue by simple refactoring. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2016-10-27 Bin Cheng * tree-vect-data-refs.c (vect_slp_analyze_node_dependences): Skip

[PATCH GCC]Clean pedantic calls and useless lvalue code in fold_cond_expr_with_comparison

patch doesn't do that because that depends on the answer to the question of the aforementioned message. Bootstrap and test on x86_64 and AArch64. Any comments? Thanks, bin 2016-10-27 Bin Cheng * fold-const.c (fold_cond_expr_with_comparison): Remove call

[PATCH test]Refine test string for scev-8.c

Bin Cheng * gcc.dg/tree-ssa/scev-8.c: Update test string. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c b/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c index 766f674..bb2ee7a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c @@ -59,4 +59,4

[PATCH test]Refine test string for scev-8.c

Bin Cheng * gcc.dg/tree-ssa/scev-8.c: Update test string. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c b/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c index 766f674..bb2ee7a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/scev-8.c @@ -59,4 +59,4

[PATCH testsuite]XFAIL gcc.dg/tree-ssa/pr71347 on some targets

/ChangeLog 2016-06-20 Bin Cheng PR tree-optimization/71347 * gcc.dg/tree-ssa/pr71347.c: XFAIL on ia64, arm, m68k and sparc. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr71347.c b/gcc/testsuite/gcc.dg/tree-ssa/pr71347.c index c8f87a9..428e41b 100644 --- a/gcc/testsuite/gcc.dg/tree

[PATCH PR71503/PR71683]Fix ICE in tree-if-conv.c

86_64. Is it OK? Thanks, bin 2016-07-13 Bin Cheng PR tree-optimization/71503 PR tree-optimization/71683 * tree-if-conv.c (gen_phi_arg_condition): Set cond when predicate is true. gcc/testsuite/ChangeLog 2016-07-13 Bin Cheng PR tree-optimization/

[PATCH GCC]Remove support for -funsafe-loop-optimizations

etes the two now useless tests, while the option interface is preserved for backward compatibility purpose. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2016-07-14 Bin Cheng * common.opt (funsafe-loop-optimizations): Mark ignore. (Wunsafe-loop-optimizations): Di

[PATCH GCC]Improve no-overflow check in SCEV using value range info.

) can help various loop passes like vectorization. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2016-07-15 Bin Cheng * tree-chrec.c (convert_affine_scev): New parameter. Pass new arg. (chrec_convert_1, chrec_convert): Ditto. * tree-chrec.h (chr

[PATCH GCC]Cleanup lt_to_ne handling in niter analyzer

is handled in function number_of_iterations_cond before. This patch also refines comment a little. Bootstrap and test on x86_64, is it OK? Thanks, bin 2016-07-19 Bin Cheng * tree-ssa-loop-niter.c (number_of_iterations_lt_to_ne): Clean up by removing computation

[PATCH test]XFAIL gcc.dg/vect/vect-mask-store-move-1.c

Hi, After patch @238301, issue reported in PR65206 is also exposed by case gcc.dg/vect/vect-mask-store-move-1.c. This patch xfail the case for the moment. Test result checked, is it OK? Thanks, bin gcc/testsuite/ChangeLog 2016-07-14 Bin Cheng * gcc.dg/vect/vect-mask-store-move-1.c

[PATCH GCC/02]Remove -funsafe-loop-optimizations option.

Hi, This patch removes support for -funsafe-loop-optimizations on both GIMPLE and RTL level by marking it as ignored. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2016-07-20 Bin Cheng * common.opt (funsafe-loop-optimizations): Mark ignore. * doc/invoke.texi (funsafe

[Patch GCC/01]Bring back warning message on loop whose counter might overflow

which removes -funsafe-loop-optimizations. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2016-07-20 Bin Cheng * tree-ssa-loop-niter.h (number_of_iterations_exit_assumptions): New Parameter. * tree-ssa-loop-niter.c (number_of_iterations_exit_assumptions)

[PATCH GCC/03]New option warning missed optimization on loops whose counter may overflow

Hi, This patch adds new option -Wmissed-loop-optimizations warning on loops whose counter may overflow, as well as makes -Wunsafe-loop-optimizations an alias to the new option. Bootstrap and test on x86_64 ongoing. Is it OK? Thanks, bin 2016-07-20 Bin Cheng * common.opt (Wmissed

[Patch GCC]Support constraint flags in loop structure.

constraint to vectorize possible infinite loop by versioning, I would also expect possible infinite loops (loops with assumptions) can be handled by more optimizers. This patch itself doesn't change GCC behavior, bootstrap and test on x86_64. Any comments? Thanks, bin 201

[PATCH GCC]Vectorize possible infinite loop by loop versioning.

flags for versioned loop so that niter analyzer in following optimizers can take advantage of it. The patch also adds two tests. Bootstrap and test on x86_64. Any comments? Thanks, bin 2016-07-25 Bin Cheng PR tree-optimization/57558 * tree-vect-loop-manip.c

[PATCH PR34114/1]More multiple_of_p cases.

if it's defined as: Y = X % bottom top = X - Y Bootstrap and test on x86_64 and AArch64 along with next patch. Is it OK? Thanks, bin 2016-07-27 Bin Cheng * fold-const.c (multiple_of_p): Improve MULT_EXPR, PLUS_EXPR, PLUS_EXPR case. Handle SSA_NAME ca

[PATCH PR34114/2]Prove no-overflow for loop with NE_EXPR exit condition and non-ONE step

2016-07-27 Bin Cheng PR tree-optimization/34114 * tree-ssa-loop-niter.c (number_of_iterations_ne): Prove no-overflow information for more control IVs. gcc/testsuite/ChangeLog 2016-07-27 Bin Cheng PR tree-optimization/34114 * gcc.dg/tree-ssa/loop-42.c

[PATCH AArch64/V3]Add new patterns for vcond_mask and vec_cmp

Hi, This is the 3rd version patch implementing vcond_mask and vec_cmp patterns on AArch64. Bootstrap and test along with next patch on AArch64, is it OK? Thanks, bin 2016-07-28 Alan Lawrence Renlin Li Bin Cheng * config/aarch64/aarch64-simd.md (vec_cmp

[PATCH AArch64][V3]Rewrite vcond patterns using vcond_mask/vec_cmp, also support missing vect_cond_mixed patterns

; res = mask ? T : F" into "res = x ? F : T", thus an additional inversion instruction can be saved. The patch includes a test for this purpose. Bootstrap and test along with previous one on AArch64, is it OK? Thanks, bin 2016-07-28 Alan Lawrence Renlin Li

[PATCH PR78507/PR78510]Fix two ICEs in pattern (cond (cmp (convert1? @1) @3) (convert2? @1) @2).

only when transformation is valid, it also incorporates Marc's suggestion by using cmp directly. Two tests are added too. Bootstrap and test on x86_64 and AArch64 ongoing, is it OK if no failures? Thanks, bin 2016-11-24 Bin Cheng PR middle-end/78507 PR middle-end/78510

[PATCH PR78574]Fix infinite recursion in find_deriving_biv_for_expr

imes in inner loop, it computes the same result for every iteration. Anyway this is stage1 work. Thanks, bin 2016-11-30 Bin Cheng PR tree-optimization/78574 * tree-ssa-loop-ivopts.c (find_deriving_biv_for_expr): Skip loop header PHI that doesn't define biv. gcc/te

[PATCH PR78559][RFC]Proposed fix

st on x86_64 and AArch64, any suggestion on how to fix this? Thanks, bin 2016-12-01 Bin Cheng PR rtl-optimization/78559 * combine.c (try_combine): Discard REG_EQUAL and REG_EQUIV for other_insn in combine. gcc/testsuite/ChangeLog 2016-12-01 Bin Cheng P

[PATCH PR78691]Require integral type for pattern ((convert1 (minmax ((convert2 (x) c)))) -> minmax (x c))

-06 Bin Cheng PR tree-optimization/78691 * match.pd ((convert1 (minmax ((convert2 (x) c -> minmax (x c)): Require integral type for the outer expression. gcc/testsuite/ChangeLog 2016-12-06 Bin Cheng PR tree-optimization/78691 * gcc.target/i386/p

[PATCH PR78684]Check sign bit for index step of data reference.

Hi, This patch fixes ICE reported in PR78684, it checks sign bit of integer const thus can handle unsigned types. Bootstrap and test on x86_64, is it OK? Thanks, bin 2016-12-06 Bin Cheng PR middle-end/78684 * tree-vect-loop-manip.c (create_intersect_range_checks_index

[PATCH TEST]Add test for PR78652

Hi, PR78652 was fixed by patch for PR77856, this patch adds a test for it. Test result checked, is it OK? Thanks, bin gcc/testsuite/ChangeLog 2016-12-07 Bin Cheng PR rtl-optimization/78652 * gcc.c-torture/execute/pr78652.c: New test.diff --git a/gcc/testsuite/gcc.c-torture

[PATCH GCC]Do more tree if-conversions by handlding PHIs with more than two arguments.

o; cleanups code logic in if_convertible_loop_p about aggressive_if_conv. Bootstrap and test on x86_64 and AArch64, is it OK? Thanks, bin 2016-04-26 Bin Cheng PR tree-optimization/56541 * tree-if-conv.c (MAX_PHI_ARG_NUM): New macro. (any_complicated_phi): New static variable.

[PATCH GCC]Proving no-trappness for array ref in tree if-conv using loop niter information.

p and test on x86_64 and aarch64, is it OK? Thanks, bin 2016-04-28 Bin Cheng * tree-if-conv.c (tree-ssa-loop.h): Include header file. (tree-ssa-loop-niter.h): Ditto. (idx_within_array_bound, ref_within_array_bound): New functions. (ifcvt_memrefs_wont_trap): Che

[PATCH PR70803]Require "vect_int_mult" for the test.

Hi, This patch fixes PR70803 by skipping targets that don't support vect_int_mult. It's an obvious change. Thanks, bin gcc/testsuite/ChangeLog 2016-04-29 Bin Cheng PR tree-optimization/70803 * gcc.dg/vect/pr56625.c: Require vect_int_mult.diff --git a/gcc/testsu

[PATCH GCC]Don't clobber cbase when computing iv_use cost.

Hi, This fixes a latent bug I introduced. Variable "cbase" shouldn't be modified since it will be used afterwards. Bootstrap and test on x86_64. I think it's an obvious change, is it OK? Thanks, bin 2016-04-28 Bin Cheng * tree-ssa-loop-ivopts.c (get_computa

[PATCH GCC]Check depends_on before recording invariant expressions

K? Thanks, bin 2016-04-28 Bin Cheng * tree-ssa-loop-ivopts.c (get_computation_cost_at): Check depends_on before using it.diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c index 7be4f16..acafaff 100644 --- a/gcc/tree-ssa-loop-ivopts.c +++ b/gcc/tree-ssa-loo

[PATCH PR57206]Add test since the PR is fixed by patch to PR48052

Hi, This patch adds a test for PR57206. The issue itself is long fixed by patch to PR48052. Test on x86_64. It's an obvious change, applied on trunk. Thanks bin gcc/testsuite/ChangeLog 2016-05-04 Bin Cheng PR tree-optimization/57206 * gcc.dg/vect/pr57206.c: New test

[PATCH PR69848/partial]Propagate comparison into VEC_COND_EXPR if target supports

comments? Thanks, bin 2016-05-12 Bin Cheng PR tree-optimization/69848 * optabs-tree.c (expand_vcond_mask_p, expand_vcond_p): New. (expand_vec_cmp_expr_p): Call above functions. * optabs-tree.h (expand_vcond_mask_p, expand_vcond_p): New. * tree-ssa-for

[PATCH GCC]Document vect_cond_mixed in sourcebuild.texi

Hi, This is an obvious patch documenting vect_cond_mixed in sourcebuild.texi. OK? Thanks, bin 2016-05-13 bin cheng * doc/sourcebuild.texi (@item vect_cond_mixed): New item.diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 3142cd5..f1bd9be 100644 --- a/gcc/doc

[PATCH AArch64]Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.

on "vect_cond_mixed" can be enabled on AArch64 (in a following patch). Bootstrap and test on AArch64. Is it OK? BTW, this patch is necessary for gcc.dg/vect/PR56541.c (on AArch64) which was added before in tree if-conversion patch. Thanks, bin 2016-05-11 Alan Lawrence

[PATCH GCC]Enable vect_cond_mixed for AArch64.

This was failed for all targets, but was just fixed by my previous tree ifcvt patch. slp-cond-2-big-array.c slp-cond-2.c vect-cond-10.c vect-cond-8.c vect-cond-9.c They will start passing after this patch. Test on AArch64. Is it OK? Thanks, bin gcc/testsuite/ChangeLog 2016-05-12 Bin Cheng

[PATCH Obvious/r236200]Check invariant expression pointer, not pointer to the pointer

/pr42505.c. Apply as obvious. Thanks, bin 2016-05-18 Bin Cheng * tree-ssa-loop-ivopts.c (get_computation_cost_at): Check invariant expression pointer, not pointer to the pointer.diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c index e8953a0..9ce6b64 100644

[PATCH GCC]A latent alignment bug in tree-ssa-address.c

t needs non-trivial code refactoring since copy_ref_info is uses by different parts of compiler. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2016-05-20 Bin Cheng * tree-ssa-address.c (copy_ref_info): Check null TMR_STEP.diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-addr

[PATCH GCC][rework]Improve loop bound info by simplifying conversions in iv base

never executed, so I removed that part code. The patch also includes some code format changes. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2015-08-27 Bin Cheng * tree-ssa-loop-niter.c (tree_simplify_using_condition_1): Support new parameter. (tree_sim

[PATCH PR66388]Add sizetype cand for BIV of smaller type if it's used as index of memory ref

and aarch64. It fixes failure of gcc.target/i386/pr49781-1.c, without new breakage. So what do you think? Thanks, bin 2015-08-31 Bin Cheng * tree-affine.c (aff_combination_expand): New parameters. (tree_to_aff_combination_expand): Ditto. * tree-affine.h (aff_combinat

[PATCH GCC]Try to fold (long)(A-B) into (long)A - (long)B for canonicalization in tree affine

is in tree_to_aff_combination, so it can produce canonical affines rather than stupid expressions like "&arr + (sizetype) (t_4(D) + t_4(D)) * 4 - (sizetype)t_4(D) * 8". Bootstrap and test on x86_64 and aarch64 along with other patches. Is it OK? 2015-08-31 Bin Cheng

[PATCH GCC]Look into unnecessary conversion when checking mult_op in get_shiftadd_cost

patches. Is it OK? Thanks, bin 2015-08-31 Bin Cheng * tree-ssa-loop-ivopts.c (get_shiftadd_cost): Look into unnecessary type conversion for OP1. Index: gcc/tree-ssa-loop-ivopts.c === --- gcc/tree-ssa-loop-ivopts.c

[PATCH TEST]Drop xfail for gcc.dg/vect/vect-cond-2.c

Hi, Test gcc.dg/vect/vect-cond-2.c can be vectorized by GCC now, this patch drops the xfail. Thanks, bin gcc/testsuite/ChangeLog 2016-11-04 Bin Cheng * gcc.dg/vect/vect-cond-2.c: Drop xfail.diff --git a/gcc/testsuite/gcc.dg/vect/vect-cond-2.c b/gcc/testsuite/gcc.dg/vect/vect-cond-2

[PATCH TEST]Drop xfail for gcc.dg/tree-ssa/pr71347.c

Hi, With tree pre improvement @239414, test gcc.dg/tree-ssa/pr71347.c no longer xfails. Given the change is target independent, I am dropping xfail of the test for all targets. Thanks, bin gcc/testsuite/ChangeLog 2016-11-04 Bin Cheng * gcc.dg/tree-ssa/pr71347.c: Drop xfail.diff

[PATCH TEST]XFAIL gcc.dg/vect/pr56541.c for !vect_cond_mixed target for now

on at the moment, this patch xfail it on such targets. Thanks, bin gcc/testsuite/ChangeLog 2016-11-04 Bin Cheng * gcc.dg/vect/pr56541.c: Xfail on !vect_cond_mixed targets.diff --git a/gcc/testsuite/gcc.dg/vect/pr56541.c b/gcc/testsuite/gcc.dg/vect/pr56541.c index 16b8d7c..d5def68 1

[PATCH TEST]Only drop xfail for gcc.dg/vect/vect-cond-2.c on targets supporting vect_max_reduc

Hi, Test gcc.dg/vect/vect-cond-2.c still requires vect_max_reduc to be vectorized, this patch adds the requirement. Thanks, bin gcc/testsuite/ChangeLog 2016-11-09 Bin Cheng * gcc.dg/vect/vect-cond-2.c: Only drop xfail for targets supporting vect_max_reduc.diff --git a/gcc

[PATCH Obvious]Adjust test string wrto update dump info for gcc.target/arm/ivopts-orig_biv-inc.c

Hi, Dump information of IVOPT has been updated while test string gcc.target/arm/ivopts-orig_biv-inc.c is not. This patch does this. Test result checked on arm-none-eabi. Commit as obvious? Thanks, bin gcc/testsuite/ChangeLog 2016-11-16 Bin Cheng * gcc.target/arm/ivopts-orig_biv

[PATCH PR78114]Refine gfortran.dg/vect/fast-math-mgrid-resid.f

is 2; or vectorization variable is created when factor is 4. This works since we have only one main loop, and only one vector factor can be used. Test result checked for various x64 targets. Is it OK? Thanks, bin gcc/testsuite/ChangeLog 2016-11-16 Bin Cheng PR testsuite/

[PATCH GCC]Move simplification from fold-cond.c to match.pd and extend it

handled by a follow up). This patch also adds several tests, some tests are for existing fold_cond_expr_with_comparison simplification but not covered yet; others are for new extension. Bootstrap and test on x86_64 and AArch64 along with following patches, is it OK? Thanks, bin 2016-11-1

[PATCH GCC]Move simplification of (A == C1) ? A : C2 to match.pd

Hi, This is a follow up patch for https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01898.html It moves remaining simplification for (A == C1) ? A : C2 in fold_cond_expr_with_comparison to match.pd. Bootstrap and test on x86_64 and AArch64, is it OK? Thanks, bin 2016-11-17 Bin Cheng

[PATCH GCC]Simplify (cond (cmp (convert? x) c1) (op x c2) c3) -> (op (minmax x c1) c2)

gs as suggested. Bootstrap and test on x86_64 and AArch64, is it OK? Thanks, bin 2016-11-17 Bin Cheng * match.pd: Add new pattern: (cond (cmp (convert? x) c1) (op x c2) c3) -> (op (minmax x c1) c2). gcc/testsuite/ChangeLog 2016-11-17 Bin Cheng * gcc.dg/fold-bop

[PATCH GCC]Refine type conversion in result expressions for cond_expr pattern

? Thanks, bin 2016-11-23 Bin Cheng * match.pd: Refine type conversion in result expressions for below pattern: (cond (cmp (convert1? x) c1) (convert2? x) c2) -> (minmax (x c)).Index: gcc/match.pd === ---

[PATCH PR68911]Check overflow when computing range information from loop niter bound

dn't do that in this patch. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2016-01-10 Bin Cheng PR tree-optimization/68911 * tree-vrp.c (adjust_range_with_scev): Check overflow in range information computed for expression "init +

[PATCH PR66796]Obvious, revise check condition in test case

for it. Test run on HPPA. Applied as an obvious change. Thanks, bin gcc/testsuite/ChangeLog 2016-01-18 Bin Cheng PR tree-optimization/66797 * gcc.c-torture/execute/pr65447.c: Relax check condition.

[PATCH PR62178]Improve candidate selecting in IVOPT, 2nd try.

with lower cost, any regressions revealed are latent bugs of other components in GCC. I also collected GCC bootstrap time on x86_64, no regression either. Is this OK? 2014-12-03 Bin Cheng bin.ch...@arm.com PR tree-optimization/62178 * tree-ssa-loop-ivopts.c (iv_ca_replace): New fun

[PATCH PR62151]Fix REG_DEAD note distribution issue by using right ELIM_I0/ELIM_I1

doesn't touch distribute_notes because we are in stage3 and I want to have more discussion on it. Bootstrap and test on x86_64. aarch64 is ongoing. So is it ok? 2014-12-11 Bin Cheng PR rtl-optimization/62151 * combine.c (try_combine): Reset elim_i0 and elim_i1

[PATCH AARCH64]Make ldp/stp case less vulnerable

possible fix is to move sched_fusion after regrename, it does help a lot. I didn't do that because regrenamre is currently disabled. Tested on aarch64-elf. Is it OK? Thanks, bin gcc/testsuite/ChangeLog 2014-12-11 Bin Cheng * gcc.target/aarch64/ldp_stp_2.c: Make test less vulne

[GCC arm-embedded-4_7]Backport r192603/r192604 to arm-embedded-4_7 branch

Hi, I back ported revision 192603/192604 to arm-embedded-4_7 branch as r193088. Thanks. r193088 | amker | 2012-11-02 10:15:42 +0800 (五, 02 11月 2012) | 39 lines Backport from mainline r192604 2012-10-19 Bin Cheng * common.opt (flag_ira_hoist_pressure): New

[PATCH Version 2][RFA]Improving register pressure directed hoist

uting VBE optimistically in compute_code_hoist_vbeinout). Also I don't understand why the bogus patch can catch more hoist opportunities and improve code size, so please help if you have any idea about this. It is re-tested on x86. OK? Thanks very much. 2012-11-02 Bin Cheng

RE: [PATCH Version 2][RFA]Improving register pressure directed hoist

> -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Tuesday, November 06, 2012 4:51 AM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH Version 2][RFA]Improving register pressure directed hoist > > On 11/02/2012 0

RE: [PATCH Version 2][RFA]Improving register pressure directed hoist

> -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Tuesday, November 06, 2012 9:04 PM > To: 'Jeff Law' > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [PATCH Version 2][RFA]Impro

RE: [PATCH Version 2][RFA]Improving register pressure directed hoist

> -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Friday, November 09, 2012 9:58 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH Version 2][RFA]Improving register pressure directed hoist > > On 11/07/2012 02:05 PM, Bin

[GCC ARM-Embedded-4_7]Back port r193425(improving reger pressure hoisting) from TRUNK

Hi, I back ported r193425 from TRUNK to GCC ARM-Embedded-4_7 branch as r193495. Thanks Backport from mainline r193425 2012-11-12 Bin Cheng * gcse.c (struct bb_data): Add new fields, old_pressure, live_in and backup. (get_regno_pressure_class): Add

[PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target

-uninit.c now and should be pruned. I have already implemented a quick fix and it works for our scenario. I can take this problem once I get some time. This is an backend patch and not a bug fix, I am not sure whether it can go in trunk or I have to wait for GCC4.9? Thanks 2012-11-16 Bin Cheng

RE: [PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target

> -Original Message- > From: Matthew Gretton-Dann [mailto:matthew.gretton-d...@linaro.org] > Sent: Friday, November 16, 2012 6:30 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target > > O

RE: [PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target

> -Original Message- > From: Matthew Gretton-Dann [mailto:matthew.gretton-d...@linaro.org] > Sent: Monday, November 19, 2012 8:20 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target > > O

RE: [PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target

> -Original Message- > From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > Sent: Wednesday, November 21, 2012 6:02 AM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH ARM]Define LOGICAL_OP_NON_SHORT_CIRCUIT for ARM target > > On F

[Patch Ping] Fix problem that hardreg_cprop opportunities are missed on thumb1GCC

> -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Wednesday, October 10, 2012 5:58 PM > To: gcc-patches@gcc.gnu.org > Cc: Ramana Radhakrishnan; Richard Earnshaw; 'Richard Sandifor

[GCC ARM-Embedded-4_7]Back port r191457/r193687(prefer short-circuit on ARMv6m) from TRUNK

Hi, I back ported r193687/r191457 from TRUNK to GCC ARM-Embedded-4_7 branch as r193744/r193745. Thanks ChangeLog/r193687 Backport from mainline r193687 2012-11-21 Bin Cheng * config/arm/arm-cores.def (cortex-m0plus): Use v6m. * config/arm/arm-protos.h

RE: [PING Updated]: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1

> -Original Message- > From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > Sent: Saturday, November 24, 2012 7:20 AM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan; Richard Earnshaw; Richard > Sandiford > Subject: Re: [PING Updated]

[PATCH ARM] Disable "-fira-hoist-pressure" on Thumb2

ses performance regression in some cases on Thumb2, so this patch disables the option on Thumb2 and modify the corresponding test cases. Tested on arm-none-eabi/M3, is it OK? Thanks. 2012-11-21 Bin Cheng * config/arm/arm.c (arm_option_override): Disable option -fira-hoist-pre

RE: [PATCH ARM] Disable "-fira-hoist-pressure" on Thumb2

> -Original Message- > From: Richard Earnshaw > Sent: Wednesday, November 28, 2012 2:02 AM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH ARM] Disable "-fira-hoist-pressure" on Thumb2 > > On 27/11/12 10:10, Bin Cheng wrote:

[GCC ARM-Embedded-4_7]Back port r193841(hardreg cprop on Thumb1) from TRUNK

Hi, I back ported r193841 from TRUNK to ARM Embedded-4_7-branch as r193881. Thanks.

[PATCH GCC/ARM] Fix big size regression in register renaming for thumb2 instruction set

gister renaming disabled. I tested the patches on cortex-m3 with and without register renaming, and on x86 with register renaming. I will apply this patch into ARM Embedded-4_7-branch and commit it to TRUNK after approval. Thanks. 2012-11-30 Bin Cheng * config/arm/arm-cores.def (corte

[GCC ARM-Embedded-4_7/Commit]Disable -fira-hoist-pressure on Thumb2

Hi, I committed the patch disabling "-fira-hoist-pressure" on Thumb2 to ARM Embedded-4_7 branch as r193979. Thanks. gcc/ChangeLog.arm 2012-11-30 Bin Cheng * config/arm/arm.c (arm_option_override): Disable option -fira-hoist-pressure on Thumb2. gcc/testsuite/Cha

[GCC ARM-Embedded-4_7/Commit]Fix size regression of regrename on Thumb2

Hi, I committed the patch fixing size regression of regrename on Thumb2 to ARM Embedded-4_7 branch as r193980. Thanks. gcc/ChangeLog.arm 2012-11-30 Bin Cheng * config/arm/arm-protos.h (tune_params): Add preferred_renaming_class. * config/arm/arm.c (arm_slowmul_tune

RE: [PATCH ARM] Disable "-fira-hoist-pressure" on Thumb2

> -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Wednesday, November 28, 2012 9:48 AM > To: Richard Earnshaw > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [PATCH ARM] Disable "-fira

[PATCH arm/embedded-4_7-branch]fix fialure of mtune option

Hi, This patch fixes failure of command "arm-none-eabi-gcc -O2 -mthumb -mtune=cortex-m4 ..." on arm/embedded-4_7-branch by removing the assertion in arm_cortex_v7m_branch_cost. Is it OK? Thanks. 2013-06-06 Bin Cheng * config/arm/arm.c (arm_cortex_v7m_branch_cost): Remove

[PATCH GCC]Consider NOP_EXPR and CONVERT_EXPR as equal nodes in operand_equal_p

ersion 23>> This patch fixes the problem. Please refer to http://gcc.gnu.org/ml/gcc/2013-05/msg00199.html for more information. Bootstrap and test on x86 and cortex-a15. Is it OK? Thanks. bin 2013-06-13 Bin Cheng * fold-const.c (operand_equal_p): Consider NOP_EXPR and CONVE

[PATCH GCC]Check the code to be executed for COND_EXEC in noop_move_p

x-a15. Is it OK? Thanks. bin 2013-06-13 Bin Cheng * rtlanal.c (noop_move_p): Check the code to be executed for COND_EXEC. Index: gcc/rtlanal.c === --- gcc/rtlanal.c (revision 199949) +++ gcc/rtlanal.c

RE: [PATCH GCC]Consider NOP_EXPR and CONVERT_EXPR as equal nodes in operand_equal_p

> -Original Message- > From: Richard Biener [mailto:richard.guent...@gmail.com] > Sent: Thursday, June 13, 2013 3:51 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Consider NOP_EXPR and CONVERT_EXPR as equal nodes in > operand_equal_p >

RE: [PATCH GCC]Check the code to be executed for COND_EXEC in noop_move_p

> -Original Message- > From: Eric Botcazou [mailto:ebotca...@adacore.com] > Sent: Thursday, June 13, 2013 3:36 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Check the code to be executed for COND_EXEC in > noop_move_p > &

[PATCH GCC]Fix PR57540, try to choose scaled_offset address mode when expanding array reference

cmp r3, #0 bge .L5 uxtbr2, r2 Bootstrap and test on x86/arm, any comments? Thanks. bin 2013-06-13 Bin Cheng PR target/57540 * emit-rtl.c (offset_address): Try to force ADDR into register and generate reg+offset if addr+offset is

[PATCH RFC]Pair load store instructions using a generic scheduling fusion pass

by default on non-armv7 processors. I may investigate the failure and try to enable the pass for all arm targets in the future. So any comments on this? 2014-09-30 Bin Cheng Mike Stump * timevar.def (TV_SCHED_FUSION): New time var. * passes.def (pass_

[PATCH GCC]Improve candidate selecting in IVOPT

b. As for the compilation time, the newly added function actually is one iteration of previous selection algorithm, it should be much faster than previous process. I also added one target dependent test case. Bootstrap and test on x86_64, test on aarch64. Any comments? 2014-09-30 Bin

RE: [PATCH GCC]Fix PR57540, try to choose scaled_offset address mode when expanding array reference

> -Original Message- > From: Eric Botcazou [mailto:ebotca...@adacore.com] > Sent: Saturday, June 15, 2013 5:37 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Fix PR57540, try to choose scaled_offset address mode > when expanding arra

RE: [PATCH GCC]Fix PR57540, try to choose scaled_offset address mode when expanding array reference

> -Original Message- > From: Eric Botcazou [mailto:ebotca...@adacore.com] > Sent: Monday, June 17, 2013 3:32 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Fix PR57540, try to choose scaled_offset address mode > when expanding array

RE: [PATCH GCC]Fix PR57540, try to choose scaled_offset address mode when expanding array reference

> -Original Message- > From: Eric Botcazou [mailto:ebotca...@adacore.com] > Sent: Monday, June 17, 2013 4:42 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH GCC]Fix PR57540, try to choose scaled_offset address mode > when expanding array refere

[PING] Two patches pending

Hi, FW: [PATCH GCC]Relax the probability condition in CE pass when optimizing for code size http://gcc.gnu.org/ml/gcc-patches/2013-03/msg00969.html [PATCH ARM]Extend thumb1_reorg to save more comparison instructions http://gcc.gnu.org/ml/gcc-patches/2013-04/msg01057.html Thanks. bin

[PATCH GCC/ARM]Disable "-fira-hoist-pressure" on Thumb2

ifying the corresponding test cases. Tested on arm-none-eabi/M3, is it OK? Thanks. bin 2013-04-25 Bin Cheng * common.opt (flag_ira_hoist_pressure): Initialize to 2. * doc/invoke.texi (-fira-hoist-pressure): Disabled by default on Thumb2 instruction set. * config

RE: FW: [PATCH GCC]Relax the probability condition in CE pass when optimizing for code size

> -Original Message- > From: Eric Botcazou [mailto:ebotca...@adacore.com] > Sent: Wednesday, July 10, 2013 5:06 PM > To: Bin Cheng > Cc: gcc-patches@gcc.gnu.org > Subject: Re: FW: [PATCH GCC]Relax the probability condition in CE pass when > optimizing for code size &

RE: [PING] Two patches pending

Ping this patch: > > [PATCH ARM]Extend thumb1_reorg to save more comparison instructions > > http://gcc.gnu.org/ml/gcc-patches/2013-04/msg01057.html Thanks. bin > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Saturday, July 20, 2013 1:34 AM

RE: [PATCH GCC/ARM]Disable "-fira-hoist-pressure" on Thumb2

ping. Thanks. bin > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Tuesday, July 09, 2013 4:08 PM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH GCC/ARM]Disable "-fira-hoist-pres

[PATCH ARM-Embedded-4_7-branch] fixing incoorect instruction length in checkin r193980

applied to ARM-Embedded-4_7-branch as r196368. Thanks. 2013-03-01 Bin Cheng * config/arm/arm.md (*arm_addsi3, *arm_subsi3_insn, *arm_mulsi3_v6) (*arm_andsi3_insn, andsi_notsi_si, *iorsi3_insn, *arm_xorsi3) (*arm_shiftsi3): Change attribute length from 2 to

RE: [PATCH ARM-Embedded-4_7-branch] fixing incoorect instruction length in checkin r193980

My bad for missing the patch. As stated in previous message, the patch has already been applied to ARM-Embedded-4_7-Branch. Thanks. > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Bin Cheng > Sent: Friday, Marc

FW: [PATCH GCC/pr56124] Don't prefer memory if the source of load operation has side effect

Sorry for the wrong list. -Original Message- From: Bin Cheng [mailto:bin.ch...@arm.com] Sent: Monday, March 25, 2013 3:00 PM To: g...@gcc.gnu.org Subject: [PATCH GCC/pr56124] Don't prefer memory if the source of load operation has side effect Hi, As reported in PR56124, IRA c

FW: [PATCH GCC]Relax the probability condition in CE pass when optimizing for code size

Wrong list. -Original Message- From: Bin Cheng [mailto:bin.ch...@arm.com] Sent: Monday, March 25, 2013 3:01 PM To: g...@gcc.gnu.org Subject: [PATCH GCC]Relax the probability condition in CE pass when optimizing for code size Hi, The CE pass has been adapted to work with the probability

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