[PATCH GCC]Enable vect_cond_mixed for AArch64.

[Bin Cheng]

Hi,
After supporting all vcond/vcondu patterns in AArch64 backend, now we can 
vectorize VEC_COND_EXPR with different type in comparison operands and value 
operands on AArch64.  GCC uses vect_cond_mixed to control such test cases, for 
now, there are below cases affected by it:

pr61194.c
    This was failed for all targets, but was just fixed by my previous tree 
ifcvt patch.
slp-cond-2-big-array.c
slp-cond-2.c
vect-cond-10.c
vect-cond-8.c
vect-cond-9.c

They will start passing after this patch.

Test on AArch64.  Is it OK?

Thanks,
bin

gcc/testsuite/ChangeLog
2016-05-12  Bin Cheng  <bin.ch...@arm.com>

        * lib/target-supports.exp (check_effective_target_vect_cond_mixed):
        Add aarch64*-*-*.
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 04ca176..db6b01e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5007,6 +5007,7 @@ proc check_effective_target_vect_cond_mixed { } {
     } else {
        set et_vect_cond_mixed_saved 0
        if { [istarget i?86-*-*] || [istarget x86_64-*-*]
+            || [istarget aarch64*-*-*]
             || [istarget powerpc*-*-*] } {
           set et_vect_cond_mixed_saved 1
        }