* H. J. Lu:
> Add preserve_none attribute which is similar to no_callee_saved_registers
> attribute, except on x86-64, r12, r13, r14, r15, rdi and rsi registers are
> used for integer parameter passing. This can be used in an interpreter
> to avoid saving/restoring the registers in functions whic
Add the `+cmpbr` option to enable the FEAT_CMPBR architectural
extension.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (cmpbr): New
option.
* config/aarch64/aarch64.h (TARGET_CMPBR): New macro.
* doc/invoke.texi (cmpbr): New option.
---
gcc/config
Hi all,
this patch fixes setting the coarray bounds correctly when a scalar char array
(i.e. CHARACTER(len=N)) is passed to function expecting a coarray. And when a
derived type coarray is passed to a function expecting a polymorphically typed
coarray as argument.
Regtests ok on x86_64-pc-linux-
store_bit_field_1 has an optimization where if a target is not a memory operand
and the entire value is being set from something larger we can just wrap a
subreg around the source and emit a move.
For vector constructors this is however problematic because the subreg means
that the expansion of th
> Am 25.06.2025 um 16:30 schrieb Martin Jambor :
>
> Hi,
>
> since r15-4695-gd17e672ce82e69 (Richard Biener: Assert finished
> vectorizer pattern COND_EXPR transition), the static const array
> cond_expr_maps is unused and when GCC is compiled with clang, it warns
> about that.
>
> This patc
Hi!
The following patch attempts to implement the C++26 P2927R3 - Inspecting
exception_ptr
paper (but not including P3748R0, I plan to play with it incrementally and
it will really depend on the Constexpr exceptions patch).
The function template is implemented using an out of line private method
Andre,
this series of patches (six in total) adds a new coarray backend library to
libgfortran. The library uses shared memory and processes to implement
running multiple images on the same node. The work is based on work started by
Thomas and Nicolas Koenig. No changes to the gfortran compile
Hi!
The following patch attempts to implement the C++26 P2830R10 - Constexpr Type
Ordering paper, with a minor change that std::type_order class template
doesn't derive from integer_constant, because std::strong_ordering is not
a structural type (except in MSVC), so instead it is just a class temp
This is patch #1 of 3 that adds the support that can be used in developing GCC
support for potential future PowerPC processors. With all 3 patches, the tuning
for the 'future' processor is the same as power10 and power11. It may be in the
future this tuning will change as any future PowerPC proce
Hi,
when building GCC with clang, it warns that the private member suffix
in class cp_coroutine_transform (defined in gcc/cp/coroutines.h) is
not used which indeed looks like it is the case. This patch therefore
removes it.
Bootstrapped and tested on x86_64-linx. OK for master?
Alternatively,
On 6/25/25 7:29 AM, Nathaniel Shead wrote:
On Tue, Jun 24, 2025 at 11:14:51AM -0400, Jason Merrill wrote:
On 6/24/25 10:16 AM, Nathaniel Shead wrote:
On Tue, Jun 24, 2025 at 01:03:53PM +0200, Jakub Jelinek wrote:
Hi!
The following patch implements the P3618R0 paper by tweaking pedwarn
conditi
For tcpsock_test.go in libgo tests,
commit aba3b9d3a48a0703fd565f7c5f0caf604f59970b
Author: H.J. Lu
Date: Fri May 9 07:17:07 2025 +0800
x86: Extend the remove_redundant_vector pass
added an instruction:
(insn 501 101 102 21 (set (reg:V2DI 234)
(vec_duplicate:V2DI (reg:DI 111 [ _4
On Tue, Jun 24, 2025 at 2:21 PM H.J. Lu wrote:
>
> Add debug dump for the remove_redundant_vector pass with the following
> output:
>
> Replace:
>
> (insn 7 4 8 2 (set (reg:V2DI 103)
> (const_vector:V2DI [
> (const_int 0 [0]) repeated x2
> ])) "x.c":8:13 2406 {m
Add the `+cmpbr` option to enable the FEAT_CMPBR architectural
extension.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (cmpbr): New
option.
* config/aarch64/aarch64.h (TARGET_CMPBR): New macro.
* doc/invoke.texi (cmpbr): New option.
---
gcc/config
From: panciyan
This patch would like to support signed scalar SAT_ADD IMM form 2
Form2:
T __attribute__((noinline)) \
sat_s_add_imm_##T##_fmt_2##_##INDEX (T x)\
{\
T sum = (T)((UT)x
The function `vect_check_gather_scatter` requires the `base` of the load
to be loop-invariant and the `off`set to be not loop-invariant. When faced
with a scenario where `base` is not loop-invariant, instead of giving up
immediately we can try swapping the `base` and `off`, if `off` is
actually loo
If gfortran will have a shared-memory coarray implemented, it would be
great to also drop the requirement to pass -fcoarray. Other compilers
have trended in the direction of dropping the flag too, including Cray and
NAG.
Even all these years after Fortran 2008 introduced multi-image execution, I
On Tue, Jun 24, 2025 at 4:54 AM Cui, Lili wrote:
> > > > From: Lili Cui
> > > >
> > > > Hi Uros,
> > > >
> > > > I need to remove another assertion in the shrink wrap separate patch.
> > > Added two cases for changing the CHECK_STACK_LIMIT value.
> > > >
> > > > The default values for CHECK_STAC
This is patch #3 of 3 to add -mcpu=future support to the PowerPC.
Compared to the previous version of tis patch, I update a comment to say
_ARCH_FUTURE instead of _ARCH_PWR11 that was a typo.
This patch adds simple tests for -mcpu=future.
I have tested these patches on both big endian and little
On Tue, Jun 24, 2025 at 5:40 PM Richard Sandiford
wrote:
>
> process_uses_of_deleted_def seems to have been written on the assumption
> that non-degenerate phis would be explicitly deleted by an insn_change,
> and that the function therefore only needed to delete degenerate phis.
> But that was in
Extract the hardcoded values for the minimum PC-relative displacements
into named constants and document them.
gcc/ChangeLog:
* config/aarch64/aarch64.md (BRANCH_LEN_P_128MiB): New constant.
(BRANCH_LEN_N_128MiB): Likewise.
(BRANCH_LEN_P_1MiB): Likewise.
(BRANCH_LE
On Tue, Jun 17, 2025 at 8:54 PM Cui, Lili wrote:
>
>
>
> > -Original Message-
> > From: H.J. Lu
> > Sent: Monday, June 16, 2025 10:08 PM
> > To: Jan Hubicka
> > Cc: Uros Bizjak ; Cui, Lili ; gcc-
> > patc...@gcc.gnu.org; Liu, Hongtao ;
> > mjgu...@gmail.com
> > Subject: [PATCH v3] x86: U
gcc/ChangeLog:
* tree-object-size.cc (access_with_size_object_size): Update comments
for pointers with .ACCESS_WITH_SIZE.
(collect_object_sizes_for): Propagate size info through GIMPLE_ASSIGN
for pointers with .ACCESS_WITH_SIZE.
gcc/testsuite/ChangeLog:
*
Hi,
this pass removes early-inlining from afdo pass since all inlining
should now happen from early inliner. I tedted this on spec and there
are 3 inlines happening here which are blocked at early-inline time by
hitting large function growth limit. We probably want to bypass that
limit, I will lo
On Wed, 25 Jun 2025 at 19:51, Jakub Jelinek wrote:
>
> Hi!
>
> The following patch attempts to implement the C++26 P2830R10 - Constexpr Type
> Ordering paper, with a minor change that std::type_order class template
> doesn't derive from integer_constant, because std::strong_ordering is not
> a str
On Wed, 25 Jun 2025 at 19:56, Jakub Jelinek wrote:
>
> Hi!
>
> The following patch attempts to implement the C++26 P2927R3 - Inspecting
> exception_ptr
> paper (but not including P3748R0, I plan to play with it incrementally and
> it will really depend on the Constexpr exceptions patch).
>
> The
Richard Biener writes:
> On Tue, 24 Jun 2025, Richard Sandiford wrote:
>
>> Tamar Christina writes:
>> > store_bit_field_1 has an optimization where if a target is not a memory
>> > operand
>> > and the entire value is being set from something larger we can just wrap a
>> > subreg around the sou
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk/branches?
-- >8 --
Here we end up with "error reporting routines re-entered" because
resolve_nondeduced_context isn't passing complain to mark_used.
PR c++/120756
gcc/cp/ChangeLog:
* pt.cc (resolve_nondeduced_context):
Give the `define_insn` rules used in lowering `cbranch4` to RTL
more descriptive and consistent names: from now on, each rule is named
after the AArch64 instruction that it generates. Also add comments to
document each rule.
gcc/ChangeLog:
* config/aarch64/aarch64.md (condjump): Rename to
Andreas reported openvino failed to build with LTO enabled with gcc-15
on RISC-V. The included .o file was enough for me to reproduce the
problem and it was trivial to then track it down to a fix I'd already
made to the trunk.
commit b93d8873cda88f0892c7782b274904fa8d3751fb
Author: Jeff Law
This is patch #2 of 3 to add -mcpu=future support to the PowerPC.
This patch makes -mtune=future use the same tuning decision as -mtune=power10 or
-mtune=power11.
I added a new attribute (power10_tuning) that says whether the current processor
is tuned like a power10. This is true for power10, p
> Am 25.06.2025 um 17:27 schrieb Karl Meakin :
>
> The function `vect_check_gather_scatter` requires the `base` of the load
> to be loop-invariant and the `off`set to be not loop-invariant. When faced
> with a scenario where `base` is not loop-invariant, instead of giving up
> immediately we c
On 6/25/25 1:28 PM, Marek Polacek wrote:
@@ -24604,7 +24604,7 @@ resolve_nondeduced_context (tree orig_expr,
tsubst_flags_t complain)
}
if (good == 1)
{
- mark_used (goodfn);
+ mark_used (goodfn, complain);
Actually, if we're going to pass complain, we s
Hi,
update of std module is missing.
Regards,
Maciej
On 5/21/25 10:16 PM, Nathaniel Shead wrote:
I'm not sure if there might be a better way to retrieve the prefix back
off an IDENTIFIER_NODE?
I don't think so, given that a target could do arbitrary transformations
in ASM_GENERATE_INTERNAL_LABEL.
I'm also not sure if IDENTIFIER_INTERNAL_P
cou
Andre,
I assumed that there would be some overhead, and perhaps bloat,
if -fcoarray=single were made the default. With the introduction
of a shmem runtime, changing the default is likely a GCC 17 change
and not something we should pursue for GCC 16.
Yes, I know that this uses shmem and not MPI.
On Wed, Jun 25, 2025 at 04:09:26PM +0200, Martin Jambor wrote:
> Hi,
>
> When compiling fortran/match.cc, clang emits a warning
>
> fortran/match.cc:5301:7: warning: variable 'p' is used uninitialized
> whenever 'if' condition is true [-Wsometimes-uninitialized]
>
> which looks accurate, so t
On Thu, Jun 26, 2025 at 6:20 AM H.J. Lu wrote:
>
> For tcpsock_test.go in libgo tests,
>
> commit aba3b9d3a48a0703fd565f7c5f0caf604f59970b
> Author: H.J. Lu
> Date: Fri May 9 07:17:07 2025 +0800
>
> x86: Extend the remove_redundant_vector pass
>
> added an instruction:
>
> (insn 501 101 102
On Thu, Jun 26, 2025 at 6:21 AM H.J. Lu wrote:
>
> On Tue, Jun 24, 2025 at 2:21 PM H.J. Lu wrote:
> >
> > Add debug dump for the remove_redundant_vector pass with the following
> > output:
> >
> > Replace:
> >
> > (insn 7 4 8 2 (set (reg:V2DI 103)
> > (const_vector:V2DI [
> >
> -Original Message-
> From: Andrew Pinski (QUIC)
> Sent: Wednesday, June 25, 2025 4:20 PM
> To: Andrew Pinski (QUIC) ; gcc-
> patc...@gcc.gnu.org
> Subject: RE: [PATCH] expand: Allow sibcalling for return
> structures in some cases [PR71761]
>
> > -Original Message-
> > From: And
On Thu, Jun 26, 2025 at 1:24 PM Hongtao Liu wrote:
>
> On Thu, Jun 26, 2025 at 6:20 AM H.J. Lu wrote:
> >
> > For tcpsock_test.go in libgo tests,
> >
> > commit aba3b9d3a48a0703fd565f7c5f0caf604f59970b
> > Author: H.J. Lu
> > Date: Fri May 9 07:17:07 2025 +0800
> >
> > x86: Extend the remo
Use the inner scalar mode of vector broadcast source in:
(set (reg:V8DF 394)
(vec_duplicate:V8DF (reg:V2DF 190 [ alpha ])))
to compute the vector mode for broadcast from vector source.
gcc/
PR target/120830
* config/i386/i386-features.cc (ix86_get_vector_cse_mode): Handle
vector broadc
On Thu, Jun 26, 2025 at 1:56 PM H.J. Lu wrote:
>
> On Thu, Jun 26, 2025 at 1:24 PM Hongtao Liu wrote:
> >
> > On Thu, Jun 26, 2025 at 6:20 AM H.J. Lu wrote:
> > >
> > > For tcpsock_test.go in libgo tests,
> > >
> > > commit aba3b9d3a48a0703fd565f7c5f0caf604f59970b
> > > Author: H.J. Lu
> > > Da
Since float vector constant
(const_vector:V4SF [(const_double:SF -QNaN [-QNaN]) repeated x4])
is an all 1s float vector constant, update the remove_redundant_vector
pass to replace
(insn 20 18 21 2 (set (reg:V4SF 124)
(const_vector:V4SF [
(const_double:SF -QNaN [-QNaN]) r
In the case of tailing call with a return of a structure, currently
all large structures are rejected. We can allow the case were the return
of the "tail call" function is setting the return value of the current
function. This allows for the musttail that is located in pr71761-1.c.
This should be
On Jun 25, 2025, Vladimir Makarov wrote:
> Alex, thanks for investigation of corner cases of register elimination.
You're welcome. Thanks for the reviews
> I guess it is too strict.
Yeah. I have a less strict version that relaxes it enough to not
regress acats-4 on arm-linux-gnueabihf, and t
On Thu, Jun 26, 2025 at 1:59 PM H.J. Lu wrote:
>
> Use the inner scalar mode of vector broadcast source in:
>
> (set (reg:V8DF 394)
>(vec_duplicate:V8DF (reg:V2DF 190 [ alpha ])))
>
> to compute the vector mode for broadcast from vector source.
ix86_get_vector_cse_mode (unsigned int si
On Thu, Jun 26, 2025 at 2:02 PM H.J. Lu wrote:
>
> Since float vector constant
>
> (const_vector:V4SF [(const_double:SF -QNaN [-QNaN]) repeated x4])
>
> is an all 1s float vector constant, update the remove_redundant_vector
> pass to replace
>
> (insn 20 18 21 2 (set (reg:V4SF 124)
> (cons
On Thu, Jun 26, 2025 at 2:11 PM Hongtao Liu wrote:
>
> On Thu, Jun 26, 2025 at 1:59 PM H.J. Lu wrote:
> >
> > Use the inner scalar mode of vector broadcast source in:
> >
> > (set (reg:V8DF 394)
> >(vec_duplicate:V8DF (reg:V2DF 190 [ alpha ])))
> >
> > to compute the vector mode for bro
> -Original Message-
> From: Andrew Pinski (QUIC)
> Sent: Monday, June 23, 2025 11:39 AM
> To: Andrew Pinski (QUIC) ; gcc-
> patc...@gcc.gnu.org
> Subject: RE: [PATCH] expand: Allow sibcalling for return
> structures in some cases [PR71761]
>
> > -Original Message-
> > From: Andre
On Wed, Jun 25, 2025 at 3:35 PM H.J. Lu wrote:
>
> Add preserve_none attribute which is similar to no_callee_saved_registers
> attribute, except on x86-64, r12, r13, r14, r15, rdi and rsi registers are
> used for integer parameter passing. This can be used in an interpreter
> to avoid saving/rest
On Wed, Jun 25, 2025 at 4:59 PM Florian Weimer wrote:
>
> * H. J. Lu:
>
> > Add preserve_none attribute which is similar to no_callee_saved_registers
> > attribute, except on x86-64, r12, r13, r14, r15, rdi and rsi registers are
> > used for integer parameter passing. This can be used in an inter
Trying again, hopefully formatted correctly this time, and now including a test
case. Test case fails with original code, passes with patch. Command to execute
test case:
make check-c RUNTESTFLAGS="--target-board='arm-sim/-march=armv5t'
arm.exp=pr117366.c"
gcc/ChangeLog:
* arm.cc: fix
On 6/25/25 2:51 PM, Jakub Jelinek wrote:
Hi!
The following patch attempts to implement the C++26 P2830R10 - Constexpr Type
Ordering paper, with a minor change that std::type_order class template
doesn't derive from integer_constant, because std::strong_ordering is not
a structural type (except i
Fixing issue with thumb1 code generation clobbering register. Detailed in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117468
Test case included; run with:
make check-c RUNTESTFLAGS="--target-board='arm-sim/-march=armv5t'
arm.exp=pr117468.c"
gcc/ChangeLog:
* arm.cc: fix thumb1 prologue
On Wed, 25 Jun 2025, Richard Biener wrote:
> On Wed, 25 Jun 2025, Robin Dapp wrote:
>
> > Hi,
> >
> > this patch adds simple misalignment checks for gather/scatter
> > operations. Previously, we assumed that those perform element accesses
> > internally so alignment does not matter. The riscv
At least my introduction of a new --param made raising the LTO IL
minor necessary, so do it now, also in preparation for GCC 15.2.
Will push shortly.
* lto-streamer.h (LTO_minor_version): Bump to 1.
---
gcc/lto-streamer.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
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