Hi!
extract_bit_field can't handle extraction of non-mode precision
from complex mode operands which don't live in memory, e.g. gen_lowpart
crashes on those.
The following patch in that case defers the extract_bit_field call
until op0 is forced into memory.
Bootstrapped/regtested on x86_64-linux
From: Pan Li
This patch would like to remove the unnecessary option for the
strided load/store testcases. After fix the option from the rvv.exp,
both the O2 and O3 will be passed to the test files for rtl expand
dump check but the O2 has 2 time for IFN while the O3 has 4 times with
-fvectorize s
On Mon, 18 Nov 2024, Eric Gallager wrote:
> On Fri, Nov 15, 2024 at 11:08 AM Jakub Jelinek wrote:
> >
> > Hi!
> >
> > The following patch adds a new tristate option for optimizations related to
> > replaceable global operators new/delete.
> > The option isn't called -fassume-sane-operator-new (wh
For the BWX case we have a pessimisation in `alpha_expand_block_move'
for HImode loads where we place the data loaded into a HImode register
as well, therefore losing information that indeed the data loaded has
already been zero-extended to the full DImode width of the register.
Later on when
Eliminate a redundant bitwise inclusive OR operation on the insertion of
constant zero into a bit-field, improving code produced at `-O2' from an
output sequence such as:
mov $31,$3 # Redundant!
ldq_u $1,7($16)
insqh $3,$16,$3
On Mon, 18 Nov 2024, Victor Do Nascimento wrote:
> On 11/5/24 07:39, Richard Biener wrote:
> > On Tue, 5 Nov 2024, Victor Do Nascimento wrote:
> >
> >> The current codegen code to support VF's that are multiples of a simdclone
> >> simdlen rely on BIT_FIELD_REF to create multiple input vectors.
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* g++.dg/opt/pr69175.C: Added option "-mcpu=unset".
Signed-off-by: Torbjörn SVENSSON
---
gcc/testsuite/g++.dg/opt/pr69175.C | 2 +-
1 file changed, 1 insertion(+), 1
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/acle/pacbti-m-predef-1.c: Use effective-target
arm_arch_v8_1m_main.
* gcc.target/arm/acle/pacbti-m-predef-2.c: Likewise.
* gcc.t
From: Pan Li
The testcases of vector strided load/store are designed to pick up
different sorts of optimization options but actually these option
are ignored according to the Execution log of gcc.log. This patch
would like to make it correct, and then you will see the build option
similar as bel
Hi!
I'd like to ping various stage1 patches.
Padding zeroing patchset
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/665565.html
expr, c, gimplify: Don't clear whole unions [PR116416]
This one needs C FE review (especially if the testcase matches
the actual
The commit 2c0fa3ecf70d199af18785702e9e0548fd3ab793 reuses VALUEs on sp
adjustments. We can generalize the idea and reuse VALUEs on other
registers. This can help the postreload pass find more opportunities to
simplify insns.
The following assembly code is generated from the testcase using the c
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/pac-1.c: Use effective-target
arm_arch_v8_1m_main_pacbti.
* gcc.target/arm/pac-1.c: Likewise.
* gcc.target/arm/pac-2.c: Likewise
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/small-multiply-m0-1.c: Use effective-target
arm_arch_v6m and added option "-march=unset".
* gcc.target/arm/small-multiply-m0-2.c: Likewi
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/vect-early-break-cbranch.c: Use
effective-target arm_arch_v8a_hard.
Signed-off-by: Torbjörn SVENSSON
---
gcc/testsuite/gcc.target/arm/vect-ea
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/thumb2-slow-flash-data-2.c: Use
effective-target arm_arch_v7em and added option "-march=unset
-mfpu=auto".
* gcc.target/arm/thum
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/cortex-m55-nodsp-flag-hard.c: Added option
"-march=unset".
* gcc.target/arm/cortex-m55-nodsp-flag-softfp.c: Likewise.
* gcc.targ
Update test case to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/lto/pr96939_0.c: Use effective-target
arm_arch_v8a.
* gcc.target/arm/lto/pr96939_1.c: Remove dg-options.
Signed-off-by: Torbjörn SVENSSO
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* g++.dg/other/pr56184.C: Use effective-target
arm_arch_v7a_neon and arm_arch_v7a_thumb.
* g++.dg/other/pr59985.C: Use effective-target
arm_arch_
> -Original Message-
> From: Andrew Pinski
> Sent: Friday, November 15, 2024 7:16 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; ktkac...@gcc.gnu.org; Richard Sandiford
>
> Subject: Re: [PATCH]AArch64 Suppress default options when march or mcpu used
> i
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/bfloat16_scalar_1_2.c: Added option
"-march=unset".
* gcc.target/arm/bfloat16_scalar_2_1.c: Likewise.
* gcc.target/arm/bfloat16_
On Tue, Nov 19, 2024 at 10:25:16AM +0100, Richard Biener wrote:
> I think it's pretty clear and easy to describe to users what "m " and
> what "mC" do. But with "pure" this is an odd intermediate state. For both
> "m " and "mP" you suggest above the new/delete might modify their
> global state b
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/acle/crc_hf_1.c: Use effective-target
arm_arch_v8a_hard and added option "-mcpu=unset".
Signed-off-by: Torbjörn SVENSSON
---
gcc/testsuite/gc
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.target/arm/pure-code/no-literal-pool-m0.c: Use
effective-target arm_cpu_cortex-m0.
* gcc.target/arm/pure-code/no-literal-pool-m23.c: Use
ef
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* g++.dg/ext/pr57735.C: Use effective-target arm_cpu_xscale_arm.
Signed-off-by: Torbjörn SVENSSON
---
gcc/testsuite/g++.dg/ext/pr57735.C | 7 +++
1 file changed,
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* gcc.dg/pr41574.c: Added option "-mcpu=unset".
* gcc.dg/pr59418.c: Likewise.
* lib/target-supports.exp (add_options_for_vect_early_break):
Likewi
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* g++.target/arm/mve/general-c++/nomve_fp_1.c: Added option
"-mcpu=unset".
Signed-off-by: Torbjörn SVENSSON
---
gcc/testsuite/g++.target/arm/mve/general-c++/n
Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.
gcc/testsuite/ChangeLog:
* g++.target/arm/pr103676.C: Use effective-target
arm_cpu_cortex_m7.
* gcc.target/arm/no-volatile-in-it.c: Likewise.
* gcc.target/arm/fma-sp.c: U
> On Tue, Nov 19, 2024 at 10:25:16AM +0100, Richard Biener wrote:
> > I think it's pretty clear and easy to describe to users what "m " and
> > what "mC" do. But with "pure" this is an odd intermediate state. For both
> > "m " and "mP" you suggest above the new/delete might modify their
> > glob
On Tue, Nov 19, 2024 at 09:35:06AM +0100, Richard Biener wrote:
> > This all seems excessively complicated; can't it be simplified a bit?
>
> I'd like to second this - I don't see value in adding the "intermediate"
> state which we never had. We for quite some time had two extremes, if
> we want
* gcc.target/m68k/crash1.c (seq_printf): Add prototype.
* gcc.target/m68k/pr63347.c (oof): Add missing parameter.
---
gcc/testsuite/gcc.target/m68k/crash1.c | 2 +-
gcc/testsuite/gcc.target/m68k/pr63347.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/t
On Tue, 19 Nov 2024, Jakub Jelinek wrote:
> On Tue, Nov 19, 2024 at 09:35:06AM +0100, Richard Biener wrote:
> > > This all seems excessively complicated; can't it be simplified a bit?
> >
> > I'd like to second this - I don't see value in adding the "intermediate"
> > state which we never had. W
On Tue, 19 Nov 2024, Jan Hubicka wrote:
> >
> > The problem with the two states we had/have is that they are too extreme.
> >
> > Our old one (i.e. those "mC" etc.) is too strong and doesn't have any
> > backup in the standard, I think the PR101480 testcase is perfectly
> > valid C++ and so it p
>
> The problem with the two states we had/have is that they are too extreme.
>
> Our old one (i.e. those "mC" etc.) is too strong and doesn't have any
> backup in the standard, I think the PR101480 testcase is perfectly
> valid C++ and so it probably isn't a good idea to enable such behavior
> b
> On Tue, 19 Nov 2024, Jan Hubicka wrote:
>
> > >
> > > The problem with the two states we had/have is that they are too extreme.
> > >
> > > Our old one (i.e. those "mC" etc.) is too strong and doesn't have any
> > > backup in the standard, I think the PR101480 testcase is perfectly
> > > valid
> > On Tue, 19 Nov 2024, Jan Hubicka wrote:
> >
> > > >
> > > > The problem with the two states we had/have is that they are too
> > > > extreme.
> > > >
> > > > Our old one (i.e. those "mC" etc.) is too strong and doesn't have any
> > > > backup in the standard, I think the PR101480 testcase i
On Tue, 19 Nov 2024, Jakub Jelinek wrote:
> Hi!
>
> extract_bit_field can't handle extraction of non-mode precision
> from complex mode operands which don't live in memory, e.g. gen_lowpart
> crashes on those.
> The following patch in that case defers the extract_bit_field call
> until op0 is for
On Tue, 19 Nov 2024, Jakub Jelinek wrote:
> Hi!
>
> The following patch handles PAREN_EXPR in bitint lowering, and handles it
> as an optimization barrier, so that temporary arithmetics from PAREN_EXPR
> isn't mixed with temporary arithmetics from outside of the PAREN_EXPR.
>
> Bootstrapped/regt
On Tue, 19 Nov 2024, Jakub Jelinek wrote:
> On Tue, Nov 19, 2024 at 11:23:31AM +0100, Jakub Jelinek wrote:
> > On Tue, Nov 19, 2024 at 10:25:16AM +0100, Richard Biener wrote:
> > > I think it's pretty clear and easy to describe to users what "m " and
> > > what "mC" do. But with "pure" this is a
The loop unrolling code assumes that one third of all volatile accesses
can be possibly optimized away which is of course not true. This leads
to excessive unrolling in some cases. The following tracks the number
of stmts with side-effects as those are not eliminatable later and
only assumes one
From: Eric Botcazou
The case and if expressions are exactly the conditional expressions.
gcc/ada/ChangeLog:
* exp_util.ads (Within_Case_Or_If_Expression): Rename into...
(Within_Conditional_Expression): ...this.
* exp_util.adb (Within_Case_Or_If_Expression): Rename into.
On 11/15/24 8:31 AM, Dimitar Dimitrov wrote:
When configuring GCC for RV32EC with:
./configure \
--target=riscv32-none-elf \
--with-multilib-generator="rv32ec-ilp32e--" \
--with-abi=ilp32e \
On Sun, Nov 17, 2024 at 4:28 AM Lewis Hyatt wrote:
>
> Currently, when we allocate a gphi object, we round up the capacity for the
> trailing arguments array such that it will make full use of the page size
> that ggc will allocate. While there is also an explicit minimum of 2
> arguments, in prac
Am Dienstag, dem 19.11.2024 um 09:18 -0800 schrieb Kees Cook:
> On Tue, Nov 19, 2024 at 05:41:13PM +0100, Martin Uecker wrote:
> > Am Dienstag, dem 19.11.2024 um 10:47 -0500 schrieb Marek Polacek:
> > > On Mon, Nov 18, 2024 at 07:10:35PM +0100, Martin Uecker wrote:
> > > > Am Montag, dem 18.11.2024
On 19/11/2024 10:24, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/cortex-m55-nodsp-flag-hard.c: Added option
> "-march=unset".
> * gcc.target/arm/cort
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr117595.c: Restrict to non vector targets.
Signed-off-by: Edwin L
Alex Coplan writes:
> On 19/11/2024 17:02, Richard Sandiford wrote:
>> Sorry for the slow review. Finally catching up on backlog.
>>
>> Richard Biener writes:
>> > On Mon, 28 Oct 2024, Alex Coplan wrote:
>> >
>> >> This allows us to vectorize more loops with early exits by forcing
>> >> peeling
On 11/19/24 2:08 PM, Edwin Lu wrote:
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr117595.c: Restrict to n
On 11/19/24 12:01 PM, Jeff Law wrote:
Andreas reported GCC mis-compiled GAS for risc-v Thankfully he also
reduced it to a nice little testcase.
So the whole point of the pattern in question is to "reduce" the
constants by right shifting away common unnecessary bits in RTL
expressions like
On Tue, 15 Oct 2024, Jakub Jelinek wrote:
> --- gcc/testsuite/gcc.dg/gnu11-empty-init-1.c.jj 2024-10-15
> 16:14:23.411063701 +0200
> +++ gcc/testsuite/gcc.dg/gnu11-empty-init-1.c 2024-10-15 16:31:02.302984714
> +0200
> @@ -0,0 +1,199 @@
> +/* Test GNU C11 support for empty initializers. */
From: Eric Botcazou
The (minimal) expansion is now done by Build_Array_Aggr_Code in all cases,
which means that it must prevent the aggregate from being re-analyzed as
the RHS of the assignment, which may trigger a bogus warning and lead to
another useless rewriting.
The change also inlines Buil
Kyrylo Tkachov writes:
>> On 15 Nov 2024, at 12:33, Wilco Dijkstra wrote:
>>
>> Hi Kyrill,
>>
>>> This would make USE_NEW_VECTOR_COSTS effectively the default.
>>> Jennifer has been trying to do that as well and then to remove it (as it
>>> would be always true) but there are some codegen regr
Richard Biener writes:
> On Mon, 18 Nov 2024, Victor Do Nascimento wrote:
>
>> On 11/5/24 07:39, Richard Biener wrote:
>> > On Tue, 5 Nov 2024, Victor Do Nascimento wrote:
>> >
>> >> The current codegen code to support VF's that are multiples of a simdclone
>> >> simdlen rely on BIT_FIELD_REF to
On Tue, Nov 19, 2024 at 11:23:31AM +0100, Jakub Jelinek wrote:
> On Tue, Nov 19, 2024 at 10:25:16AM +0100, Richard Biener wrote:
> > I think it's pretty clear and easy to describe to users what "m " and
> > what "mC" do. But with "pure" this is an odd intermediate state. For both
> > "m " and "m
On 18/11/2024 12:00, Christophe Lyon wrote:
> Hi Torbjörn,
>
>
> On 11/18/24 10:37, Torbjorn SVENSSON wrote:
>>
>>
>> On 2024-11-08 20:37, Torbjorn SVENSSON wrote:
>>>
>>>
>>> On 2024-11-08 12:24, Richard Earnshaw (lists) wrote:
On 05/11/2024 20:06, Torbjörn SVENSSON wrote:
> Based on ho
On 11/19/24 1:30 AM, pan2...@intel.com wrote:
From: Pan Li
The testcases of vector strided load/store are designed to pick up
different sorts of optimization options but actually these option
are ignored according to the Execution log of gcc.log. This patch
would like to make it correct, an
On Mon, Nov 18, 2024 at 9:13 PM Richard Sandiford
wrote:
>
> In an attempt to reduce compile time, rtl-ssa computes the cost
> of existing instructions lazily rather than eagerly. However,
> this means that it might need to calculate the cost of an existing
> instruction while a change group is a
On 19/11/2024 10:23, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/small-multiply-m0-1.c: Use effective-target
> arm_arch_v6m and added option "-march=unset"
On 19/11/2024 10:23, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/thumb2-slow-flash-data-2.c: Use
> effective-target arm_arch_v7em and added option "-march=
On 19/11/2024 10:24, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
> * gcc.dg/pr41574.c: Added option "-mcpu=unset".
> * gcc.dg/pr59418.c: Likewise.
> * lib/target-supports.
On 19/11/2024 10:24, Torbjörn SVENSSON wrote:
> Update test case to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/lto/pr96939_0.c: Use effective-target
> arm_arch_v8a.
> * gcc.target/arm/lto/pr96939_
As reported in bug 114869, the C front end wrongly creates nullptr_t
as a built-in typedef; it should only be defined in . While
the type node needs a name for debug info generation, it doesn't need
to be a valid identifier; use typeof (nullptr) instead, similar to how
the C++ front end uses declt
Am Montag, dem 18.11.2024 um 21:31 + schrieb Qing Zhao:
>
> > On Nov 18, 2024, at 13:10, Martin Uecker wrote:
>
...
> So, I guess that the more accurate question is, for the following:
>
> struct annotated {
> int b;
> int *c __attribute__ ((counted_by (b)));
> } *p_array_annotated;
>
On 11/14/24 9:14 PM, Kito Cheng wrote:
AddressSanitizer has supported dynamic shadow offsets since 2016[1], but
GCC hasn't implemented this yet because targets using dynamic shadow
offsets, such as Fuchsia and iOS, are mostly unsupported in GCC.
However, RISC-V 64 switched to dynamic shadow o
On 19/11/2024 10:23, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/pure-code/no-literal-pool-m0.c: Use
> effective-target arm_cpu_cortex-m0.
> * gcc.ta
On 19/11/2024 10:24, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/bfloat16_scalar_1_2.c: Added option
> "-march=unset".
> * gcc.target/arm/bfloat16_sc
> -Original Message-
> From: Xi Ruoyao
> Sent: 16 November 2024 09:23
> To: Prathamesh Kulkarni ; josmy...@redhat.com;
> Matthew Malcomson ; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] PR81358: Enable automatic linking of libatomic
>
> External email: Use caution opening links or attac
On Tue, Nov 19, 2024 at 9:21 AM Andrew Pinski wrote:
>
> __builtin_aarch64_im_lane_boundsi is known not to throw or call back into
> another
> function since it will either folded into an NOP or will produce a compiler
> error.
>
> This fixes the ICE by fixing the missed optimization. It does no
__builtin_aarch64_im_lane_boundsi is known not to throw or call back into
another
function since it will either folded into an NOP or will produce a compiler
error.
This fixes the ICE by fixing the missed optimization. It does not fix the
underlying
issue with fold_marked_statements; which I fi
On 19/11/2024 17:02, Richard Sandiford wrote:
> Sorry for the slow review. Finally catching up on backlog.
>
> Richard Biener writes:
> > On Mon, 28 Oct 2024, Alex Coplan wrote:
> >
> >> This allows us to vectorize more loops with early exits by forcing
> >> peeling for alignment to make sure th
On 11/17/24 2:55 AM, shiyul...@iscas.ac.cn wrote:
From: yulong
This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and
xsfvfnrclipxfqf extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New.
* config/riscv/riscv.opt: New.
gcc/testsuite/ChangeL
On 11/15/24 8:21 PM, Liao Shihua wrote:
RISC-V N32 ABI means using 32-bit ABI on 64-bit ISA, the discussion in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/381 .
At this moment, N32 is supported batemental toolchain.
Three OpenSource RTOS using this feature and have been merged i
On 18/11/2024 11:13, Torbjörn SVENSSON wrote:
> Changes since v1:
>
> - Replaced fragile checks on constants with check for literal pool
> using "ldr r[0-9]+, \.L[0-9]+".
>
> Ok for trunk?
>
> --
>
> With the changes in r15-1579-g792f97b44ff, the constants have been
> updated.
> This patch dr
On Tue, Nov 19, 2024 at 9:55 AM Richard Biener
wrote:
>
> On Sun, Nov 17, 2024 at 4:25 AM Lewis Hyatt wrote:
> >
> > The array gimple_ops_offset_[], which is used to find the trailing op[]
> > array for a given gimple struct, is computed assuming that op[] will be
> > found at sizeof(tree) bytes
On Thu, 2024-11-14 at 15:27 -0500, Antoni Boucher wrote:
> It seems we don't need to do the cleanup in i386-builtins.cc anymore,
> so
> I removed it.
> David: Is it possible that your recent fixes for the GC within
> libgccjit
> also fixed the issue here?
>
> Here's the updated patch and answers
On Tue, 19 Nov 2024, Jakub Jelinek wrote:
> Hi!
>
> Apparently the middle-end/expansion can only handle {L,R}ROTATE_EXPR
> on types with mode precision, or large/huge BITINT_TYPE.
> So, the following patch uses the rotate exprs only in those cases
> where it can be handled, and emits code with sh
On 11/17/24 7:59 PM, Maciej W. Rozycki wrote:
Expand coverage for `__builtin_memcpy', primarily for "cpymemM" block
copy pattern, although with smaller sizes open-coded sequences may be
produced instead.
This verifies block sizes in bytes from 1 to 64, across byte alignments
of 1, 2, 4, 8 and
On 11/15/24 3:53 AM, Monk Chiang wrote:
This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
вт, 19 нояб. 2024 г. в 21:22, Georg-Johann Lay :
>
> This patch calculates more accurate shift costs, but makes
> the costs for larger offsets no more expensive than the costs
> for an unrolled shift.
>
> Ok for trunk?
Ok. Please apply.
Denis.
Hi,
Random request...
On Tue, Nov 19, 2024 at 11:14:38AM -0500, David Malcolm wrote:
> > Here's the updated patch and answers below.
> >
> > (GitHub link if you find it easier for review:
> > https://github.com/antoyo/libgccjit/pull/5)
> >
> > Thanks.
>
> Thanks; I looked over the patch via t
On Wed, 13 Nov 2024, Jakub Jelinek wrote:
> On Tue, Nov 12, 2024 at 06:34:39PM +0100, Jakub Jelinek wrote:
> > What do you think about this? So far lightly tested.
>
> Unfortunately bootstrap/regtest revealed some issues in the patch,
> the tree-ssa-ccp.cc changes break bootstrap because fntype
Am Dienstag, dem 19.11.2024 um 10:47 -0500 schrieb Marek Polacek:
> On Mon, Nov 18, 2024 at 07:10:35PM +0100, Martin Uecker wrote:
> > Am Montag, dem 18.11.2024 um 17:55 + schrieb Qing Zhao:
> > > Hi,
> > >
> > > I am working on extending “counted_by” attribute to pointers inside a
> > > stru
On Thu, 2023-11-30 at 17:16 -0500, Antoni Boucher wrote:
> All of these are fixed in this new patch.
> Thanks for the review.
Thanks for the updated patch.
I had said "OK with those fixed" on the older version and it looks like
you have indeed fixed the issues I noticed, so this updated patch is
Skipping these test cases that are not int16 clean (execution fail,
UB due to shift offset, etc).
Johann
--
testsuite/52641 - Skip test cases that are not 16-bit clean.
gcc/testsuite/
PR testsuite/52641
PR testsuite/116488
PR testsuite/116915
* gcc.dg/torture/pr
"H.J. Lu" writes:
> Adjust BLKmode argument size for parameter alignment for sibcall check.
>
> gcc/
>
> PR middle-end/117098
> * calls.cc (store_one_arg): Adjust BLKmode argument size for
> alignment padding for sibcall check.
>
> gcc/testsuite/
>
> PR middle-end/117098
> * gcc.dg/sibcall-12.c: N
Thanks, committed to trunk :)
On Wed, Nov 20, 2024 at 2:09 AM Jeff Law wrote:
>
>
>
> On 11/17/24 2:55 AM, shiyul...@iscas.ac.cn wrote:
> > From: yulong
> >
> > This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and
> > xsfvfnrclipxfqf extensions.
> >
> > gcc/ChangeLog:
> >
> >
LGTM
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-11-20 15:37
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF'
type condition error
This patch fix the wrong condition for RVVMF2BF. It should
Bug 115515 (plus its duplicate 117139) reports an ICE with constexpr
initializer for an integer type variable that is not of integer type.
Fix this by not calling int_fits_type_p unless the previous check for
an integer constant expression passes.
Bootstrapped with no regressions for x86_64-pc-lin
On 2024-11-20 14:54 钟居哲 wrote:
>
>Are you trying to fix this PR ?
Yes.
>117669 – RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error
>
>I think you should add PR target/117669 in the changelog
>
OK.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Feng Wang
>Date: 2024-11-20 14:50
>To: gcc-pat
On Thu, 2023-12-21 at 08:36 -0500, Antoni Boucher wrote:
> Hi.
> Here's the updated patch.
> Thanks.
Sorry for the delay in responding.
The updated patch is good for trunk - thanks!
Dave
>
> On Thu, 2023-12-07 at 20:15 -0500, David Malcolm wrote:
> > On Thu, 2023-12-07 at 17:34 -0500, Antoni B
On 11/19/24 10:29 AM, Andrew Carlotti wrote:
On Sun, Oct 27, 2024 at 04:00:43PM +, Yangyu Chen wrote:
Following the implementation of commit b8ce8129a5 ("Redirect call
within specific target attribute among MV clones (PR ipa/82625)"),
we can now optimize calls by invoking a versioned func
This patch fix the wrong condition for RVVMF2BF. It should be
TARGET_VECTOR_ELEN_BF_16.
gcc/ChangeLog:
PR target/117669
* config/riscv/vector-iterators.md:
Signed-off-by: Feng Wang
---
gcc/config/riscv/vector-iterators.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
On Wed, Nov 20, 2024 at 2:12 AM Richard Sandiford
wrote:
>
> "H.J. Lu" writes:
> > Adjust BLKmode argument size for parameter alignment for sibcall check.
> >
> > gcc/
> >
> > PR middle-end/117098
> > * calls.cc (store_one_arg): Adjust BLKmode argument size for
> > alignment padding for sibcall c
On Thu, 2024-01-25 at 16:04 -0500, Antoni Boucher wrote:
> Thanks for the review!
> On Wed, 2024-01-24 at 13:10 -0500, David Malcolm wrote:
> > On Thu, 2024-01-11 at 18:42 -0500, Antoni Boucher wrote:
> > > Hi.
> > > This patch fixes the bug 113343.
> > > I'm wondering if there's a better solution
> Had the discussion above been included in the patch I probably would
> have just acked it then :-) Now that I understand what you're doing,
> it's fine.
I see, thank you ;).
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, November 19, 2024 10:57 PM
To: Li, Pan2 ; gcc-patches@
This patch calculates more accurate shift costs, but makes
the costs for larger offsets no more expensive than the costs
for an unrolled shift.
Ok for trunk?
Johann
--
AVR: target/54378 - Reconsider the default shift costs.
This patch calculates more accurate shift costs, but makes
the costs
On 19/11/2024 10:23, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/arm/pr103676.C: Use effective-target
> arm_cpu_cortex_m7.
> * gcc.target/arm/no-volatile
Now that the C default is C23, we can use bool in avr.h
(which is still used in libgcc via tm.h).
bool is a keyword in C23, so no stdbool.h is required in libgcc.
No regressions. Ok for trunk?
Johan
--
AVR: Use more bool.
Now that the C default is C23, we can use bool in avr.h
(which is still
On 19/11/2024 10:23, Torbjörn SVENSSON wrote:
> Update test cases to use -mcpu=unset/-march=unset feature introduced in
> r15-3606-g7d6c6a0d15c.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/pac-1.c: Use effective-target
> arm_arch_v8_1m_main_pacbti.
> * gcc.target/arm/pac-1
On Thu, 14 Nov 2024, Jakub Jelinek wrote:
> The patch adjusts builtins (when we have them) corresponding to the APIs
> mentioned in the C2Y N3322 paper:
> 1) strndup and memset get one nonnull_if_nonzero attribute instead of
>nonnull
> 2) memcpy, memmove, strncpy, memcmp, strncmp get two nonnu
This fixes a few aarch64 specific testcases after the move to default to GNU
C23.
For the SME testcases, I decided to add a new one for the GNU C23 case as `()`
changing
to mean `(void)` instead of a non-prototype declaration and add `-std=gnu17` to
the old one.
For pic-*.c `-Wno-old-style-defin
1 - 100 of 138 matches
Mail list logo