[PATCH 1/2] c++: Implement a coroutine language debug dump

This provides to people working on coroutines, as well as writing tests for coroutines, a way to have insight into the results and inputs of the coroutine transformation passes, which is quite essential to understanding what happens in the coroutine transformation. Currently, the information dumpe

[PATCH 0/2] Support for coroutine frames with new-extended alignment

This patch series implements support for coroutines whose frames require alignment. The standard currently does not specify much about this case AFAICT, so we can do this for now (until P2014 progresses). The new dump was useful for testing, and might be useful to coroutine hackers. This patchse

[PATCH] c++: concept in default argument [PR109859]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- 1) We're hitting the assert in cp_parser_placeholder_type_specifier. It says that if it turns out to be false, we should do error() instead. Do so, then. 2) lambda-targ8.C should compile fine, though. The problem was that loca

[PATCH 2/2] c++/coroutines: handle (new-)extended alignment [PR104177]

This patch implements support for frames and promises with new-extended alignment. There are two kinds of alignment to worry about here: - Promise alignment, which causes "internal" padding inside the frame struct. The reason this is a problem is because the (yet to be formalized, but agreed

RE: [PATCH v4 1/4] Match: Add interface match_cond_with_binary_phi for true/false arg

Got, thanks Richard and will have a try in v5. Pan -Original Message- From: Richard Biener Sent: Wednesday, September 18, 2024 8:06 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.

RE: [PATCH v1] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

Thanks Jeff for comments. > Not particularly happy with the wall of expected assembly output, though > it at least tries to be generic in terms of registers and such. Sort of, the asm check for ssadd is quit long up to a point. > So I'll ACK. But > I'd like us to start thinking about what

Re: [PATCH] dwarf2asm: Use constexpr for eh_data_format_name initialization for C++14

On 9/18/24 11:00 AM, Jakub Jelinek wrote: On Wed, Sep 18, 2024 at 10:51:49AM -0600, Jeff Law wrote: On 9/18/24 10:04 AM, Jakub Jelinek wrote: Hi! Similarly to the previous patch, dwarf2asm.cc had HAVE_DESIGNATED_INITIALIZERS support, and as fallback a huge switch. The switch from what I can

Re: [PATCH] SVE intrinsics: Fold svmul with all-zero operands to zero vector

Jennifer Schmitz writes: > From 05e010a4ad5ef8df082b3e03b253aad85e2a270c Mon Sep 17 00:00:00 2001 > From: Jennifer Schmitz > Date: Tue, 17 Sep 2024 00:15:38 -0700 > Subject: [PATCH] SVE intrinsics: Fold svmul with all-zero operands to zero > vector > > As recently implemented for svdiv, this pat

Re: [RFC PATCH] Allow functions with target_clones attribute to be inlined

On Thu, Sep 19, 2024 at 01:01:39AM +0800, Yangyu Chen wrote: > > > > On Sep 18, 2024, at 23:36, Andrew Carlotti wrote: > > > > On Wed, Sep 18, 2024 at 09:46:15AM +0100, Richard Sandiford wrote: > >> Yangyu Chen writes: > >>> I recently found that target_clones functions cannot inline even when

[PATCH] c++: tweak for -Wrange-loop-construct [PR116731]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- This PR reports that the warning would be better off using a check for trivially constructible rather than trivially copyable. LLVM accepted a similar fix: https://github.com/llvm/llvm-project/issues/47355 PR c++/11673

[patch, fortran] Add random numbers and fix some bugs.

This patch adds random number support for UNSIGNED, plus fixes two bugs, with array I/O where the type used to be set to BT_INTEGER, and for division with the divisor being a constant. Again, depends on prevous submissions. OK for trunk? gcc/fortran/ChangeLog: * check.cc (gfc_check_ran

[patch, fortran] Implement IANY, IALL and IPARITY for unsigned

OK for trunk? This is based on the previous submissions. Again, this does not generate a new library version; rather it re-uses the signed integer version already present in the library. OK for trunk? Previous submissions (without which this will not work): https://gcc.gnu.org/pipermail/fortra

[PATCH] s390: Add expander for uaddc/usubc optabs

Bootstrapped and regtested on s390. Both expander are constrained to z196 because of the conditional moves. I guess this is reasonable nowadays. Would be great if you could have a second look that setting the carry/borrow bit (bit 18 of the PSW) is indeed correct. Brain twisted me at first ;-)

Re: [PATCH] ltmain.sh: Fix typos

Hi! Thanks for the patch. Andrew Kreimer writes: > Fix typos in comments. I'm not sure we should further diverge our local libtool copy compared to upstream. Best check whether the same errors exist in upstream libtool ( https://savannah.gnu.org/projects/libtool/ ) and fix them there, I think

[PATCH] libcc1: Fix a typo

Fix a typo in comments. Signed-off-by: Andrew Kreimer --- libcc1/configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcc1/configure b/libcc1/configure index ea689a353c8..d27b9a1f600 100755 --- a/libcc1/configure +++ b/libcc1/configure @@ -17682,7 +17682,7 @@ func_base

Re: [PATCH] libcpp: Add -Wtrailing-blanks warning

On Wed, Sep 18, 2024 at 1:33 PM Jakub Jelinek wrote: > > On Wed, Sep 18, 2024 at 06:17:58PM +0100, Richard Sandiford wrote: > > +1 I'd much rather learn about this kind of error before the code reaches > > a review tool :) > > > > >From a quick check, it doesn't look like Clang has this, so there

RE: [PATCH v2 2/2] aarch64: Improve part-variable vector initialization with SVE INDEX instruction [PR113328]

> > Pengxuan Zheng writes: > > > We can still use SVE's INDEX instruction to construct vectors even > > > if not all elements are constants. For example, { 0, x, 2, 3 } can > > > be constructed by first using "INDEX #0, #1" to generate { 0, 1, 2, > > > 3 }, and then set the elements which are non-

[PATCH] ltmain.sh: Fix typos

Fix typos in comments. Signed-off-by: Andrew Kreimer --- ltmain.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ltmain.sh b/ltmain.sh index 70990740b6c..54f5b964282 100644 --- a/ltmain.sh +++ b/ltmain.sh @@ -177,7 +177,7 @@ basename="s,^.*/,," # to NONDI

Re: [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

> > gcc/ChangeLog: > > > > * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension > > on rv32. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test. > I've pushed this version to the trunk. > > Thanks, > jeff Thanks Jeff and Christoph

Re: [PATCH v2] MATCH: Simplify `a rrotate (32-b) -> a lrotate b` [PR109906]

On 9/18/24 12:45 AM, Eikansh Gupta wrote: The pattern `a rrotate (32-b)` should be optimized to `a lrotate b`. The same is also true for `a lrotate (32-b)`. It can be optimized to `a rrotate b`. This patch adds following patterns: a rrotate (32-b) -> a lrotate b a lrotate (32-b) -> a rrotate

Re: [PATCH] libcpp: Add -Wtrailing-blanks warning

On Wed, Sep 18, 2024 at 06:17:58PM +0100, Richard Sandiford wrote: > +1 I'd much rather learn about this kind of error before the code reaches > a review tool :) > > >From a quick check, it doesn't look like Clang has this, so there is no > existing name to follow. I was considering also -Wtrail

Re: [PATCH] configure: fix typos

On 9/8/24 5:43 AM, Andrew Kreimer wrote: Fix typos in comments. Signed-off-by: Andrew Kreimer --- configure| 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Thanks. I create a suitable ChangeLog and pushed this to the trunk. jeff

Re: [PATCH] jit: Ensure ssize_t is defined.

Thanks, pushed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=fe1ed68000d5e9d41ed48ef1202fd21c8b8c9ff8 FX

Re: [RFC PATCH] Enable vectorization for unknown tripcount in very cheap cost model but disable epilog vectorization.

Richard Biener writes: > On Thu, Sep 12, 2024 at 4:50 PM Hongtao Liu wrote: >> >> On Wed, Sep 11, 2024 at 4:21 PM Hongtao Liu wrote: >> > >> > On Wed, Sep 11, 2024 at 4:04 PM Richard Biener >> > wrote: >> > > >> > > On Wed, Sep 11, 2024 at 4:17 AM liuhongt wrote: >> > > > >> > > > GCC12 enable

Re: [PATCH] testsuite/gcc.dg/pr84877.c: Add machinery to stabilize stack aligmnent

On 9/5/24 9:44 AM, Hans-Peter Nilsson wrote: Tested adding 0..more-than-four environment variables, running cris-sim+cris-elf. I also checked that foo stays the same generated code regardless of the new code: this is not obviously true as foo is "just" noinline, not __noipa__. Ok to commit?

[PATCH v5 2/4] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi

From: Pan Li This patch would like to leverage the match_cond_with_binary_phi to match the phi on cond, and get the true/false arg if matched. This helps a lot to simplify the implementation of gen_phi_on_cond. Before this patch: basic_block _b1 = gimple_bb (_a1); if (gimple_phi_num_args (_a1)

[PATCH v5 4/4] RISC-V: Fix vector SAT_ADD dump check due to middle-end change

From: Pan Li This patch would like fix the dump check times of vector SAT_ADD. The middle-end change makes the match times from 2 to 4 times. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/b

[PATCH v5 1/4] Match: Add interface match_cond_with_binary_phi for true/false arg

From: Pan Li When matching the cond with 2 args phi node, we need to figure out which arg of phi node comes from the true edge of cond block, as well as the false edge. This patch would like to add interface to perform the action and return the true and false arg in TREE type. The below test su

[PATCH v5 3/4] Match: Support form 3 for scalar signed integer .SAT_ADD

From: Pan Li This patch would like to support the form 3 of the scalar signed integer .SAT_ADD. Aka below example: Form 3: #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ T __attribute__((noinline))\ sat_s_add_##T##_fmt_3 (T x, T y)

[PING] [PATCH] contrib: Set check-params-in-docs.py to skip tables of values of a param

Hi, I'd like to ping my patch. You can find it here: https://gcc.gnu.org/pipermail/gcc-patches/2024-August/661362.html Btw not sure if I could Cc anyone on this. AFAIK no one is a maintainer of the ./contrib scripts. Thanks, Filip Kastl

Re: [PATCH][v2] tree-optimization/116573 - .SELECT_VL for SLP

On Tue, 17 Sep 2024, Richard Biener wrote: > The following restores the use of .SELECT_VL for testcases where it > is safe to use even when using SLP. I've for now restricted it > to single-lane SLP plus optimistically allow store-lane nodes > and assume single-lane roots are not widened but at m

[PATCH v2 1/4] Hard register constraints

Implement hard register constraints of the form {regname} where regname must be any valid register name for the target. Such constraints may be used in asm statements as a replacement for register asm and in machine descriptions. Due to optimizations it is not unexpected if two or more inputs req

[PATCH v2 0/4] Hard Register Constraints

This is a follow-up to https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662725.html I basically added only some documentation to the first patch. If you think that gcc/doc/extend.texi isn't the right place (especially the discussion part which will be dropped/rephrased in the end anyway),

Re: [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

On 9/9/24 3:10 AM, Jin Ma wrote: gcc/ChangeLog: * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test. I've pushed this version to the trunk. Thanks, jeff

Re: [PATCH v9 1/2] aarch64: Add AdvSIMD faminmax intrinsics

writes: > The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and > mandatory from Armv9.5-a. It introduces instructions for computing the > floating point absolute maximum and minimum of the two vectors element-wise. > > This patch introduces AdvSIMD faminmax intrinsics. The intrinsics

Re: [PATCH v9 2/2] aarch64: Add codegen support for AdvSIMD faminmax

writes: > The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and > mandatory from Armv9.5-a. It introduces instructions for computing the > floating point absolute maximum and minimum of the two vectors > element-wise. > > This patch adds code generation support for famax and famin in

Re: [PATCH RFC] libstdc++: add #pragma diagnostic

On Thu, 12 Sept 2024 at 21:51, Jason Merrill wrote: > > Tested x86_64-pc-linux-gnu. Thoughts about the remaining warnings discussed > below? Any other comments? > > -- 8< -- > > The use of #pragma GCC system_header in libstdc++ has led to bugs going > undetected for a while due to the silencing

[PATCH v2 3/4] genoutput: Verify hard register constraints

Since genoutput has no information about hard register names we cannot statically verify those names in constraints of the machine description. Therefore, we have to do it at runtime. Although verification shouldn't be too expensive, restrict it to checking builds. This should be sufficient since

Re: [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

On 9/13/24 9:17 PM, Jin Ma wrote: Hi, any more comments about this patch to fix zfa's ICE? Sorry, need to correct the final conclusion in my last message. We should go with the v3 patch, not the v2 patch. jeff

[COMMITED] [PATCH v2] contrib: Set check-params-in-docs.py to skip tables of values of a param

Thanks for the approval Richard! I've incorporated your suggestion to remove the "digits skip" code and I've pushed the patch. Cheers, Filip Kastl -- 8< -- Currently check-params-in-docs.py reports extra params being listed in invoke.texi. However, those aren't actual params but items in a t

Re: [RFC 0/4] Hard Register Constraints

On Wed, Sep 18, 2024 at 03:53:37PM +0200, Michael Matz wrote: > Hello, > > On Thu, 12 Sep 2024, Stefan Schulze Frielinghaus wrote: > > > > > #define call_on_stack(stack, func, asm_call, argconstr...) > > > > \ > > > > {

[PATCH] dwarf2asm: Use constexpr for eh_data_format_name initialization for C++14

Hi! Similarly to the previous patch, dwarf2asm.cc had HAVE_DESIGNATED_INITIALIZERS support, and as fallback a huge switch. The switch from what I can see is expanded as a jump table with 256 label pointers and code at those labels then loads addresses of string literals. The following patch instea

[PATCH] libcpp: Add -Wtrailing-blanks warning

Hi! Trailing blanks is something even git diff diagnoses; while it is a coding style issue, if it is so common that git diff diagnoses it, I think it could be useful to various projects to check that at compile time. Dunno if it should be included in -Wextra, currently it isn't, and due to tons o

Re: [Ping, Fortran, Patch, PR85002, v1] Fix deep-copy of alloc. comps. in coarrays ICEing and crashing w/ lib.

Am 18.09.24 um 12:31 schrieb Andre Vehreschild: Regtested ok on x86_64-pc-linux-gnu / F39. Ok for mainline? OK. Thanks for the patch! Best regards Thomas

[PATCH RFC] build: update bootstrap req to C++14

Tested x86_64-pc-linux-gnu with 5.5.0 bootstrap compiler. Thoughts? -- 8< -- This implements my proposal to update our bootstrap requirement to C++14. The big benefit of the change is the greater constexpr power, but C++14 also added variable templates, generic lambdas, lambda init-capture, bina

Re: [Fortran, Patch, PR106606, v1] Fortran: Break recursion building recursive types. [PR106606]

Hi Andre, Regtested ok on x86_64-pc-linux-gnu / Fedora 39. Ok for mainline? Extremely minor nit: In the commit message and ChangeLog entry, Build a derived type component's type only, when it is not already being build and the component uses pointer semantics. I believe that should be "being

[PATCH] tree-optimization/116585 - SSA corruption with split_constant_offset

split_constant_offset when looking through SSA defs can end up picking SSA leafs that are subject to abnormal coalescing. This can lead to downstream consumers to insert code based on the result (like from dataref analysis) in places that violate constraints for abnormal coalescing. It's best to

[PATCH] i386: Update the comment for mapxf option

Hi, After APX NF, CCMP and NF features supported, the comment for APX option also need update. Ok for trunk? gcc/ChangeLog: * config/i386/i386.opt: Update the features included in apxf. --- gcc/config/i386/i386.opt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/g

Re: [PATCH v3] match: Fix A || B not optimized to true when !B implies A [PR114326]

On Mon, Sep 9, 2024 at 3:11 PM Richard Biener wrote: > > On Thu, Aug 29, 2024 at 9:03 AM wrote: > > > > From: kelefth > > > > In expressions like (a != b || ((a ^ b) & c) == d) and > > (a != b || (a ^ b) == c), (a ^ b) is folded to false. > > In the equivalent expressions (((a ^ b) & c) == d ||

RE: [PATCH] i386: Update the comment for mapxf option

> -Original Message- > From: Kong, Lingling > Sent: Wednesday, September 18, 2024 4:31 PM > To: gcc-patches > Cc: Liu, Hongtao ; Wang, Hongyu > > Subject: [PATCH] i386: Update the comment for mapxf option > > Hi, > > After APX NF, CCMP and NF features supported, the comment for APX

Re: [REPOST, PATCH] PR 89213: Add better support for shifting vectors with 64-bit elements

On Wed, Sep 18, 2024 at 01:51:21AM -0400, Michael Meissner wrote: > On Tue, Sep 17, 2024 at 02:33:09AM -0500, Segher Boessenkool wrote: > > Hi! > > > > On Mon, Sep 16, 2024 at 11:40:45PM -0400, Michael Meissner wrote: > > > With this patch, GCC now realizes that the vector shift instructions will

Re: [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

On 9/17/24 2:57 AM, Xianmiao Qu wrote: The Combine Pass may generate zero_extract instructions that are out of range. Drawing from other architectures like AArch64, we should impose restrictions on the "*th_extu4" pattern. gcc/ * config/riscv/thead.md (*th_extu4): Fix th.extu

Re: [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

On 9/16/24 2:10 AM, Xianmiao Qu wrote: I think it is a typo. When calculating the 'SET_SRC (x)' cost, outer_code should be set to SET. gcc/ * config/riscv/riscv.cc (riscv_rtx_costs): Fix the outer_code when calculating the cost of SET expression. Agreed and pushed. Thanks fo

[PATCH][v2] Fall back to single-lane SLP before falling back to no SLP

The following changes the fallback to disable SLP when any of the discovered SLP instances failed to pass vectorization checking into a fallback that emulates what no SLP would do with SLP - force single-lane discovery for all instances. The patch does not remove the final fallback to disable SLP

Re: [PATCH v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

On 9/18/24 8:03 AM, Christoph Müllner wrote: On Wed, Sep 18, 2024 at 3:55 PM Jeff Law wrote: On 9/10/24 10:09 AM, Christoph Müllner wrote: But if the generated code is just moving bits, why can't we use the standard movXX patterns for the data movement? Clearly there's something about

[PATCH v2 2/4] Error handling for hard register constraints

This implements some basic error handling for hard register constraints including potential conflics with register asm operands. In contrast to register asm operands, hard register constraints allow more than just one register per operand. Even more than just one register per alternative. For ex

[PATCH v2 4/4] Rewrite register asm into hard register constraints

Currently a register asm already materializes during expand. This means, a hard register is allocated for the very first access of a register asm as e.g. in an assignment. As a consequence this might lead to suboptimal register allocation if the assignment and the using asm statement are spread f

Re: [PATCH][PR116569] match.pd: Check trunc_mod vector obtap before folding.

On Wed, 18 Sep 2024, Jennifer Schmitz wrote: > > > > On 6 Sep 2024, at 16:20, Jakub Jelinek wrote: > > > > External email: Use caution opening links or attachments > > > > > > On Fri, Sep 06, 2024 at 02:10:19PM +, Kyrylo Tkachov wrote: > >>> This is certainly wrong. > >>> PROP_gimple_any

Re: [PATCH 2/2] RISC-V: Optimize the cost of the LO_SUM expression.

On 9/16/24 2:11 AM, Xianmiao Qu wrote: Currently, the cost of the LO_SUM expression is based on the cost of calculating the first subexpression. And that's probably the real bug here. THe first subexpression is typically going to be a REG and is not interesting from a costing standpoint. W

Re: [PATCH] contrib: Set check-params-in-docs.py to skip tables of values of a param

Filip Kastl writes: > Hi, > > Here is the part of invoke.texi that currently confuses > check-params-in-docs.py: > > @item aarch64-autovec-preference > Force an ISA selection strategy for auto-vectorization. > @table @samp > @item default > Use the default heuristics. > @item asimd-only > Use only

Re: [RFC 0/4] Hard Register Constraints

Hello, On Thu, 12 Sep 2024, Stefan Schulze Frielinghaus wrote: > > > #define call_on_stack(stack, func, asm_call, argconstr...) \ > > > { \ > > > register void *tos asm("r11");

Re: [PATCH v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

On 9/10/24 10:09 AM, Christoph Müllner wrote: But if the generated code is just moving bits, why can't we use the standard movXX patterns for the data movement? Clearly there's something about this that I'm missing. > This is a special case for rv32 + D, where we have SI, SF and DF, but no

[PATCH v2 1/4] aarch64: store signing key and signing method in DWARF _Unwind_FrameState

This patch is only a refactoring of the existing implementation of PAuth and returned-address signing. The existing behavior is preserved. _Unwind_FrameState already contains several CIE and FDE information (see the attributes below the comment "The information we care about from the CIE/FDE" in l

[PATCH v2 0/4][libgcc] store signing key and signing method in DWARF _Unwind_FrameState

This patch series is only a refactoring of the existing implementation of PAuth and returned-address signing. The existing behavior is preserved. 1. aarch64: store signing key and signing method in DWARF _Unwind_FrameState _Unwind_FrameState already contains several CIE and FDE information (see

[PATCH v2 2/4] aarch64: skip copy of RA state register into target context

The RA state register is local to a frame, so it should not be copied to the target frame during the context installation. This patch adds a new backend handler that check whether a register needs to be skipped or not before its installation. libgcc/ChangeLog: * config/aarch64/aarch64-unwind.

Re: [PATCH] libcpp: Add -Wtrailing-blanks warning

On 9/18/24 10:11 AM, Jakub Jelinek wrote: Hi! Trailing blanks is something even git diff diagnoses; while it is a coding style issue, if it is so common that git diff diagnoses it, I think it could be useful to various projects to check that at compile time. Dunno if it should be included in

Re: [PATCH] dwarf2asm: Use constexpr for eh_data_format_name initialization for C++14

On 9/18/24 10:04 AM, Jakub Jelinek wrote: Hi! Similarly to the previous patch, dwarf2asm.cc had HAVE_DESIGNATED_INITIALIZERS support, and as fallback a huge switch. The switch from what I can see is expanded as a jump table with 256 label pointers and code at those labels then loads addresses

Re: [PATCH RFC] build: update bootstrap req to C++14

1. GNAT needs GCC 5.1 or later 2. Ubuntu 16.04 uses GCC 5.4 3. The propose is bump to GCC 5.5 4. Debian 9 uses GCC 6.3 5. D need GCC 9.4 or later GCC 9.4 is obviously too new, and using GCC 5.5 rules out Ubuntu 16.04. So unless there is a strong reason to do so, it is recommended to bump to GCC 5.

Re: [PATCH RFC] build: update bootstrap req to C++14

Jason Merrill writes: > Tested x86_64-pc-linux-gnu with 5.5.0 bootstrap compiler. Thoughts? > > -- 8< -- > > This implements my proposal to update our bootstrap requirement to C++14. > The big benefit of the change is the greater constexpr power, but C++14 also > added variable templates, generi

Re: [PATCH v2 0/4][libgcc] store signing key and signing method in DWARF _Unwind_FrameState

Matthieu Longo writes: > This patch series is only a refactoring of the existing implementation of > PAuth and returned-address signing. The existing behavior is preserved. The series LGTM, thanks. OK for trunk if there are no objections before Monday. Richard > > 1. aarch64: store signing ke

Re: [PATCH] dwarf2asm: Use constexpr for eh_data_format_name initialization for C++14

On Wed, Sep 18, 2024 at 10:51:49AM -0600, Jeff Law wrote: > On 9/18/24 10:04 AM, Jakub Jelinek wrote: > > Hi! > > > > Similarly to the previous patch, dwarf2asm.cc had > > HAVE_DESIGNATED_INITIALIZERS support, and as fallback a huge switch. > > The switch from what I can see is expanded as a jump

Re: [PATCH v2 0/4] dwarf2: add hooks for architecture-specific CFIs

Matthieu Longo writes: > Architecture-specific CFI directives are currently declared an processed > among others architecture-independent CFI directives in gcc/dwarf2* files. > This approach creates confusion, specifically in the case of DWARF > instructions in the vendor space and using the sa

Re: [PATCH RFC] build: update bootstrap req to C++14

On 9/18/24 6:36 PM, Iain Sandoe wrote: On 18 Sep 2024, at 17:18, Jason Merrill wrote: Tested x86_64-pc-linux-gnu with 5.5.0 bootstrap compiler. Thoughts? Despite that adequate support is available in GCC-5.5/6, would it be useful to jump to a version that allows a single toolchain to boot

Re: [RFC PATCH] Allow functions with target_clones attribute to be inlined

> On Sep 18, 2024, at 23:36, Andrew Carlotti wrote: > > On Wed, Sep 18, 2024 at 09:46:15AM +0100, Richard Sandiford wrote: >> Yangyu Chen writes: >>> I recently found that target_clones functions cannot inline even when >>> the caller has exactly the same target. However, if we only use targe

Re: [PATCH] libcpp: Add -Wtrailing-blanks warning

Jeff Law writes: > On 9/18/24 10:11 AM, Jakub Jelinek wrote: >> Hi! >> >> Trailing blanks is something even git diff diagnoses; while it is a coding >> style issue, if it is so common that git diff diagnoses it, I think it could >> be useful to various projects to check that at compile time. Nic

Re: [RFC PATCH] Allow functions with target_clones attribute to be inlined

Yangyu Chen writes: > I recently found that target_clones functions cannot inline even when > the caller has exactly the same target. However, if we only use target > attributes in C++ and let the compiler generate IFUNC for us, the > functions with the same target will be inlined. > > For example

Re: [RFC PATCH] Allow functions with target_clones attribute to be inlined

On Wed, Sep 18, 2024 at 8:41 PM Andrew Carlotti wrote: > > On Thu, Sep 19, 2024 at 01:01:39AM +0800, Yangyu Chen wrote: > > > > > > > On Sep 18, 2024, at 23:36, Andrew Carlotti > > > wrote: > > > > > > On Wed, Sep 18, 2024 at 09:46:15AM +0100, Richard Sandiford wrote: > > >> Yangyu Chen writes:

Re: [PATCH] i386: Enhance AVX10.2 convert tests

On Wed, Sep 18, 2024 at 1:42 PM Haochen Jiang wrote: > > Hi all, > > For AVX10.2 convert tests, all of them are missing mask tests > previously, this patch will add them in the tests. > > Tested on sde with assembler with these insts. Ok for trunk? Ok. > > Thx, > Haochen > > gcc/testsuite/ChangeLo

Re: [PATCH] i386: Add ssemov2, sseicvt2 for some load instructions that use memory on operand2

On Thu, Sep 19, 2024 at 9:34 AM Hu, Lin1 wrote: > > Hi, all > > The memory attr of some instructions should be 'load', but these is 'none' > currently. > > This patch add two new types ssemov2, sseicvt2 for some load instructions that > use memory on operands. So their memory attr will be 'load'.

Re: [PATCH v5 2/4] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi

On Thu, Sep 19, 2024 at 6:11 AM wrote: > > From: Pan Li > > This patch would like to leverage the match_cond_with_binary_phi to > match the phi on cond, and get the true/false arg if matched. This > helps a lot to simplify the implementation of gen_phi_on_cond. > > Before this patch: > basic_blo

Re: [PATCH v5 3/4] Match: Support form 3 for scalar signed integer .SAT_ADD

On Thu, Sep 19, 2024 at 6:12 AM wrote: > > From: Pan Li > > This patch would like to support the form 3 of the scalar signed > integer .SAT_ADD. Aka below example: > > Form 3: > #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ > T __attribute__((noinline))

[PATCH] Fall back to single-lane SLP before falling back to no SLP

The following changes the fallback to disable SLP when any of the discovered SLP instances failed to pass vectorization checking into a fallback that emulates what no SLP would do with SLP - force single-lane discovery for all instances. The patch does not remove the final fallback to disable SLP

Re: [PATCH v3] match: Fix A || B not optimized to true when !B implies A [PR114326]

On Wed, Sep 18, 2024 at 10:42 AM Konstantinos Eleftheriou wrote: > > On Mon, Sep 9, 2024 at 3:11 PM Richard Biener > wrote: > > > > On Thu, Aug 29, 2024 at 9:03 AM wrote: > > > > > > From: kelefth > > > > > > In expressions like (a != b || ((a ^ b) & c) == d) and > > > (a != b || (a ^ b) == c),

[PATCH v9 1/2] aarch64: Add AdvSIMD faminmax intrinsics

The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and mandatory from Armv9.5-a. It introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch introduces AdvSIMD faminmax intrinsics. The intrinsics of this extensio

[PATCH v9 0/2] Add support for AdvSIMD faminmax

From: Saurabh Jha This is a revised version of this patch series: https://gcc.gnu.org/pipermail/gcc-patches/2024-September/thread.html Thanks for the review comments. They are all addressed in this version. The changes are as follows. 1. [intrinsics patch] Using enum class for aarch64_builtin_si

Re: [Ping*2, Patch, Fortran, 77871, v1] Allow for class typed coarray parameter as dummy [PR77871]

Hi all, back from my holidays and still no review. PING PING! Rebased to current mainline. Regtested ok on x86_64-pc-linux-gnu / F39. Ok for mainline? Regards, Andre On Wed, 21 Aug 2024 13:43:52 +0200 Andre Vehreschild wrote: > Hi all, > > pinging this patch for the first time. > >

Re: [PATCH] jit: Ensure ssize_t is defined.

Can I please get an approval on that one? It’s been there since January, I’ve amended it following review, but cannot get a definite ok. It is five lines. Bootstrapped on x86_64-apple-darwin23. OK to push? FX > Le 7 sept. 2024 à 19:35, FX Coudert a écrit : > > ping**many on this patch, origi

Re: [Ping, Fortran, Patch, PR85002, v1] Fix deep-copy of alloc. comps. in coarrays ICEing and crashing w/ lib.

Hi all, pinging this patch. Regtested ok on x86_64-pc-linux-gnu / F39. Ok for mainline? Regards, Andre On Fri, 23 Aug 2024 11:19:59 +0200 Andre Vehreschild wrote: > Hi all, > > attached patch fixes an ICE during trans-phase when allocatable components in > derived typed coarrays were

[patch,reload] Add target macro RELOAD_ELIMINABLE_REGS (PR116326)

The is patch adds the new target macro RELOAD_ELIMINABLE_REGS that's needed during the reload -> LRA transition because reload and LRA disagree on how ELIMINABLE_REGS should represent multi-register frame pointer eliminations. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116326#c2 As ELIMIN

Re: [PATCH][PR116569] match.pd: Check trunc_mod vector obtap before folding.

> On 6 Sep 2024, at 16:20, Jakub Jelinek wrote: > > External email: Use caution opening links or attachments > > > On Fri, Sep 06, 2024 at 02:10:19PM +, Kyrylo Tkachov wrote: >>> This is certainly wrong. >>> PROP_gimple_any is set already at the end of gimplification, so certainly >>> doe

[PATCH v2 4/4] libgcc: update configure (regenerated by autoreconf)

libgcc/ChangeLog: * configure: Regenerate. --- libgcc/configure | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libgcc/configure b/libgcc/configure index a69d314374a..15a0be23644 100755 --- a/libgcc/configure +++ b/libgcc/configure @@ -587,6 +587,7 @@ ac_includes_default='/* none */

Re: [PATCH v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

On Wed, Sep 18, 2024 at 3:55 PM Jeff Law wrote: > > > > On 9/10/24 10:09 AM, Christoph Müllner wrote: > > >> But if the generated code is just moving bits, why can't we use the > >> standard movXX patterns for the data movement? Clearly there's > >> something about this that I'm missing. > > > Th

[PATCH v2 1/4] Rename REG_CFA_TOGGLE_RA_MANGLE to REG_CFA_NEGATE_RA_STATE

The current name REG_CFA_TOGGLE_RA_MANGLE is not representative of what it really is, i.e. a register to represent several states, not only a binary one. Same for dwarf2out_frame_debug_cfa_toggle_ra_mangle. gcc/ChangeLog: * combine-stack-adj.cc (no_unhandled_cfa): Rename.

[PATCH v2 3/4] libgcc: hide CIE and FDE data for DWARF architecture extensions behind a handler.

This patch provides a new handler MD_ARCH_FRAME_STATE_T to hide an architecture-specific structure containing CIE and FDE data related to DWARF architecture extensions. Hiding the architecture-specific attributes behind a handler has the following benefits: 1. isolating those data from the generic

[PATCH v2 2/4] dwarf2: add hooks for architecture-specific CFIs

Architecture-specific CFI directives are currently declared an processed among others architecture-independent CFI directives in gcc/dwarf2* files. This approach creates confusion, specifically in the case of DWARF instructions in the vendor space and using the same instruction code. Such a clash

[PATCH v2 0/4] dwarf2: add hooks for architecture-specific CFIs

Architecture-specific CFI directives are currently declared an processed among others architecture-independent CFI directives in gcc/dwarf2* files. This approach creates confusion, specifically in the case of DWARF instructions in the vendor space and using the same instruction code. Such a clas

[PATCH v2 3/4] aarch64 testsuite: explain expectections for pr94515* tests

gcc/testsuite/ChangeLog: * g++.target/aarch64/pr94515-1.C: Improve test documentation. * g++.target/aarch64/pr94515-2.C: Same. --- gcc/testsuite/g++.target/aarch64/pr94515-1.C | 8 gcc/testsuite/g++.target/aarch64/pr94515-2.C | 39 +--- 2 files changed, 41 in

[PATCH v2 4/4] dwarf2: store the RA state in CFI row

On AArch64, the RA state informs the unwinder whether the return address is mangled and how, or not. This information is encoded in a boolean in the CFI row. This binary approach prevents from expressing more complex configuration, as it is the case with PAuth_LR introduced in Armv9.5-A. This patc

Re: [PATCH RFC] build: update bootstrap req to C++14

On Wed, Sep 18, 2024 at 6:22 PM Jason Merrill wrote: > > Tested x86_64-pc-linux-gnu with 5.5.0 bootstrap compiler. Thoughts? I'm fine with this in general - do we have needs of bumping the requirement for GCC 15 though? IMO we should bump once we are requiring actual C++14 in some place. As of

Re: [PATCH v5 1/4] Match: Add interface match_cond_with_binary_phi for true/false arg

On Thu, Sep 19, 2024 at 6:11 AM wrote: > > From: Pan Li > > When matching the cond with 2 args phi node, we need to figure out > which arg of phi node comes from the true edge of cond block, as > well as the false edge. This patch would like to add interface > to perform the action and return th

  1   2   >