Re: [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

[Jeff Law]

On 9/17/24 2:57 AM, Xianmiao Qu wrote:
The Combine Pass may generate zero_extract instructions that are out of range.
Drawing from other architectures like AArch64, we should impose restrictions
on the "*th_extu<mode>4" pattern.

gcc/
        * config/riscv/thead.md (*th_extu<mode>4): Fix th.extu
        operands exceeding range on rv32.
        * testsuite/gcc.target/riscv/xtheadbb-extu-4.c: New.
Thanks.  I fixed a nit in the ChangeLog (testsuite has its own 
ChangeLog) and pushed this to the trunk.

jeff