Re: New version of unsiged patch

Ping (a little bit)? With another weekend coming up, I would have some time to work on incorporating any feedback, or on putting in more intrinsics. Best regards Thomas

[PATCH] c++: Handle attributes on exception declarations [PR110345]

Hi! This is a continuation of the series for the ignorability of standard attributes, on top of https://gcc.gnu.org/pipermail/gcc-patches/2024-August/661904.html https://gcc.gnu.o

[PATCH] c++: Add carries_dependency further test coverage [PR110345]

Hi! This patch adds additional test coverage for the carries_dependency attribute (unlike other attributes, the attribute actually isn't implemented for real, so we warn even in the cases of valid uses because we ignore those as well). Bootstrapped/regtested on x86_64-linux and i686-linux, ok for

Re: [PATCH] RISC-V: Handle unused-only-live stmts in SLP discovery

On Wed, 4 Sep 2024, Palmer Dabbelt wrote: > On Wed, 04 Sep 2024 04:10:52 PDT (-0700), rguent...@suse.de wrote: > > The following adds SLP discovery for roots that are only live but > > otherwise unused. These are usually inductions. This allows a > > few more testcases to be handled fully with S

[PATCH] c++: Add fallthrough attribute further test coverage [PR110345]

Hi! Similarly for fallthrough attribute. Had to add a second testcase because the diagnostics for fallthrough not used within switch at all is done during expansion and expansion won't happen if there are other errors in the testcase. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for

[PATCH] c++: Add {,un}likely attribute further test coverage [PR110345]

Hi! Similarly for likely/unlikely attributes. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2024-09-05 Jakub Jelinek PR c++/110345 * g++.dg/cpp0x/attr-likely1.C: New test. * g++.dg/cpp0x/attr-unlikely1.C: New test. --- gcc/testsuite/g++.dg/cpp0

Re: [PATCH] fab: Cleanup eh after optimize_memcpy [PR116601]

On Thu, Sep 5, 2024 at 8:25 AM Andrew Pinski wrote: > > When optimize_memcpy was added in r7-5443-g7b45d0dfeb5f85, > a path was added such that a statement was turned into a non-throwing > statement and maybe_clean_or_replace_eh_stmt/gimple_purge_dead_eh_edges > would not be called for that statem

[PATCH] c++: Fix up maybe_unused attribute handling [PR110345]

Hi! When adding test coverage for maybe_unused attribute, I've run into several things: 1) similarly to deprecated attribute, the attribute shouldn't pedantically appertain to types other than class/enumeration definitions 2) similarly to deprecated attribute, the attribute shouldn't pedantical

[PATCH] RISC-V: Lookup reversely in riscv_select_multilib_by_abi

From: YunQiang Su When use --print-multilib-os-dir, gcc outputs different value with full -march option and the base one only. $ ./gcc/xgcc --print-multilib-os-dir -mabi=lp64d -march=rv64gc lib64/lp64d $ ./gcc/xgcc --print-multilib-os-dir -mabi=lp64d -march=rv64gc_zba . The reason is that in m

[PATCH] vrp: Fix up diagnostics wording

Hi! I've noticed non-standard wording of this diagnostics when looking at a miscompilation with --param=vrp-block-limit=0. Diagnostics generally shouldn't start with uppercase letter (unless the upper case would appear also in the middle of a sentence) and shouldn't be separate sentences with dot

Re: [PATCH] vrp: Fix up diagnostics wording

Ok On Thu, Sep 5, 2024, 09:30 Jakub Jelinek wrote: > Hi! > > I've noticed non-standard wording of this diagnostics when looking at > a miscompilation with --param=vrp-block-limit=0. > > Diagnostics generally shouldn't start with uppercase letter (unless > the upper case would appear also in the

[COMMITTED 1/6] ada: Tweak assertions in Inline.Cannot_Inline

From: Ronan Desplanques The purpose of this patch is to silence a GNATSAS report. gcc/ada/ * inline.adb (Cannot_Inline): Remove assertion. * inline.ads (Cannot_Inline): Add precondition. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/inline.adb | 2 -- gcc/ad

[COMMITTED 5/6] ada: Streamline handling of low-level peculiarities of record field layout

From: Eric Botcazou This factors out the interface to the low-level field layout machinery. gcc/ada/ * gcc-interface/gigi.h (default_field_alignment): New function. * gcc-interface/misc.cc: Include tm_p header file. (default_field_alignment): New function. * gcc-

[COMMITTED 2/6] ada: Binder respects Ada version for checksum of runtime files

From: Jose Ruiz The parsing to compute the checksums of runtime files (within the binder) was done using the default Ada version (Ada 2012 currently), while the creation of the checksum, when the runtime files are compiled, is performed in a more recent Ada version (Ada 2022 currently). This chan

[COMMITTED 4/6] ada: Remove unused parameters in validity checking routine

From: Piotr Trojanek Code cleanup; semantics is unaffected. gcc/ada/ * exp_util.ads, exp_util.adb (Duplicate_Subexpr_No_Checks): Remove parameters, which are no longer used. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/exp_util.adb | 18 ++

[COMMITTED 6/6] ada: Add bypass for internal fields on strict-alignment platforms

From: Eric Botcazou This is required to support misalignment of tagged types in legacy code. gcc/ada/ * gcc-interface/trans.cc (addressable_p) : Add bypass for internal fields on strict-alignment platforms. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/gcc-i

Re: [PATCH] Vect: use a small step to calculate induction for the unrolled loop (PR tree-optimization/110449)

On Thu, Jul 6, 2023 at 7:50 PM Richard Sandiford wrote: > > Richard Biener via Gcc-patches writes: > > On Wed, Jul 5, 2023 at 8:44 AM Hao Liu OS via Gcc-patches > > wrote: > >> > >> Hi, > >> > >> If a loop is unrolled by n times during vectoriation, two steps are used to > >> calculate the induc

Re: [PATCH] RISC-V: Lookup reversely in riscv_select_multilib_by_abi

LGTM, thanks for catching this, but commit log seems not right? should it be -print-multi-directory or -print-multi-os-directory rather than --print-multilib-os-dir? (I guess should be -print-multi-directory per your output) Anyway, you can go ahead and push that after the fix:) On Thu, Sep 5, 2

[PATCH] testsuite: Fix xorsign.c, vect-double-2.c fails with -march=x86-64-v2

Hi, all These testcases raise fails with -march=x86-64-v2, so add -mno-sse4 to avoid these unexpected fails. Bootstrap and regtest running on x86-64-linux-gnu, pushed as obvious. BRs, Lin gcc/testsuite/ChangeLog: PR testsuite/116608 * gcc.target/i386/vect-double-2.c: Add extra

Re: [PATCH] RISC-V: Lookup reversely in riscv_select_multilib_by_abi

Kito Cheng 于2024年9月5日周四 16:36写道： > > LGTM, thanks for catching this, but commit log seems not right? > should it be -print-multi-directory or -print-multi-os-directory > rather than --print-multilib-os-dir? Yes. It is a typo. I used `--print-multilib-os-dir`, and yes, as you said, `-print-multi-d

[PATCH] tree-optimization/116609 - SLP live lane vectorization with partial vectors

The following implements the simple case of single-lane SLP when using partial vectors which can use the VEC_EXTRACT_LAST code generation without changes. I'll keep the PR open for further enhancements. This avoids FAILs of gcc.target/aarch64/sve/live_1.c when using single-lane SLP for non-groupe

[PATCH] x86: Refine V4BF/V2BF FMA testcase

Simple testcase fix, ok for trunk? This patch removes specific register checks to account for possible register spills and disables tests in 32-bit mode. This adjustment is necessary because V4BF operations in 32-bit mode require duplicating instructions, which lead to unintended test failures. It

[patch][v2] Fortran: Add OpenMP 'interop' directive parsing support

Now also supports the following (note the variable name): 'init(targetsync, target)' – and I fixed an ICE when the variable parsing failed. Comments before I commit it? Tobias Tobias Burnus wrote: This patch adds Fortran parsing support for OpenMP's 'interop' directive (which stops with a 's

[PATCH] tree-optimization/116610 - wrong SLP induction bias for mask peeling

The following fixes a mistake when applying the bias for peeling via masking to the inital value of SLP inductions. This resolves gcc.target/aarch64/sve/peel_ind_1.c (a scan-assembler only unfortunately) when forcing single-lane SLP for it. Bootstrap and regtest running on x86_64-unknown-linux-gn

[PATCH] [AARCH64] adjust gcc.target/aarch64/sve/mask_gather_load_7.c

The following adjusts the scan-assembler to also allow predicate registers p8-15 to be used for the destination of the compares. I see that code generation with a pending vectorizer patch (the only assembler change is different predicate register allocation). Tested on aarch64. OK for trunk? Tha

Re: [PATCH][testsuite]: remove -fwrapv from signbit-5.c

On 2024-09-05 01:02, Jeff Law wrote: On 9/4/24 1:13 AM, Torbjorn SVENSSON wrote: On 2024-09-03 20:23, Richard Biener wrote: Am 03.09.2024 um 19:00 schrieb Tamar Christina : Hi All, The meaning of the testcase was changed by passing it -fwrapv.  The reason for the test failures on

[PATCH] libsanitizer: On aarch64 use hint #34 in prologue of libsanitizer functions

Hi! When gcc is built with -mbranch-protection=standard, running sanitized programs doesn't work properly on bti enabled kernels. This has been fixed upstream with https://github.com/llvm/llvm-project/pull/84061 The following patch cherry picks that from upstream, ok for trunk/14.3? For trunk w

Re: [PATCH] libsanitizer: On aarch64 use hint #34 in prologue of libsanitizer functions

Jakub Jelinek writes: > Hi! > > When gcc is built with -mbranch-protection=standard, running sanitized > programs doesn't work properly on bti enabled kernels. > > This has been fixed upstream with > https://github.com/llvm/llvm-project/pull/84061 > > The following patch cherry picks that from ups

[PATCH V4 04/10] arm: Fix arm backend-use of (u|s|us)dot_prod patterns

Changes from previous revision: As was done for the equivalent aarch64 patch, we rework this patch to do away with mission creep, keeping changes as simple as possible. We thus remove the `gimple_fold_builtin' changes that would have replaced the dot-product builtin calls with DOT_PROD_EXPRs a

Re: [PATCH] c++: Fix overeager Woverloaded-virtual with conversion operators [PR109918]

Hi Jason, On 4 Sep 2024, at 18:09, Jason Merrill wrote: > On 9/1/24 2:51 PM, Simon Martin wrote: >> Hi Jason, >> >> On 26 Aug 2024, at 19:23, Jason Merrill wrote: >> >>> On 8/25/24 12:37 PM, Simon Martin wrote: On 24 Aug 2024, at 23:59, Simon Martin wrote: > On 24 Aug 2024, at 15:13, Jas

[PATCH V4 10/10] autovectorizer: Test autovectorization of different dot-prod modes.

Changes from previous revision: Rename new `check_effective_target' and tests to make their intent clearer. * lib/target-supports.exp: For new `check_effective_target', s/vect_dotprod_twoway/vect_dotprod_hisi/. * One test is renamed to `vect-dotprod-conv-optab.c' to emphasize aim of c

Re: [PATCH] [AARCH64] adjust gcc.target/aarch64/sve/mask_gather_load_7.c

Richard Biener writes: > The following adjusts the scan-assembler to also allow predicate > registers p8-15 to be used for the destination of the compares. > I see that code generation with a pending vectorizer patch (the > only assembler change is different predicate register allocation). Oops,

[PATCH v1 1/9] Support weak references

Monday, September 2, 2024 Richard Sandiford wrote: > On patch 1, do you have a reference for how AArch64 and x86 handle weak > references for MinGW?  The code looks good, but I didn't really follow > why it was doing what it was doing. Monday, September 2, 2024 Martin Storsjö >> The patch adds

Re: PING: [PATCH] ipa: Don't disable function parameter analysis for fat LTO streaming

On Tue, Sep 3, 2024 at 4:00 AM Jan Hubicka wrote: > > > > > > > > > PR ipa/116410 > > > > * ipa-modref.cc (analyze_parms): Always analyze function > > > > parameter > > > > for LTO streaming. > > > > > > > > Signed-off-by: H.J. Lu > > > > --- > > > > gcc/ipa-modref.cc |

[PATCH v1 5/9] aarch64: Multiple adjustments to support the SMALL code model correctly

Monday, September 2, 2024 Richard Sandiford wrote: > I realise this is pre-existing, bue the last line should probably be: > > fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", (ROUNDED))) > > to avoid silent truncation. (Even if the format only supports 32-bit > code and data, it's bett

Re: [PATCH v1 1/9] Support weak references

On Thu, 5 Sep 2024, Evgeny Karpov wrote: Monday, September 2, 2024 Martin Storsjö The patch adds support for weak references. The original MinGW implementation targets ix86, which handles weak symbols differently compared to AArch64. Please clarify this statement. Here is an explanation of

[PATCH v1 0/9] SMALL code model fixes, optimization fixes, LTO and minimal C++ enablement

Monday, September 2, 2024 Richard Sandiford wrote: > Thanks for submitting this. I've responded with minor comments to > some individual patches, but the rest (1, 2, 7, and 8) look good to > me as-is. Thank you for the review. The patch series v2 will be submitted after the validation. Regards

[PATCH] RISC-V: Fix out of index in riscv_select_multilib_by_abi

commit b5c2aae48723c9098a8a3dab1409b30fd87bbf56 Author: YunQiang Su Date: Thu Sep 5 15:14:43 2024 +0800 RISC-V: Lookup reversely in riscv_select_multilib_by_abi The last element should use index multilib_infos.size () - 1 gcc * common/config/riscv/riscv-common.cc(riscv_select_m

[PATCH v2 1/2] Genmatch: Support control flow graph case 1 for phi on condition

From: Pan Li The gen_phi_on_cond can only support below control flow for cond from day 1. Aka: +--+ | def | | ... | +-+ | cond |-->| def | +--+ | ... | | +-+ | | v | +-+ | | PHI |<--+ +-+ U

[PATCH v2 2/2] Match: Support form 3 for scalar signed integer .SAT_ADD

From: Pan Li This patch would like to support the form 3 of the scalar signed integer .SAT_ADD. Aka below example: Form 3: #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ T __attribute__((noinline))\ sat_s_add_##T##_fmt_3 (T x, T y)

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: > On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: > ... > > + bool bit31 = (hival & 0x8000) != 0; > > + int trailing_shift = ctz_hwi (loval) - ctz_hwi (hival); > > + int leading_shift = clz_hwi (loval) - clz_hwi (hival); > > +

Re: [PATCH 3/3] RISC-V: Constant synthesis of inverted halves

On Wed, Sep 4, 2024 at 8:35 PM Jeff Law wrote: > On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: >... > > +unsigned long foo_0x4afe605fb5019fa0(void) { return 0x4afe605fb5019fa0UL; } > > +unsigned long foo_0x07a80d21f857f2de(void) { return 0x07a80d21f857f2deUL; } > > +unsigned long foo_0x6699f19c

Zen5 tuning part 5: update instruction latencies in x86-tune-costs

Hi, there is nothing exciting in this patch. I measured latencies and also compared them with newly released optimization guide and it seems that only important change is that addss is fastr now. It can be 2 cycles instaead of 3 in some cases when the input parameter is computed by another additio

Move from 'gcc.target/nvptx/nvptx.exp' into 'target-supports.exp' additions for nvptx target (was: [PATCH] Make 'target-supports.exp' additions for nvptx target generally available)

Hi! On 2024-07-18T13:44:37+0200, wrote: > OK to push (once testing completes) the attached > "Make 'target-supports.exp' additions for nvptx target generally available"? > > The idea of this new scheme is that explicit feature/target-specific > stuff isn't kept in 'gcc/testsuite/lib/target-suppor

Fix 'gcc.target/nvptx/alias-2.c' comment (was: [committed][nvptx] Use .alias directive for mptx >= 6.3)

Hi! On 2022-03-22T14:41:46+0100, Tom de Vries via Gcc-patches wrote: > --- /dev/null > +++ b/gcc/testsuite/gcc.target/nvptx/alias-1.c > @@ -0,0 +1,27 @@ > +[...] > +int v; > + > +void __f () > +{ > + v = 1; > +} > + > +void f () __attribute__ ((alias ("__f"))); > + > +int > +main (void) > +{ >

Re: [committed][nvptx] Use .alias directive for mptx >= 6.3

Hi! On 2022-03-22T14:41:46+0100, Tom de Vries via Gcc-patches wrote: > Starting with ptx isa version 6.3, a ptx directive .alias is available. > Use this directive to support symbol aliases, as far as possible. > The alias support has the following [and more] limitations. > Aliases to aliases

Enhance 'gcc.target/nvptx/alias-*.c' assembler scanning (was: [committed][nvptx] Use .alias directive for mptx >= 6.3)

Hi! On 2024-09-05T14:36:54+0200, I wrote: > On 2022-03-22T14:41:46+0100, Tom de Vries via Gcc-patches > wrote: >> [nvptx] Use .alias directive for mptx >= 6.3 > >> --- a/gcc/config/nvptx/nvptx.cc >> +++ b/gcc/config/nvptx/nvptx.cc > >> @@ -968,7 +969,8 @@ static void >> write_fn_proto_1 (std::s

Add 'g++.target/nvptx/alias-g++.dg_init_dtor2-1.C' (was: Enhance 'gcc.target/nvptx/alias-*.c' assembler scanning (was: [committed][nvptx] Use .alias directive for mptx >= 6.3))

Hi! On 2024-09-05T14:39:46+0200, I wrote: > On 2024-09-05T14:36:54+0200, I wrote: >> On 2022-03-22T14:41:46+0100, Tom de Vries via Gcc-patches >> wrote: >>> [nvptx] Use .alias directive for mptx >= 6.3 >> >>> --- a/gcc/config/nvptx/nvptx.cc >>> +++ b/gcc/config/nvptx/nvptx.cc >> >>> @@ -968,7 +9

nvptx: Emit DECL and DEF linker markers for aliases [PR104957] (was: Add 'g++.target/nvptx/alias-g++.dg_init_dtor2-1.C' (was: Enhance 'gcc.target/nvptx/alias-*.c' assembler scanning (was: [committed][

Hi! On 2024-09-05T14:42:00+0200, I wrote: > On 2024-09-05T14:39:46+0200, I wrote: >> On 2024-09-05T14:36:54+0200, I wrote: >>> On 2022-03-22T14:41:46+0100, Tom de Vries via Gcc-patches >>> wrote: [nvptx] Use .alias directive for mptx >= 6.3 >>> --- a/gcc/config/nvptx/nvptx.cc +++

c++: Add nodiscard attribute further test coverage [PR110345]

Hi! Fairly non-problematic attribute, again on top of the whole series. Tested on x86_64-linux, ok for trunk? 2024-09-05 Jakub Jelinek PR c++/110345 * g++.dg/cpp0x/attr-nodiscard1.C: New test. --- gcc/testsuite/g++.dg/cpp0x/attr-nodiscard1.C.jj 2024-09-05 13:11:26.91404

c++: Add noreturn attribute further test coverage [PR110345]

Hi! Another non-problematic attribute. Tested on x86_64-linux and i686-linux, ok for trunk? 2024-09-05 Jakub Jelinek PR c++/110345 * g++.dg/cpp0x/attr-noreturn1.C: New test. --- gcc/testsuite/g++.dg/cpp0x/attr-noreturn1.C.jj 2024-09-05 13:45:58.193567109 +0200 +++ gcc/

c++: Add no_unique_address attribute further test coverage [PR110345]

Hi! Another non-problematic attribute. Tested on x86_64-linux and i686-linux, ok for trunk? 2024-09-05 Jakub Jelinek PR c++/110345 * g++.dg/cpp0x/attr-no_unique_address1.C: New test. --- gcc/testsuite/g++.dg/cpp0x/attr-no_unique_address1.C.jj 2024-09-05 14:01:00.3968869

[RFC PATCH] c++: Add alignas further test coverage [PR110345]

Hi! I've tried to do the same thing I did for normal standard attributes also for alignas, but there are way too many cases which are silently accepted although my reading of: "An alignment-specifier may be applied to a variable or to a class data member, but it shall not be applied to a bit-fiel

RE: [gimplify.cc] Avoid ICE when passing VLA vector to accelerator

> -Original Message- > From: Richard Biener > Sent: Tuesday, September 3, 2024 2:09 PM > To: Prathamesh Kulkarni > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [gimplify.cc] Avoid ICE when passing VLA vector to > accelerator > > External email: Use caution opening links or attachments >

[PATCH 1/3] tree-optimization/116609 - SLP live lane vectorization with partial vectors

The following implements the simple case of single-lane SLP when using partial vectors which can use the VEC_EXTRACT_LAST code generation without changes. I'll keep the PR open for further enhancements. This avoids FAILs of gcc.target/aarch64/sve/live_1.c when using single-lane SLP for non-groupe

[PATCH 3/3] Handle non-grouped stores as single-lane SLP

The following enables single-lane loop SLP discovery for non-grouped stores and adjusts vectorizable_store to properly handle those. For gfortran.dg/vect/vect-8.f90 we vectorize one additional loop, not running into the "not falling back to strided accesses" bail-out. I have not investigated in de

[PATCH 2/3] tree-optimization/116610 - wrong SLP induction bias for mask peeling

The following fixes a mistake when applying the bias for peeling via masking to the inital value of SLP inductions. This resolves gcc.target/aarch64/sve/peel_ind_1.c (a scan-assembler only unfortunately) when forcing single-lane SLP for it. PR tree-optimization/116610 * tree-vect-

Re: PING: [PATCH] ipa: Don't disable function parameter analysis for fat LTO streaming

> On Tue, Sep 3, 2024 at 4:00 AM Jan Hubicka wrote: > > > > > > > > > > > > PR ipa/116410 > > > > > * ipa-modref.cc (analyze_parms): Always analyze function > > > > > parameter > > > > > for LTO streaming. > > > > > > > > > > Signed-off-by: H.J. Lu > > > > > --- > > > > >

[RISCV] target-specific source placement

Hi, looking at the RISCV code, it seems that there are several vendor-specific files in config/riscv. For instance sifive-7.md and xiangshan.md. It seems these are unconditionally included for all riscv targets. I guess then one doesn't end up with some combinatorial explosion of possible risc

Re: [PATCH v2] c++: fn redecl in fn scope wrongly accepted [PR116239]

On 9/4/24 1:18 PM, Marek Polacek wrote: On Wed, Sep 04, 2024 at 12:28:49PM -0400, Jason Merrill wrote: + if (!validate_constexpr_redeclaration (alias, decl)) +return; + retrofit_lang_decl (decl); DECL_LOCAL_DECL_ALIAS (decl) = alias; } I don't think we need this in the case

Re: [PATCH] c++, v3: Partially implement CWG 2867 - Order of initialization for structured bindings [PR115769]

On 9/4/24 2:03 PM, Jakub Jelinek wrote: On Wed, Sep 04, 2024 at 01:22:47PM -0400, Jason Merrill wrote: @@ -8985,6 +9003,13 @@ cp_finish_decl (tree decl, tree init, bo if (var_definition_p) abstract_virtuals_error (decl, type); + if (decomp && !processing_template_decl) +

[PATCH] c++: template depth of lambda in default targ [PR116567]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/14? -- >8 -- A lambda within a default template argument used in some template-id may have a smaller template depth than the context of the template-id. For example, the lambda in v1's default template argument has tem

Re: [PATCH] c++: template depth of lambda in default targ [PR116567]

On Thu, 5 Sep 2024, Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK > for trunk/14? > > -- >8 -- > > A lambda within a default template argument used in some template-id > may have a smaller template depth than the context of the template-id. > For exa

[PATCH] c++: Fix mangling of otherwise unattached class-scope lambdas [PR116568]

Bootstrapped and regtested (so far just dg.exp) on x86_64-pc-linux-gnu, OK for trunk if full regtest passes? Or would it be better to try to implement all the rules mentioned in the linked pull request for one commit; I admit I haven't looked very closely yet at how else we diverge? -- >8 -- Thi

Re: [PATCH] RISC-V: Optimize branches with shifted immediate operands

> It's worth noting there is a newer way which is usually slightly simpler > than a match_operator. Specifically code iterators. Thank you for the very detailed feedback. It is not a problem to add code iterators. I would add iterators for "eq" and "ne" in riscv/iterators.md since they don't cur

[PATCH v3] c++: fn redecl in fn scope wrongly accepted [PR116239]

On Thu, Sep 05, 2024 at 10:42:22AM -0400, Jason Merrill wrote: > On 9/4/24 1:18 PM, Marek Polacek wrote: > > On Wed, Sep 04, 2024 at 12:28:49PM -0400, Jason Merrill wrote: > > > > > + if (!validate_constexpr_redeclaration (alias, decl)) > > > > +return; > > > > + > > > > retrofit_lang_de

[PATCH] c++, v4: Partially implement CWG 2867 - Order of initialization for structured bindings [PR115769]

On Thu, Sep 05, 2024 at 10:51:47AM -0400, Jason Merrill wrote: > > @@ -8993,6 +9010,11 @@ cp_finish_decl (tree decl, tree init, bo > > if (var_definition_p) > > abstract_virtuals_error (decl, type); > > + if (decomp > > + && !processing_template_decl > > + && !cp_finish_dec

Re: [RFC PATCH] c++: Add alignas further test coverage [PR110345]

On 9/5/24 9:03 AM, Jakub Jelinek wrote: Hi! I've tried to do the same thing I did for normal standard attributes also for alignas, but there are way too many cases which are silently accepted although my reading of: "An alignment-specifier may be applied to a variable or to a class data member,

Re: [PATCH v3] c++: fn redecl in fn scope wrongly accepted [PR116239]

On 9/5/24 11:10 AM, Marek Polacek wrote: On Thu, Sep 05, 2024 at 10:42:22AM -0400, Jason Merrill wrote: On 9/4/24 1:18 PM, Marek Polacek wrote: On Wed, Sep 04, 2024 at 12:28:49PM -0400, Jason Merrill wrote: + if (!validate_constexpr_redeclaration (alias, decl)) +return; + retrofit

Re: [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

On Wed, 04 Sep 2024 15:20:45 PDT (-0700), jeffreya...@gmail.com wrote: On 9/4/24 4:07 PM, Palmer Dabbelt wrote: These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires

Re: [PATCH] c++, v4: Partially implement CWG 2867 - Order of initialization for structured bindings [PR115769]

On 9/5/24 11:14 AM, Jakub Jelinek wrote: On Thu, Sep 05, 2024 at 10:51:47AM -0400, Jason Merrill wrote: @@ -8993,6 +9010,11 @@ cp_finish_decl (tree decl, tree init, bo if (var_definition_p) abstract_virtuals_error (decl, type); + if (decomp + && !processing_template

[PATCH] testsuite/gcc.dg/pr84877.c: Add machinery to stabilize stack aligmnent

Tested adding 0..more-than-four environment variables, running cris-sim+cris-elf. I also checked that foo stays the same generated code regardless of the new code: this is not obviously true as foo is "just" noinline, not __noipa__. Ok to commit? -- >8 -- This test awkwardly "blinks"; xfails and

[PATCH] arm: avoid indirect sibcalls when IP is live [PR116597]

On Arm only r0-r3 (the argument registers) and IP are available for use as an address for an indirect sibcall. But if all the argument registers are used and IP is clobbered during the epilogue, or is used to pass closure information, then there is no spare register to hold the address and we must

Re: [PATCH] c++: template depth of lambda in default targ [PR116567]

On 9/5/24 10:54 AM, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/14? -- >8 -- A lambda within a default template argument used in some template-id may have a smaller template depth than the context of the template-id. For example, the lambd

Re: [PATCH] c++: Fix overeager Woverloaded-virtual with conversion operators [PR109918]

On 9/5/24 7:02 AM, Simon Martin wrote: Hi Jason, On 4 Sep 2024, at 18:09, Jason Merrill wrote: On 9/1/24 2:51 PM, Simon Martin wrote: Hi Jason, On 26 Aug 2024, at 19:23, Jason Merrill wrote: On 8/25/24 12:37 PM, Simon Martin wrote: On 24 Aug 2024, at 23:59, Simon Martin wrote: On 24 Aug

Re: [PATCH 6/8] gcn: Add else operand to masked loads.

(Sorry, I missed this because I was on vacation.) On 11/08/2024 22:00, Robin Dapp wrote: This patch adds a zero else operand to the masked loads. The patch is OK, but I have a question below. gcc/ChangeLog: * config/gcn/predicates.md (maskload_else_operand): New predicate.

[pushed] doc: remove stray character

Applying to trunk as obvious. -- >8 -- There's an extra '+'. gcc/ChangeLog: * doc/invoke.texi: Remove an extra char in @item sme2. --- gcc/doc/invoke.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 193db761d64..0f9

Re: [PATCH] c++: template depth of lambda in default targ [PR116567]

On Thu, 5 Sep 2024, Jason Merrill wrote: > On 9/5/24 10:54 AM, Patrick Palka wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK > > for trunk/14? > > > > -- >8 -- > > > > A lambda within a default template argument used in some template-id > > may have a smaller temp

Re: [RISCV] target-specific source placement

On 9/5/24 8:27 AM, Nathan Sidwell wrote: Hi, looking at the RISCV code, it seems that there are several vendor- specific files in config/riscv.  For instance sifive-7.md and xiangshan.md. It seems these are unconditionally included for all riscv targets. I guess then one doesn't end up with

Re: [RISCV] target-specific source placement

On Thu, 05 Sep 2024 07:27:57 PDT (-0700), nat...@acm.org wrote: Hi, looking at the RISCV code, it seems that there are several vendor-specific files in config/riscv. For instance sifive-7.md and xiangshan.md. It seems these are unconditionally included for all riscv targets. I guess then one doe

Re: [RISCV] target-specific source placement

[Sorry I crossed the streams here, I had to run out in the middle of writing up that other reply.] On Thu, 05 Sep 2024 10:49:47 PDT (-0700), jeffreya...@gmail.com wrote: On 9/5/24 8:27 AM, Nathan Sidwell wrote: Hi, looking at the RISCV code, it seems that there are several vendor- specific f

[to-be-committed][V2][RISC-V] Avoid unnecessary extensions after sCC insns

So the first patch failed the pre-commit CI; it didn't fail in my testing because I'm using --with-arch to set a default configuration that includes things like zicond to ensure that's always tested. And the failing test is skipped when zicond is enabled by default. The failing test is desi

Re: [PATCH] c++: template depth of lambda in default targ [PR116567]

On 9/5/24 1:26 PM, Patrick Palka wrote: On Thu, 5 Sep 2024, Jason Merrill wrote: On 9/5/24 10:54 AM, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/14? -- >8 -- A lambda within a default template argument used in some template-id may have

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On 9/5/24 6:16 AM, Raphael Zinsly wrote: On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: ... + bool bit31 = (hival & 0x8000) != 0; + int trailing_shift = ctz_hwi (loval) - ctz_hwi (hival); + int leading_shift = clz_hwi (lova

[PATCH] c++: vtable referring to "unavailable" virtual fn [PR116606]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- mark_vtable_entries already has /* It's OK for the vtable to refer to deprecated virtual functions. */ warning_sentinel w(warn_deprecated_decl); but that doesn't cover __attribute__((unavailable)). We can use the follo

Re: [PATCH] c++: template depth of lambda in default targ [PR116567]

On Thu, 5 Sep 2024, Jason Merrill wrote: > On 9/5/24 1:26 PM, Patrick Palka wrote: > > On Thu, 5 Sep 2024, Jason Merrill wrote: > > > > > On 9/5/24 10:54 AM, Patrick Palka wrote: > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK > > > > for trunk/14? > > > > > > > > --

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On Thu, Sep 5, 2024 at 3:10 PM Jeff Law wrote: > On 9/5/24 6:16 AM, Raphael Zinsly wrote: > > On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: > >> On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: > >> ... > >>> + bool bit31 = (hival & 0x8000) != 0; > >>> + int trailing_shift = ctz_hw

Re: [PATCH 3/3] RISC-V: Constant synthesis of inverted halves

On 9/5/24 6:18 AM, Raphael Zinsly wrote: On Wed, Sep 4, 2024 at 8:35 PM Jeff Law wrote: On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: ... +unsigned long foo_0x4afe605fb5019fa0(void) { return 0x4afe605fb5019fa0UL; } +unsigned long foo_0x07a80d21f857f2de(void) { return 0x07a80d21f857f2deUL

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On 9/5/24 12:38 PM, Raphael Zinsly wrote: On Thu, Sep 5, 2024 at 3:10 PM Jeff Law wrote: On 9/5/24 6:16 AM, Raphael Zinsly wrote: On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: ... + bool bit31 = (hival & 0x8000) != 0; + int

Re: [to-be-committed][V2][RISC-V] Avoid unnecessary extensions after sCC insns

On Thu, 05 Sep 2024 11:03:18 PDT (-0700), jeffreya...@gmail.com wrote: So the first patch failed the pre-commit CI; it didn't fail in my testing because I'm using --with-arch to set a default configuration that includes things like zicond to ensure that's always tested. And the failing test is

[PATCH] RISC-V: Define LOGICAL_OP_NON_SHORT_CIRCUIT to 1 [PR116615]

We have cheap logical ops, so let's just move this back to the default to take advantage of the standard branch/op hueristics. gcc/ChangeLog: PR target/116615 * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove. --- There's a bunch more discussion in the bug, but it's st

Re: [PATCH] RISC-V: Define LOGICAL_OP_NON_SHORT_CIRCUIT to 1 [PR116615]

On Thu, 05 Sep 2024 11:52:57 PDT (-0700), Palmer Dabbelt wrote: We have cheap logical ops, so let's just move this back to the default to take advantage of the standard branch/op hueristics. gcc/ChangeLog: PR target/116615 * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CIRCUIT): R

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On Thu, Sep 5, 2024 at 3:41 PM Jeff Law wrote: > > > > On 9/5/24 12:38 PM, Raphael Zinsly wrote: > > On Thu, Sep 5, 2024 at 3:10 PM Jeff Law wrote: > >> On 9/5/24 6:16 AM, Raphael Zinsly wrote: > >>> On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: > On 9/2/24 2:01 PM, Raphael Moreira Zinsly

Re: [PATCH] c++: template depth of lambda in default targ [PR116567]

On 9/5/24 2:28 PM, Patrick Palka wrote: On Thu, 5 Sep 2024, Jason Merrill wrote: On 9/5/24 1:26 PM, Patrick Palka wrote: On Thu, 5 Sep 2024, Jason Merrill wrote: On 9/5/24 10:54 AM, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/14? -- >

Re: [PATCH] c++: vtable referring to "unavailable" virtual fn [PR116606]

On 9/5/24 2:28 PM, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? OK. -- >8 -- mark_vtable_entries already has /* It's OK for the vtable to refer to deprecated virtual functions. */ warning_sentinel w(warn_deprecated_decl); but that doesn't cover

Re: [PATCH] RISC-V: Define LOGICAL_OP_NON_SHORT_CIRCUIT to 1 [PR116615]

On Thu, 2024-09-05 at 11:59 -0700, Palmer Dabbelt wrote: > On Thu, 05 Sep 2024 11:52:57 PDT (-0700), Palmer Dabbelt wrote: > > We have cheap logical ops, so let's just move this back to the default > > to take advantage of the standard branch/op hueristics. > > > > gcc/ChangeLog: > > > > PR t

Re: [to-be-committed][V2][RISC-V] Avoid unnecessary extensions after sCC insns

On 9/5/24 12:46 PM, Palmer Dabbelt wrote: On Thu, 05 Sep 2024 11:03:18 PDT (-0700), jeffreya...@gmail.com wrote: So the first patch failed the pre-commit CI; it didn't fail in my testing because I'm using --with-arch to set a default configuration that includes things like zicond to ensure t

[PATCH] Fortran: fix ICE in gfc_create_module_variable [PR100273]

Dear all, the attached simple patch fixes a corner case related to pr84868, which was tracked separately. While Paul's patch for pr84868 added the framework for treating len_trim in the specification part of a character function, it missed the possibility that that function need not appear at the

Re: [PATCH] Fortran: fix ICE in gfc_create_module_variable [PR100273]

On 9/5/24 12:42 PM, Harald Anlauf wrote: Dear all, the attached simple patch fixes a corner case related to pr84868, which was tracked separately. While Paul's patch for pr84868 added the framework for treating len_trim in the specification part of a character function, it missed the possibilit

[PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements

Changes since v1: - Fix bit31. - Remove negative shift checks. - Fix synthesis-7.c expected output. -- >8 -- Improve handling of large constants in riscv_build_integer, generate better code for constants where the high half can be constructed by shifting/shiftNadding the l

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