On Fri, Jun 9, 2023 at 3:57 AM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
> >
> > gcc/ChangeLog:
> >
> > * config.gcc: Add riscv-fold-mem-offsets.o to
On Thu, Jun 8, 2023 at 8:37 AM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
> >
> > gcc/ChangeLog:
> >
> > * config.gcc: Add riscv-fold-mem-offsets.o to
From: Pan Li
This patch support the intrinsic API of FP16 ZVFHMIN vget/vset. From
the user's perspective, it is reasonable to do some get/set operations
for the vfloat16*_t types when only ZVFHMIN is enabled.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-ty
On Sat, Jun 10, 2023 at 6:49 PM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
> >
> > gcc/ChangeLog:
> >
> > * config.gcc: Add riscv-fold-mem-offsets.o to
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-12 15:40
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH
On Fri, 9 Jun 2023, Martin Jambor wrote:
> Hi,
>
> thanks for looking at this.
>
> On Fri, Jun 02 2023, Richard Biener wrote:
> > On Mon, 29 May 2023, Martin Jambor wrote:
> >
>
> [...]
>
> >> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
> >> index 27c84e78fcf..33215b5fc82 100644
Comparisons between memory and constants might be done in a smaller mode
resulting in smaller constants which might finally end up as immediates
instead of in the literal pool.
For example, on s390x a non-symmetric comparison like
x <= 0x3fff
results in the constant being spilled to
On Mon, 12 Jun 2023, Jiufu Guo wrote:
> Richard Biener writes:
>
> > On Fri, 9 Jun 2023, Jiufu Guo wrote:
> >
> >>
> >> Hi,
> >>
> >> Richard Biener writes:
> >>
> >> > On Fri, 9 Jun 2023, Jiufu Guo wrote:
> >> >
> >> >>
> >> >> Hi,
> >> >>
> >> >> Richard Biener writes:
> >> >>
> >> >>
From: Yanzhang Wang
This patch adds support to check function's argument or return is vector type
and throw warning if yes.
There're two exceptions,
- The vector_size attribute.
- The intrinsic functions.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Se
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8 (SV_VL1), x)
a scalar is selected based on a constant predicate and a variable vector.
This sequence is optimized to return the correspoding element of a NEON
vector. For eg.
svlasta (sv
From: Richard Sandiford
Date: Friday, May 19, 2023 at 3:20 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
> Am I correct to understand that we still need to check for the case when
> there's a repeating non-ze
On Sat, 10 Jun 2023 11:29:36 -0700
Mike Stump wrote:
> On Jun 9, 2023, at 2:47 PM, Bernhard Reutner-Fischer
> wrote:
> > But well. Either way, what
> > should we do about remote env, if there is one? If the target
> > supports it, send it and skip otherwise?
Hello Segher:
Please review and let me know your feedback to submit in trunk.
Thanks & Regards
Ajit
On 25/02/23 3:20 pm, Ajit Agarwal via Gcc-patches wrote:
> Hello All:
>
> Here is the patch that uses xxlor instead of fmr where possible.
> Performance results shows that fmr is better in power9
Tejas Belagod writes:
> From: Tejas Belagod
>
> This PR optimizes an SVE intrinsics sequence where
> svlasta (svptrue_pat_b8 (SV_VL1), x)
> a scalar is selected based on a constant predicate and a variable vector.
> This sequence is optimized to return the correspoding element of a NEON
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
I previously applied this change in r13-4565 but reverted it due to
PR108071. That PR was then fixed by r13-4712, but I didn't re-apply this
change then because we weren't making the array static; since r14-1500 for
PR110070 we now make the
The following fixes code GENERIC generation for (convert! ...)
which currently generates
if (TREE_TYPE (_o1[0]) != type)
_r1 = fold_build1_loc (loc, NOP_EXPR, type, _o1[0]);
if (EXPR_P (_r1))
goto next_after_fail867;
else
_r1 = _o1[0];
where obviously braces are missing.
Bo
This should be fixed by r14-1660-g953bbeaeff050f
On Sun, Jun 11, 2023 at 11:33 PM haochen.jiang
wrote:
> On Linux/x86_64,
>
> 28db36e2cfca1b7106adc8d371600fa3a325c4e2 is the first bad commit
> commit 28db36e2cfca1b7106adc8d371600fa3a325c4e2
> Author: Jason Merrill
> Date: Wed Jun 7 05:15:02 2
On Mon, Jun 5, 2023 at 9:26 AM liuhongt wrote:
>
> This patch only support vec_pack/unpacks optabs for vector modes whose lenth
> >= 128.
> For 32/64-bit vector, they're more hanlded by BB vectorizer with
> truncmn2/extendmn2/fix{,uns}_truncmn2.
>
> Bootstrapped and regtested on x86_64-pc-linux-g
On Tue, 2023-05-30 at 09:30 +0800, Lulu Cheng wrote:
>
> 在 2023/5/29 下午2:09, Xi Ruoyao 写道:
> > On Tue, 2023-04-18 at 21:06 +0800, Lulu Cheng wrote:
> > > Hi, ruoyao:
> > >
> > > Thank you so much for making this submission. But we are testing
> > > the
> > > impact of these two alignment paramete
From: Juzhe-Zhong
To be safe, add ZVFHMIN autovec block testcase to make sure
we won't enable autovec in ZVFHMIN by mistakes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: New test.
---
.../gcc.target/riscv/rvv/autovec/zvfhmin-1.c | 34 +++
1 fi
Hi Juzhe,
no complaints here. Just please make sure you add the commit
message or something related as top comment to the test when
committing.
Somebody who reads the test is not going to want to lookup
the commit message to know what's going on.
Regards
Robin
From: Juzhe-Zhong
To be safe, add ZVFHMIN autovec block testcase to make sure
we won't enable autovec in ZVFHMIN by mistakes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: New test.
---
.../gcc.target/riscv/rvv/autovec/zvfhmin-1.c | 35 +++
1 fi
Ok. Add comments in V2 patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-12 17:39
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add ZVFHMIN autovec block testcase
Hi Juzhe,
no complaints here. Just pleas
> +/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when
> -march="*zvfhmin*". */
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0
> "vect" } } */
Thanks. OK from my side.
Regards
Robin
> + (VNx16QI "TARGET_MIN_VLEN <= 128")
> + (VNx32QI "TARGET_MIN_VLEN <= 256")
> + (VNx64QI "TARGET_MIN_VLEN >= 64 && TARGET_MIN_VLEN <= 512")
> + (VNx128QI "TARGET_MIN_VLEN >= 128 && TARGET_MIN_VLEN <= 1024")
>
> This not correct, we always use VNx16QI as LMUL = m1 for min_vlen >= 128.
> Requi
I'd like you to defer to you commit my patch with your test (Jeff has approved
my patch, just feel free to commit).
Here is the description:
We have 3 configuration for "-march"
1. zve32* (TARGET_MIN_VLEN == 32), the LMUL = 1 mode will be VNx4QI, VNx2HI,
VNx1SI
2. zve64* (TARGET_MIN_VLEN == 64
Hi Coudert,
Sorry, missed that one.
I'll fix that.
Tamar.
> -Original Message-
> From: FX Coudert
> Sent: Saturday, June 10, 2023 9:21 PM
> To: Tamar Christina
> Cc: g...@gcc.gnu.org; Jeff Law ; gcc-
> patc...@gcc.gnu.org
> Subject: gcc/config.in was not regenerated
>
> Hi,
>
> Buil
Hi All,
Looks like I forgot to regenerate config.in which
causes updates when you enable maintainer mode.
Bootstrapped aarch64-none-linux-gnu.
Committed under obvious rule.
Thanks,
Tamar
gcc/ChangeLog:
* config.in: Regenerate.
--- inline copy of patch --
diff --git a/gcc/config.in b
On Sat, Jun 10, 2023 at 6:38 AM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> The following patch is an attempt to implement the C23 stdckdint.h
> header on top of our GNU extension - __builtin_{add,sub,mul}_overflow
> builtins.
>
> I have looked at gnulib stdckdint.h and they are full of worka
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, June 9, 2023 7:08 PM
> To: Kyrylo Tkachov via Gcc-patches
> Cc: Kyrylo Tkachov
> Subject: Re: [PATCH] simplify-rtx: Implement constant folding of
> SS_TRUNCATE, US_TRUNCATE
>
> Kyrylo Tkachov via Gcc-patches wr
On Mon, Jun 12, 2023 at 11:20:00AM +0100, Tamar Christina via Gcc-patches wrote:
> Hi All,
>
> Looks like I forgot to regenerate config.in which
> causes updates when you enable maintainer mode.
>
> Bootstrapped aarch64-none-linux-gnu.
>
> Committed under obvious rule.
Do you use the DEFAULT_MA
>
> Do you use the DEFAULT_MATCHPD_PARTITIONS macro anywhere?
> If not, why the AC_DEFINE_UNQUOTED at all and not just the AC_SUBST?
>
It used to be used to change the default of genmatch.cc, but the default is now
not to split anymore. So guess I can remove it.
Will follow up...
On Fri, 9 Jun 2023 at 17:41, Jonathan Wakely via Gcc-patches
wrote:
>
> Tested powerpc64le-linux. Pushed to trunk.
Hi Jonathan,
This patch causes following regression on armv8l-unknown-linux-gnueabihf:
FAIL: std/format/functions/format.cc execution test
/home/tcwg-buildslave/workspace/tcwg_gnu_3/a
PR106907 has few warnings spotted from cppcheck. Here we have
warnings for precedence clarification since boolean results are
used in bitwise operation. Bitwise xor performed on bool
is similar to checking inequality. So changed to inequality
operator (!=) instead of bitwise xor (^). And fixed comm
Hi,
Richard Biener writes:
> On Mon, 12 Jun 2023, Jiufu Guo wrote:
>
>> Richard Biener writes:
>>
>> > On Fri, 9 Jun 2023, Jiufu Guo wrote:
>> >
>> >>
>> >> Hi,
>> >>
>> >> Richard Biener writes:
>> >>
>> >> > On Fri, 9 Jun 2023, Jiufu Guo wrote:
>> >> >
>> >> >>
>> >> >> Hi,
>> >> >>
LGTM too, thanks
On Mon, Jun 12, 2023 at 5:46 PM Robin Dapp via Gcc-patches
wrote:
>
> > +/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when
> > -march="*zvfhmin*". */
> > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0
> > "vect" } } */
>
> Thanks
From: Pan Li
The test will fail on below command with multi-thread like below. However,
it comes from one missed "Oz" option when check vsetvl.
make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
or make without -
Committed, thanks Kito and Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Monday, June 12, 2023 8:19 PM
To: Robin Dapp
Cc: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org; kito.ch...@sifive.com;
pal...@dabbelt.com; pal...@rivosinc.com; jeff
Is this patch ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-12 10:41
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization
From: Juzhe-Zhong
Optimiz
Some more detail here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616051.html
On Mon, Jun 12, 2023 at 5:58 PM juzhe.zh...@rivai.ai
wrote:
>
> I'd like you to defer to you commit my patch with your test (Jeff has
> approved my patch, just feel free to commit).
>
> Here is the descrip
OK for this patch, and I am thinking we should adjust rvv.exp to
just exclude -O0, -Os and -Oz for some testcases run to simplify many
testcases.
On Mon, Jun 12, 2023 at 8:20 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> The test will fail on below command with multi-thread like below.
We have two style predictor for those define_insn_and_split patterns,
"TARGET_VECTOR"/"&& can_create_pseudo_p ()" and "TARGET_VECTOR &&
can_create_pseudo_p ()"/"&& 1", could you unify all to later form? I
feel that would be safer since those patterns are really only valid
before RA(can_create_pseud
On 05/06/2023 04:04, Jan Hubicka wrote:
On Thu, 1 Jun 2023, Andre Vieira (lists) wrote:
Hi,
This is a follow-up of the internal function patch to add widening and
narrowing patterns. This patch improves the inliner cost estimation for
internal functions.
I have no idea why calls are spec
You mean change all split pattern like this ?
;; This helps to match zero_extend + sign_extend + fma.
(define_insn_and_split "*zero_sign_extend_fma"
[(set (match_operand:VWEXTI 0 "register_operand")
(plus:VWEXTI
(mult:VWEXTI
(zero_extend:VWEXTI
(match_operand: 2 "register_oper
I found there're still some test cases that does not pass. I'll push
another version soon. Sorry for the inconvenience.
> -Original Message-
> From: Wang, Yanzhang
> Sent: Monday, June 12, 2023 4:08 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pa
Hi Yan-Zhang:
OK with one minor, go ahead IF the regression is clean.
Hi Pan:
Could you help to verify this patch and commit if the regression is clean?
thanks :)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79
Yes, change all define_insn_and_split to that style, "TARGET_VECTOR &&
can_create_pseudo_p ()"/ "&& 1", my understanding is all those
patterns should only work before RA, so all using "TARGET_VECTOR &&
can_create_pseudo_p ()" is more reasonable.
On Mon, Jun 12, 2023 at 8:41 PM juzhe.zh...@rivai.a
lgtm
On Mon, Jun 12, 2023 at 3:43 PM juzhe.zh...@rivai.ai
wrote:
>
> LGTM
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-12 15:40
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vge
Sure thing, will commit it after all riscv.exp rvv.exp pass.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, June 12, 2023 8:43 PM
To: Wang, Yanzhang
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Li, Pan2
Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.
Hi Yan-Zh
Hi!
On Sat, Feb 25, 2023 at 03:20:33PM +0530, Ajit Agarwal wrote:
> Here is the patch that uses xxlor instead of fmr where possible.
> Performance results shows that fmr is better in power9 and
> power10 architectures whereas xxlor is better in power7 and
> power 8 architectures. fmr is the only
Hi All,
As Jakub pointed out, DEFAULT_MATCHPD_PARTITIONS
is now unused and can be removed.
Bootstrapped aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Remove DEFAULT_MA
On Mon, 12 Jun 2023, Andre Vieira (lists) wrote:
>
>
> On 05/06/2023 04:04, Jan Hubicka wrote:
> >> On Thu, 1 Jun 2023, Andre Vieira (lists) wrote:
> >>
> >>> Hi,
> >>>
> >>> This is a follow-up of the internal function patch to add widening and
> >>> narrowing patterns. This patch improves the
On Mon, 12 Jun 2023, Tamar Christina wrote:
> Hi All,
>
> As Jakub pointed out, DEFAULT_MATCHPD_PARTITIONS
> is now unused and can be removed.
>
> Bootstrapped aarch64-none-linux-gnu and no issues.
>
> Ok for master?
OK.
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> * config.in: Regenerate
On Mon, Jun 12, 2023 at 01:53:26PM +0100, Tamar Christina wrote:
> gcc/ChangeLog:
>
> * config.in: Regenerate.
> * configure: Regenerate.
> * configure.ac: Remove DEFAULT_MATCHPD_PARTITIONS.
Ok, thanks.
Jakub
Alias analysis was treating .MASK_STORE as storing a full vector
which means we disambiguate against decls of smaller than vector size.
That's of course wrong and a similar issue was fixed for DSE already.
The following makes sure we set the size of the access to unknown
and only constrain max_size
Hi,
For stack_tie, currently below insn is generated:
(insn 15 14 16 3 (parallel [
(set (mem/c:BLK (reg/f:DI 1 1) [1 A8])
(const_int 0 [0]))
]) "/home/guojiufu/temp/gdb.c":13:3 922 {stack_tie}
(nil))
It is "set (mem/c:BLK (reg/f:DI 1 1) (const_int 0 [
From: Juzhe-Zhong
According to RVV ISA:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
We can enhance VLA SLP auto-vectorization with (16.5.1. Synthesizing
vdecompress)
Decompress operation.
Case 1 (nunits = POLY_INT_CST [16, 16]):
_48 = VEC_PERM_EXPR <_37, _35, { 0, POLY_INT_CS
I found that add the -Wno-psabi to CFLAGS will be overrode by
dg-options. It seems we can only add this option to the third
arg of dg-runtest. Attach the dg-runtest comments,
# dg-runtest -- simple main loop useful to most testsuites
#
# OPTIONS is a set of options to always pass.
# DEFAULT_EXTRA_
The following simple test case, from PR 104610, shows that memcmp () == 0
can result in some bizarre code sequences on x86.
int foo(char *a)
{
static const char t[] = "0123456789012345678901234567890";
return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
}
with -O2 currently contains both:
How about appending to DEFAULT_CFLAGS?
On Mon, Jun 12, 2023 at 9:38 PM Wang, Yanzhang via Gcc-patches
wrote:
>
> I found that add the -Wno-psabi to CFLAGS will be overrode by
> dg-options. It seems we can only add this option to the third
> arg of dg-runtest. Attach the dg-runtest comments,
>
> #
Committed, thanks Kito and will take care of the define_insn_and_split part in
another PATCH.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Monday, June 12, 2023 8:45 PM
To: juzhe.zh...@rivai.ai
Cc: kito.cheng ; gcc-patches ;
palmer ; palmer ;
Committed, thanks Kito and Juzhe.
Pan
From: Kito Cheng
Sent: Monday, June 12, 2023 11:33 AM
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ;
rdapp.gcc ; Jeff Law ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API
Lgtm too :)
钟居哲 mailto:juzhe.zh...@rivai.ai>>
Committed, thanks Kito.
Sounds good to me. Not sure if there are some tests focus on -O0/Os/Oz, we can
refine this in another PATCH.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, June 12, 2023 8:30 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@g
It's the same behavior. Because the DEFAULT_CFLAGS will be copied to
CFLAGS and then passed as the DEFAULT_EXTRA_OPTIONS to dg-runtest.
> -Original Message-
> From: Kito Cheng
> Sent: Monday, June 12, 2023 10:08 PM
> To: Wang, Yanzhang
> Cc: Kito Cheng ; gcc-patches@gcc.gnu.org;
> juzhe.
On 6/12/23 07:36, Wang, Yanzhang via Gcc-patches wrote:
I found that add the -Wno-psabi to CFLAGS will be overrode by
dg-options. It seems we can only add this option to the third
arg of dg-runtest. Attach the dg-runtest comments,
I think we default to -Wno-psabi to avoid triggering diagnostic
On 6/12/23 01:36, Manolis Tsamis wrote:
Even if late, one question for the dynamic instruction numbers.
Was this measured just with f-m-o or with the stack pointer fold patch
applied too?
I remember I was getting better improvements in the past, but most of
the cases had to do with the sta
Hi Juzhe,
seems a nice improvement, looks good to me. While reading I was wondering
if vzext could help synthesize some (zero-based) patterns as well
(e.g. 0 3 0 3...).
However the sequences I could come up with were not shorter than what we
are already emitting, so probably not.
Regards
Robin
No. Such pattern you pointed I already supported.
The operation is very simple.
Just use a single vmv.v.i but larger SEW is enough. No need vzext.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-12 22:43
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; je
Hmmm, yeah, I think let's add it case by case...I assume we should get
it rid before GCC 14, it is mostly used for the transition period
before we settle down the ABI and for GCC 13.
On Mon, Jun 12, 2023 at 10:34 PM Jeff Law wrote:
>
>
>
> On 6/12/23 07:36, Wang, Yanzhang via Gcc-patches wrote:
>
I didn't take a close review yet, (and I suspect I can't find time
before I start my vacation :P), but I am thinking we may adding
selftests for expand_const_vector in *future*, again, not blocker for
this patch :)
On Mon, Jun 12, 2023 at 10:51 PM 钟居哲 wrote:
>
> No. Such pattern you pointed I alr
Hi,
this implements the vec_set and vec_extract patterns for integer and
floating-point data types. For vec_set we broadcast the insert value to
a vector register and then perform a vslideup with effective length 1 to
the requested index.
vec_extract is done by sliding down the requested element
On 6/12/23 08:54, Kito Cheng wrote:
I didn't take a close review yet, (and I suspect I can't find time
before I start my vacation :P), but I am thinking we may adding
selftests for expand_const_vector in *future*, again, not blocker for
this patch :)
I'll take this one. Go enjoy your vacatio
Hi,
when the destination register of a vmv.x.s needs to be sign extended to
XLEN we currently emit an sext insn. Since vmv.x.s performs this
implicitly this patch adds two instruction patterns (intended for
combine et al.) that include sign_extend for the destination operand.
The tests extend th
From: Juzhe-Zhong
According to RVV ISA:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
We can enhance VLA SLP auto-vectorization with (16.5.1. Synthesizing
vdecompress)
Decompress operation.
Case 1 (nunits = POLY_INT_CST [16, 16]):
_48 = VEC_PERM_EXPR <_37, _35, { 0, POLY_INT_CS
+ /* If the slide offset fits into 5 bits we can
+ use the immediate variant instead of the register variant.
+ The expander's operand[2] is ops[3] here. */
+ if (!satisfies_constraint_K (ops[3]))
+ops[3] = force_reg (Pmode, ops[3]);
I don't think we need this. maybe_expand_insn shou
Change
+(define_insn "@pred_extract_first_sextdi"
into
(define_insn "*pred_extract_first_sextdi"
Change
+(define_insn "@pred_extract_first_sextsi"
into
(define_insn "*pred_extract_first_sextsi"
I don't think we will call combine pattern in vector-opt.md in the future.
Use "*" instead of "@" can
I would suggest breaking this patch into two parts: RISC-V part and
the rest part (shrink-wrap.h / shrink-wrap.cc).
On Wed, Jun 7, 2023 at 1:55 PM Fei Gao wrote:
>
> Disable zcmp multi push/pop if shrink-wrap-separate is active.
>
> So in -Os that prefers smaller code size, by default shrink-wra
> Change
>
> +(define_insn "@pred_extract_first_sextdi"
>
> into
>
> (define_insn "*pred_extract_first_sextdi"
Yeah, I was thinking about this as well right after sending.
We will probably never call this directly.
Regards
Robin
> + /* If the slide offset fits into 5 bits we can
> + use the immediate variant instead of the register variant.
> + The expander's operand[2] is ops[3] here. */
> + if (!satisfies_constraint_K (ops[3]))
> + ops[3] = force_reg (Pmode, ops[3]);
>
> I don't think we need this. maybe_ex
This patch set completes the range-op dispatch and unification rework.
The first 7 patches move the remainder of the integral table to the
unified table, and remove the integer table.
The 8th patch moves all the pointer specific code into a new file
range-op-ptr.cc
Patches 9-12 introduce a
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 438f8281ad2d821e09eaf5691d1b76b6f2f39b4c Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 15:56:15 -0400
Subject: [PATCH 01/17] Move operator_addr_expr to the unified range-op table.
* range-op-mix
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 5bb4c53870db1331592a89119f41beee2b17d832 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 15:59:43 -0400
Subject: [PATCH 02/17] Move operator_bitwise_not to the unified range-op
table.
* range-op-m
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From cc18db2826c5449e84366644fa461816fa5f3f99 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:01:05 -0400
Subject: [PATCH 03/17] Move operator_bitwise_xor to the unified range-op
table.
* range-op-m
This is the last of the integral operators, so also remove the integral
table.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 6585fa54e0f2a54f1a398b49b5b4b6a9cd6da4ea Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:10:54 -0400
Subject: [PATC
Add a hybrid operator to choose between integer and pointer versions at
runtime.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 08f2e419b1e29f114857b3d817904abf3b4891be Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:34:26 -0400
Subject: [PA
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From f2166fc81194a3e4e9ef185a7404551b410bb752 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:02:09 -0400
Subject: [PATCH 04/17] Move operator_bitwise_and to the unified range-op
table.
At this point
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From a71ee5c2d48691280f76a90e2838d968f45de0c8 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:05:33 -0400
Subject: [PATCH 05/17] Move operator_bitwise_or to the unified range-op table.
* range-op-mix
This patch moves all the pointer specific code into a new file
range-op-ptr.cc
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From cb511d2209fa3a05801983a6965656734c1592c6 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:17:51 -0400
Subject: [PATC
Lucky 13. WIth the unified table complete, it is no longer necessary to
specify a type when constructing a range_op_handler. This patch removes
that requirement.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 8934830333933349d41e62f9fd6a3d21ab71150c Mon Sep 17 00:
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 508645fd461ceb8b743837e24411df2e17bd3950 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:09:58 -0400
Subject: [PATCH 06/17] Move operator_min to the unified range-op table.
* range-op-mixed.h (c
Now that the unified table is the only one, remove it and simply use
range_op_table as the class instead of inheriting from it.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 5bb9d2acd1987f788a52a2be9bca10c47033020a Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Da
This patch removes the hack introduced late last year for the
non-standard range-op support.
Instead of adding a a pointer to a range_operator in the header file,
and then setting the operator from another file via that pointer, the
table itself is extended and we provide new #defines to decl
Add a hybrid operator to choose between integer and pointer versions at
runtime.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 8adb8b2fd5797706e9fbb353d52fda123545431d Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:28:40 -0400
Subject: [PA
This provides range_op_handler with a default range_operator, so you no
longer need to check if it has a valid handler or not.
The valid check now turns into a "is this something other than a default
operator" check. IT means you can now simply invoke fold without
checking.. ie instead of
Add a hybrid operator to choose between integer and pointer versions at
runtime.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 80f402e832a2ce402ee1562030d5c67ebc276f7c Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Sat, 10 Jun 2023 16:33:17 -0400
Subject: [PA
Add some missing overrides, and add the diaptch pattern for FII which
will be used for integer to float conversion.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 1bed4b49302e2fd7bf89426117331ae89ebdc90b Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Mon, 12 J
Add a hybrid operator to choose between integer and pointer versions at
runtime.
This is the last use of the pointer table, so it is also removed.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From cd194f582c5be3cc91e025e304e2769f61ceb6b6 Mon Sep 17 00:00:00 2001
From:
Cleanup follow up to
r14-1579-g4ede915d5dde93 "openmp: Add support for the 'present' modifier"
committed 6 days ago.
Namely:
* Replace for the program → libgomp ABI GOMP_MAP_PRESENT_[ALLOC,TO,FROM,TOFROM]
by the preexisting GOMP_MAP_FORCE_PRESENT but keep the other enum values
(and use them
On Wed, 31 May 2023 at 00:23, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi Richard,
> > The s32 case for single constant patch doesn't regress now after the
> > above commit.
> > Bootstrapped+tested on aarch64-linux-gnu, and verified that the new
> > tests pass for aarch64_be-l
Same remark for all your alike patches.
On 11/06/2023 04:43, Ken Matsui via Libstdc++ wrote:
This patch gets std::is_reference to dispatch to new built-in trait
__is_reference.
libstdc++-v3/ChangeLog:
* include/std/type_traits (is_reference): Use __is_reference built-in
trait.
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