Hi, Richard. Thanks for the comments.
>> If we use SELECT_VL to refer only to the target-independent ifn, I don't
>> see why this last bit is true.
Could you give me more details and information about this since I am not sure
whether I catch up with you.
You mean the current SELECT_VL is not an
+DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_R
Thanks, make sense, will update V2 for this.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, June 5, 2023 3:30 PM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Li, Pan2 ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic
API
+DEF_RVV_WEXTF_OPS (vfloat
"juzhe.zh...@rivai.ai" writes:
> Hi, Richard. Thanks for the comments.
>
>>> If we use SELECT_VL to refer only to the target-independent ifn, I don't
>>> see why this last bit is true.
> Could you give me more details and information about this since I am not sure
> whether I catch up with you.
Richard Sandiford writes:
> "juzhe.zh...@rivai.ai" writes:
>> Hi, Richard. Thanks for the comments.
>>
If we use SELECT_VL to refer only to the target-independent ifn, I don't
see why this last bit is true.
>> Could you give me more details and information about this since I am not
>>
Hi, Richard.
>> No, I meant that the comment I quoted seemed to be saying that solution
>> 3 wasn't possible. The comment seemed to say that we would need to do
>> solution 1.
I am so sorry that I didn't write the comments accurately.
Could you help me with comments ? Base on what we have discuss
On 5/23/23 08:21, Jonathan Yong wrote:
On 5/22/23 13:25, Costas Argyris wrote:
Currently on Windows, when CreateProcess is called with a command-line
that exceeds the 32k Windows limit, we get a very bad error:
"CreateProcess: No such file or directory"
This patch detects the case where this w
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode
'MODE'.
* config/riscv/vector.md
(@pred_indexed_store): change
VNX16_QHSI to VNX16_QHSDI.
(@pred_indexed_store): Ditto.
---
gcc/config/riscv/vector-iterators.md | 26 +-
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:
vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin
Updated the PATCH V2 for the ZVFH requirement.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620636.html
Pan
From: Li, Pan2
Sent: Monday, June 5, 2023 3:37 PM
To: juzhe.zh...@rivai.ai; gcc-patches
Cc: Kito.cheng ; Wang, Yanzhang
Subject: RE: [PATCH v1] RISC-V: Support RVV FP16 ZVFH float
Thanks for catching this.
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-05 16:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in
vector-iterators.md.
gcc/ChangeLog:
* config/riscv/vector-iterator
LGTM,
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-05 16:20
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point. A
Only a few minor comments, otherwise LGTM :)
But I guess we need to wait until binutils merge zc stuff.
> Zcmp can share the same logic as save-restore in stack allocation:
> pre-allocation
> by cm.push, step 1 and step 2.
>
> please be noted cm.push pushes ra, s0-s11 in reverse order than what
LGTM
On Mon, Jun 5, 2023 at 4:27 PM juzhe.zh...@rivai.ai
wrote:
>
> Thanks for catching this.
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Li Xu
> Date: 2023-06-05 16:18
> To: gcc-patches
> CC: kito.cheng; palmer; juzhe.zhong; Li Xu
> Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode
Sorry for the late, I will send the binutils patch within this week.
- Original Message -
From: "Kito Cheng"
To: "Fei Gao"
Cc: gcc-patches@gcc.gnu.org, pal...@dabbelt.com, jeffreya...@gmail.com,
sinan@linux.alibaba.com, jia...@iscas.ac.cn
Sent: Mon, 5 Jun 2023 16:31:29 +0800
Su
Thanks Kito.
I will propose V4 and also make a separate patch to fix
riscv_adjust_libcall_cfi_prologue.
BR,
Fei
On 2023-06-05 16:31 Kito Cheng wrote:
>
>Only a few minor comments, otherwise LGTM :)
>
>But I guess we need to wait until binutils merge zc stuff.
>
>> Zcmp can share the same lo
Hi Carl,
on 2023/5/2 23:52, Carl Love via Gcc-patches wrote:
> GCC maintainers:
>
> The following patch adds three buitins for inserting and extracting the
> exponent and significand for an IEEE 128-bit floating point values.
> The builtins are valid for Power 9 and Power 10.
We already have:
LGTM too, thanks :)
On Mon, Jun 5, 2023 at 4:27 PM juzhe.zh...@rivai.ai
wrote:
>
> LGTM,
>
>
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2023-06-05 16:20
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH v2] RISC-V: S
Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, June 5, 2023 4:47 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Wang,
Yanzhang
Subject: Re: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic
API
LGTM too, thanks :)
O
Thanks, here is the follow up patch for a couple typos in the same file.
On Mon, 5 Jun 2023 at 09:12, Jonathan Yong <10wa...@gmail.com> wrote:
> On 5/23/23 08:21, Jonathan Yong wrote:
> > On 5/22/23 13:25, Costas Argyris wrote:
> >> Currently on Windows, when CreateProcess is called with a comman
Hi!
On Mon, Jun 05, 2023 at 12:11:42PM +0530, P Jeevitha wrote:
> PR106907 has few warnings spotted from cppcheck. In that addressing duplicate
> expression issue here. Here the same expression is used twice in logical
> AND(&&) operation which result in same result so removing that.
>
> 2023-06-
This patch optimizes the boolean evaluation of EQ/NE against zero
by adding two insn_and_split patterns similar to SImode conditional
store:
"eq_zero":
op0 = (op1 == 0) ? 1 : 0;
op0 = clz(op1) >> 5; /* optimized (requires TARGET_NSA) */
"movsicc_ne0_reg_0":
op0 = (op1 !=
"juzhe.zh...@rivai.ai" writes:
> Hi, Richard.
>
>>> No, I meant that the comment I quoted seemed to be saying that solution
>>> 3 wasn't possible. The comment seemed to say that we would need to do
>>> solution 1.
> I am so sorry that I didn't write the comments accurately.
> Could you help me wi
>> But it would make the pointer IV updates more complex. So let's
>> say that that's the reason for preferring solution 3.
Yes, I prefer pointer solution 3 to avoid complex IV updates and there is
no benefits in solution 2(unlike single-rgroup).
I read your comments, it's more comprehensive tha
"Roger Sayle" writes:
> This patch provides a wide-int implementation of bitreverse, that
> implements both of Richard Sandiford's suggestions from the review at
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618215.html of an
> improved API (as a stand-alone function matching the bswap refa
From: Ju-Zhe Zhong
Co-authored-by: Richard Sandiford
This patch address comments from Richard and rebase to trunk.
This patch is adding SELECT_VL middle-end support
allow target have target dependent optimization in case of
length calculation.
This patch is inspired by RVV ISA and LLVM:
https:
Hi, Richard and Richi.
Thanks for the help.
This patch is boostrap PASS. Ok for trunk？
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-05 18:30
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V3] VECT: Add SELECT_VL support
From: Ju-Zhe Zhong
Co-authored-
More update, just passed regression on X86.
Thanks.
juzhe.zh...@rivai.ai
发件人： juzhe.zh...@rivai.ai
发送时间： 2023-06-05 18:40
收件人： 钟居哲; gcc-patches
抄送： richard.sandiford; rguenther
主题： Re: [PATCH V3] VECT: Add SELECT_VL support
Hi, Richard and Richi.
Thanks for the help.
This patch is boostrap PA
Hi David,
Hm, I'm seeing this failure only in pre-commit testing, but I don't see it in
our post-commit testing of gcc:master.
Does this patch rely on your other patch committed just before this one?
--
Maxim Kuvyrkov
https://www.linaro.org
> On Jun 3, 2023, at 09:23, Maxim Kuvyrkov wrote:
On 6/5/23 09:22, Costas Argyris wrote:
Thanks, here is the follow up patch for a couple typos in the same file.
Thanks, pushed as obvious.
Hi!
OK to push the attached
"Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90'"?
Grüße
Thomas
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas
Heurung, Frank T
Hi!
OK to push the attached
"driver: Forward '-lgfortran', '-lm' to offloading compilation"?
(We didn't have a PR open for that, or did we?)
Grüße
Thomas
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschränkter Haf
On 6/5/23 00:29, Richard Biener wrote:
But then for example x86 has smaller encoding for byte ops and while
widening is easily done later, truncation is not.
Which probably argues we need to be checking costs.
Btw, you failed to update the overall function comment which lists
the convers
On 30/05/2023 07:26, Richard Biener wrote:
On Fri, May 26, 2023 at 4:35 PM Andrew Stubbs wrote:
Hi all,
I want to implement a vector DIVMOD libfunc for amdgcn, but I can't just
do it because the GCC middle-end models DIVMOD's return value as
"complex int" type, and there are no vector equival
Hi All,
This patch adds support for a compact syntax for specifying constraints in
instruction patterns. Credit for the idea goes to Richard Earnshaw.
With this new syntax we want a clean break from the current limitations to make
something that is hopefully easier to use and maintain.
The idea
> On Jun 3, 2023, at 19:17, Jeff Law wrote:
>
> On 6/2/23 09:20, Maxim Kuvyrkov via Gcc-patches wrote:
>> This patch adds tracking of current testsuite "tool" and "exp"
>> to the processing of .sum files. This avoids aliasing between
>> tests from different testsuites with same name+description.
writeargv can be simplified by getting rid of the error exit mode
that was only relevant many years ago when the function used
to open the file descriptor internally.
From 1271552baee5561fa61652f4ca7673c9667e4f8f Mon Sep 17 00:00:00 2001
From: Costas Argyris
Date: Mon, 5 Jun 2023 15:02:06 +0100
Su
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH Reduction floating-point.
Aka SEW=16 for below instructions:
vfredosum vfredusum
vfredmax vfredmin
vfwredosum vfwredusum
Then users can leverage the instrinsic APIs to perform the FP=16 related
reduction operations. Please note not
Am 03.06.23 um 17:53 schrieb Jeff Law:
On 6/2/23 02:46, Georg-Johann Lay wrote:
There is the following bug in postreload that can be traced back
to v5 at least:
In postreload.cc::reload_cse_move2add() there is a loop over all
insns. If it encounters a SET, the next insn is analyzed if it
From: Pan Li
This patch would like to fix some typo in vector-iterators.md, aka:
[-"vnx1DI")-]{+"vnx1di")+}
[-"vnx2SI")-]{+"vnx2si")+}
[-"vnx1SI")-]{+"vnx1si")+}
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix typo in mode attr.
---
gcc/config/riscv/vect
Ping on this patch.
The C FE and Doc changes has been approved.
Please help to review and approve the Middle-end change.
Or provide guide on how to move this patch forward.
Thanks a lot for the help.
Qing
Begin forwarded message:
From: Qing Zhao mailto:qing.z...@oracle.com>>
Subject: [V9][PAT
Hi Suwa-san,
On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
Ping for the front-end maintainers' input.
On Mon, 22 May 2023, Richard Biener wrote:
> On Thu, May 18, 2023 at 11:04 PM Alexander Monakov via Gcc-patches
> wrote:
> >
> > Implement -ffp-contract=on for C and C++ without changing default
> > behavior (=off for -std=cNN, =fast for C++ and -std=gn
gcc/ChangeLog:
* rtl.h (reg_classes_intersect_p): Change return type from int to bool.
(reg_class_subset_p): Ditto.
* reginfo.cc (reg_classes_intersect_p): Ditto.
(reg_class_subset_p): Ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros
diff --git a/gcc/re
Also change one internal variable to bool.
gcc/ChangeLog:
* rtl.h (print_rtl_single): Change return type from int to void.
(print_rtl_single_with_indent): Ditto.
* print-rtl.h (class rtx_writer): Ditto. Change m_sawclose to bool.
* print-rtl.cc (rtx_writer::rtx_writer): Update fo
On 6/5/23 09:06, Georg-Johann Lay wrote:
Am 03.06.23 um 17:53 schrieb Jeff Law:
On 6/2/23 02:46, Georg-Johann Lay wrote:
There is the following bug in postreload that can be traced back
to v5 at least:
In postreload.cc::reload_cse_move2add() there is a loop over all
insns. If it encoun
Hi,
All special enums have declarations in the D runtime library, but the
compiler will recognize and treat them specially if declared in any
module. When the underlying base type of a special enum is a different
size to its matched intrinsic, then this can cause undefined behavior at
runtime. D
On 6/5/23 00:29, Richard Biener wrote:
But then for example x86 has smaller encoding for byte ops and while
widening is easily done later, truncation is not.
Sadly, the x86 costing looks totally bogus here. We actually emit the
exact same code for a QI mode loads vs a zero-extending load f
On 6/5/23 09:07, Pan Li via Gcc-patches wrote:
From: Pan Li
This patch would like to fix some typo in vector-iterators.md, aka:
[-"vnx1DI")-]{+"vnx1di")+}
[-"vnx2SI")-]{+"vnx2si")+}
[-"vnx1SI")-]{+"vnx1si")+}
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector-iterators.m
On 6/5/23 02:09, Richard Biener wrote:
On Fri, Jun 2, 2023 at 6:57 PM Jason Merrill via Gcc-patches
wrote:
Since Jonathan approved the library change, I'm looking for middle-end
approval for the tree-eh change, even without advice on the potential
follow-up.
On 5/24/23 14:55, Jason Merrill wr
Looks good! Just some minor comments:
Tamar Christina writes:
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index
> 6a435eb44610960513e9739ac9ac1e8a27182c10..1437ab55b260ab5c876e92d59ba39d24bffc6276
> 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -27,6 +27,7 @@ See the next
On 2023/06/06 0:15, Max Filippov wrote:
> Hi Suwa-san,
Hi! Thanks for your regtest every time.
>
> On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
> wrote:
>>
>> This patch optimizes the boolean evaluation of EQ/NE against zero
>> by adding two insn_and_split patterns similar to SIm
Here when substituting the injected class name A during regeneration of
the lambda, we find ourselves in lookup_template_class for A with
V=_ZTAXtl3BarEE (i.e. the template parameter object for Foo{}). The
call to coerce_template_parms within then undesirably tries to make a copy
of this class NTT
On Mon, Jun 5, 2023 at 8:15 AM Max Filippov wrote:
>
> Hi Suwa-san,
>
> On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
> wrote:
> >
> > This patch optimizes the boolean evaluation of EQ/NE against zero
> > by adding two insn_and_split patterns similar to SImode conditional
> > store:
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-05 22:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point
intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH Reducti
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, June 6, 2023 3:01 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Fix some typo in vector-iterators.md
On 6/5/23 09
Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Monday, June 5, 2023 4:39 PM
To: juzhe.zh...@rivai.ai
Cc: Li Xu ; gcc-patches ;
palmer
Subject: Re: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in
ve
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index e4f2ba90799..c338e3c9003 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [
> ])
> (define_mod
Oh. YES. Thanks for catching this.
VF will be used in autovec for example: vfadd.
When specify zfhmin, the vfadd autovec will be enabled unexpectedly.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
Subje
I see. I restricted the ZVFH/ZVFHMIN from the riscv-vector-builtins-types.def
for ops definition but lack the consideration of autovec part.
Do you prefer leave this PATCH as is and fix this issue in another PATCH
entirely OR
update this PATCH V2 for predictor and send another PATCH for the p
I think we should split instructions pattern which belongs to ZVFHMIN.
And add ZVFH gating into all original iterator for example: VF VWFetc.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
Subject: R
OK for landing this patch first, and fix by follow up patches.
On Tue, Jun 6, 2023 at 9:41 AM juzhe.zh...@rivai.ai
wrote:
>
> I think we should split instructions pattern which belongs to ZVFHMIN.
> And add ZVFH gating into all original iterator for example: VF VWFetc.
>
> ___
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): use Pmode
for cfi reg/mem machmode
(riscv_adjust_libcall_cfi_epilogue): use Pmode for cfi reg machmode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-restore-cfi-2.c: New test to check machmode
On 6/5/23 19:57, Fei Gao wrote:
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): use Pmode
for cfi reg/mem machmode
(riscv_adjust_libcall_cfi_epilogue): use Pmode for cfi reg machmode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-res
Committed, thanks Kito and Juzhe, will fix the issue we discussed soon.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, June 6, 2023 9:48 AM
To: juzhe.zh...@rivai.ai
Cc: kito.cheng ; Li, Pan2 ;
gcc-patches ; Wang, Yanzhang
Subject: Re: Re: [PATCH v1] RISC-V: Support RVV FP16 ZV
On 6/5/23 00:07, Fei Gao wrote:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-restore-cfi.c: New test to check save-restore
cfi directives.
Wrapped the ChangeLog to 80 columns and pushed to the trunk.
Thanks,
Jeff
Oops. Sorry. Committed as obvious. A bootstrap
--enable-checking=yes,extra,rtl (same as the reporter, but
not the default) with the patch completed, where a bootstrap
without it failed.
-- >8 --
PR bootstrap/110120
* postreload.cc (reload_cse_move2add, move2add_use_add2_insn): U
Ok for trunk. Thank you for updating this!
Eugene
-Original Message-
From: Gcc-patches On
Behalf Of Andi Kleen via Gcc-patches
Sent: Tuesday, May 30, 2023 4:08 AM
To: gcc-patches@gcc.gnu.org
Cc: Andi Kleen
Subject: [EXTERNAL] [PATCH] Update perf auto profile script
- Fix gen_autofdo_e
On 6/5/23 10:18, Marek Polacek via Gcc-patches wrote:
Ping. Anyone have any further comments?
Given this was approved before, but got reverted due to issues (which
have since been addressed) -- I think you might as well go forward and
sooner rather than later so that we can catch fallout ea
On 6/5/23 08:37, Costas Argyris via Gcc-patches wrote:
writeargv can be simplified by getting rid of the error exit mode
that was only relevant many years ago when the function used
to open the file descriptor internally.
[ ... ]
Thanks. I've pushed this to the trunk.
You could (as a follow
From: Juzhe-Zhong
This patch enables basic VLA SLP auto-vectorization.
Consider this following case:
void
f (uint8_t *restrict a, uint8_t *restrict b)
{
for (int i = 0; i < 100; ++i)
{
a[i * 8 + 0] = b[i * 8 + 7] + 1;
a[i * 8 + 1] = b[i * 8 + 7] + 2;
a[i * 8 + 2] = b[i * 8
r14-1145 fold the intrinsics into gimple ABS_EXPR which has UB for
TYPE_MIN, but PABSB will store unsigned result into dst. The patch
uses ABSU_EXPR + VCE instead of ABS_EXPR.
Also don't fold _mm_abs_{pi8,pi16,pi32} w/o TARGET_64BIT since 64-bit
vector absm2 is guarded with TARGET_MMX_WITH_SSE.
B
Since mask < 0 will be always false when -funsigned-char, but
vpblendvb needs to check the most significant bit.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk and backport to GCC12/GCC13 release branch?
gcc/ChangeLog:
PR target/110108
* config/i386/i386-b
On Mon, Jun 5, 2023 at 9:34 PM liuhongt via Gcc-patches
wrote:
>
> Since mask < 0 will be always false when -funsigned-char, but
> vpblendvb needs to check the most significant bit.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk and backport to GCC12/GCC13 release bra
On Mon, Jun 5, 2023 at 9:34 PM liuhongt via Gcc-patches
wrote:
>
> r14-1145 fold the intrinsics into gimple ABS_EXPR which has UB for
> TYPE_MIN, but PABSB will store unsigned result into dst. The patch
> uses ABSU_EXPR + VCE instead of ABS_EXPR.
>
> Also don't fold _mm_abs_{pi8,pi16,pi32} w/o TAR
When building riscv32-none-elf with "--enable-checking=yes,rtl", the
following ICE is observed:
cc1: internal compiler error: RTL check: expected code 'const_int', have
'const_double' in riscv_const_insns, at config/riscv/riscv.cc:1313
0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code,
During libgcc configure stage for riscv32-none-elf, when
"--enable-checking=yes,rtl" has been activated, the following error
is observed:
configure:3814:
/home/dinux/projects/pru/local-workspace/riscv32-gcc-build/./gcc/xgcc
-B/home/dinux/projects/pru/local-workspace/riscv32-gcc-build/./gcc/
-
Jie Mei 于2023年5月19日周五 16:07写道：
>
> From: Simon Dardis
>
> Support for __attribute__ ((code_readable)). Takes up to one argument of
> "yes", "no", "pcrel". This will change the code readability setting for just
> that function. If no argument is supplied, then the setting is 'yes'.
>
> gcc/Chan
On Mon, Jun 5, 2023 at 3:49 PM Andrew Stubbs wrote:
>
> On 30/05/2023 07:26, Richard Biener wrote:
> > On Fri, May 26, 2023 at 4:35 PM Andrew Stubbs wrote:
> >>
> >> Hi all,
> >>
> >> I want to implement a vector DIVMOD libfunc for amdgcn, but I can't just
> >> do it because the GCC middle-end mo
On Mon, Jun 5, 2023 at 8:41 PM Jeff Law wrote:
>
>
>
> On 6/5/23 00:29, Richard Biener wrote:
>
> >
> > But then for example x86 has smaller encoding for byte ops and while
> > widening is easily done later, truncation is not.
> Sadly, the x86 costing looks totally bogus here. We actually emit th
From: Simon Dardis
Support for __attribute__ ((code_readable)). Takes up to one argument of
"yes", "no", "pcrel". This will change the code readability setting for just
that function. If no argument is supplied, then the setting is 'yes'.
gcc/ChangeLog:
* config/mips/mips.cc (enum mi
On Tue, Jun 6, 2023 at 6:17 AM wrote:
>
> From: Juzhe-Zhong
>
> This patch enables basic VLA SLP auto-vectorization.
> Consider this following case:
> void
> f (uint8_t *restrict a, uint8_t *restrict b)
> {
> for (int i = 0; i < 100; ++i)
> {
> a[i * 8 + 0] = b[i * 8 + 7] + 1;
>
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