pan2...@intel.com writes:
> From: Pan Li
>
> The decl_or_value is defined as void * before this PATCH. It will take
> care of both the tree_node and rtx_def. Unfortunately, given a void
> pointer cannot tell the input is tree_node or rtx_def.
>
> Then we have some implicit structure layout require
On Thu, 11 May 2023, Alan Modra wrote:
> On Thu, May 04, 2023 at 11:02:25AM +, Richard Biener via Binutils wrote:
> > So since we expect the linker to use the host side table is there a way
> > for the plugin to exactly query that (the set of symbols the linker
> > uses from the object passed
juzhe.zh...@rivai.ai writes:
> From: Juzhe-Zhong
>
> This is patch is a seperate patch preparing for supporting decrement IV.
>
> gcc/ChangeLog:
>
> * cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
> * gimple-loop-interchange.cc
> (tree_loop_interchange::map_induction
On 5/10/23 16:52, Kyrylo Tkachov wrote:
-Original Message-
From: Christophe Lyon
Sent: Wednesday, May 10, 2023 2:31 PM
To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
Richard Earnshaw ; Richard Sandiford
Cc: Christophe Lyon
Subject: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc
OK, thanks for Richard Sandiford.
Waiting for Richard Biener comment before commit.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 16:14
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V5] VECT: Add tree_code into "creat_iv" and allow it can
handle MINUS_EXPR IV
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 9:21 AM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
> Richard Earnshaw ; Richard Sandiford
>
> Subject: Re: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape
>
>
>
> On 5/10/23 16:52, Kyrylo Tkachov
On 5/11/23 10:23, Kyrylo Tkachov wrote:
-Original Message-
From: Christophe Lyon
Sent: Thursday, May 11, 2023 9:21 AM
To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
Richard Earnshaw ; Richard Sandiford
Subject: Re: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape
On 5/10/
Hi,
this patch allows mklog.py to be called with a commit hash directly.
So, instead of
git show | git gcc-mklog
git gcc-mklog --commit
can be used.
When no is given but --commit is specified, HEAD is used
instead. The behavior without --commit is the same as before.
Is that useful/OK?
Christophe Lyon writes:
> On 5/10/23 16:52, Kyrylo Tkachov wrote:
>>
>>
>>> -Original Message-
>>> From: Christophe Lyon
>>> Sent: Wednesday, May 10, 2023 2:31 PM
>>> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
>>> Richard Earnshaw ; Richard Sandiford
>>>
>>> Cc: Christophe Lyon
>>>
On Thu, May 11, 2023 at 4:23 AM Eugene Rozenfeld
wrote:
>
> I'm ok with disabling warnings as errors for autoprofiledbootstrap. What's
> the proper way to do that? Searching for "--disable-werror" I see matches in
> lib configure files but not in gcc files.
We have --with-build-config selecting
On Wed, 2023-05-10 at 22:02 +0200, Thomas Koenig wrote:
> On 10.05.23 21:29, Bernhard Reutner-Fischer via Fortran wrote:
> > On Mon, 27 Jun 2022 14:10:36 +0800
> > Xi Ruoyao wrote:
> >
> > > fgrep has been deprecated in favor of grep -F for a long time, and the
> > > next grep release (3.8 or 4.0
On Thu, 11 May 2023, Richard Sandiford wrote:
> juzhe.zh...@rivai.ai writes:
> > From: Juzhe-Zhong
> >
> > This is patch is a seperate patch preparing for supporting decrement IV.
> >
> > gcc/ChangeLog:
> >
> > * cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
> > * gi
From: Juzhe-Zhong
This is patching is adding basic vec_init support for RVV auto-vectorization.
This patch has been full coverage tested.
This patch makes vec_init support common init vector handling (using
vslide1down to insert element)
which can handle any cases of initialization vec but it's
From: Ju-Zhe Zhong
This patch is adding comments:
+/* Creates an induction variable with value BASE (+/-) STEP * iteration in
LOOP.
+ If INCR_OP is PLUS_EXPR, the induction variable is BASE + STEP * iteration.
+ If INCR_OP is MINUS_EXPR, the induction variable is BASE - STEP * iteration.
for
On 5/11/23 10:30, Richard Sandiford wrote:
Christophe Lyon writes:
On 5/10/23 16:52, Kyrylo Tkachov wrote:
-Original Message-
From: Christophe Lyon
Sent: Wednesday, May 10, 2023 2:31 PM
To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
Richard Earnshaw ; Richard Sandiford
Cc: Chris
On 5/5/23 17:10, Martin Jambor wrote:
Hello,
On Wed, Apr 26 2023, Aldy Hernandez via Gcc-patches wrote:
gcc/ChangeLog:
* ipa-cp.cc (ipa_vr_operation_and_type_effects): Convert to ranger API.
(ipa_value_range_from_jfunc): Same.
(propagate_vr_across_jump_function): Sam
Hi， Richard. Since create_iv has been approved and soon will be commited after
we bootstrap && regression.
Now, I plan to send patch for "decrement IV".
After reading your comments, I have several questions:
1.
>if (use_bias_adjusted_len)
> return rgl->bias_adjusted_ctrl;
> + else if
From: Lili Cui
Hi,
Those two patches each add a param to control the length of the chain with
FMA in reassoc pass and a tuning option in the backend.
Bootstrapped and regtested. Ok for trunk?
Regards
Lili.
Add a param for the chain with FMA in reassoc pass to make it more friendly to
the fma
From: Lili Cui
Set the length of the chain with FMA to 5 for icelake_cost.
With this patch applied,
SPR multi-copy: 508.namd_r increased by 3%
ICX multi-copy: 508.namd_r increased by 3.5%,
507.cactuBSSN_r increased by 3.7%
Using FMA instead of mult + add reduces register pressur
Changes from v1:
- Rebase against Juzhe's vec_series patch.
- Get rid of redundant scalar mode setting.
This patch adds basic binary integer operations support. It is based
on Michael Collison's work and makes use of the existing helpers in
riscv-c.cc. It introduces emit_nonvlmax_binop which
Changes from v1:
- Split into run tests (guarded by riscv_vector) and compile tests
which will be executed unconditionally. Doing dg-do run and -save-temps
on a non-supported target will not do anything at all.
This patchs adds scan as well as execution tests for vectorized
binary integer
Changes from v1:
- Change subject to RISC-V ;)
- Minor comment updates and rebasing.
This patch tries to improve the wrappers that emit either vlmax or
non-vlmax operations. Now, emit_len_op can be used to
emit a regular operation. Depending on whether a length != NULL
is passed either no VL
> "csr_operand" does seem wrong, though, as that just accepts constants.
> Maybe "arith_operand" is the way to go? I haven't looked at the
> V immediates though.
I was pondering changing the shift-count operand to QImode everywhere
but that indeed does not help code generation across the board.
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:27
To: Kito Cheng; Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
Subject: [PATCH v2] RISC-V: Add autovectorization tests for binary integer,
operations.
Ch
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:29
To: Kito Cheng; Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
Subject: [PATCH v2] RISC-V: Clarify vlmax and length handling.
Changes from v1:
- Change
LGTM. Plz commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:33
To: Palmer Dabbelt
CC: gcc-patches; juzhe.zhong; Kito Cheng; collison; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Split off shift patterns for autovectorization.
> "c
LGTM. You should commit it now. Then I can rebase vec_init patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:26
To: 钟居哲; gcc-patches; kito.cheng; Michael Collison; palmer; Jeff Law
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Add vectorized binops and insn_expander helpers.
Changes
> LGTM. You should commit it now. Then I can rebase vec_init patch.
Would need an ACK/OK from Kito at least :)
I just saw Kito has LGTM in V1 patch.
Let's wait for Kito LGTM for V2.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-11 18:36
To: juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; collison; palmer; jeffreyalaw
Subject: Re: [PATCH v2] RISC-V: Add vectorized binops and insn_expander helpers.
Passed the regression and bootstrap test in X86, will commit v6 as approved.
Pan
-Original Message-
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 11, 2023 5:39 PM
To: gcc-patches@gcc.gnu.org
Cc: Li, Pan2 ; Ju-Zhe Zhong
Subject: [PATCH V6] VECT: Add tree_code into "creat_iv" and allow
On Thu, May 11, 2023 at 12:13 PM Cui, Lili via Gcc-patches
wrote:
>
> From: Lili Cui
>
> Hi,
>
> Those two patches each add a param to control the length of the chain with
> FMA in reassoc pass and a tuning option in the backend.
>
> Bootstrapped and regtested. Ok for trunk?
>
> Regards
> Lili.
>
Thanks Richard Sandiford.
There is one interesting thing that the change from v4 to v5 (Aka, remove the
case and put dv as first arg) makes some ICE, will have a try for fixing.
Pan
-Original Message-
From: Richard Sandiford
Sent: Thursday, May 11, 2023 3:17 PM
To: Li, Pan2
Cc: gcc-p
On Thu, May 11, 2023 at 12:13 PM Cui, Lili via Gcc-patches
wrote:
>
> From: Lili Cui
>
> Set the length of the chain with FMA to 5 for icelake_cost.
>
> With this patch applied,
> SPR multi-copy: 508.namd_r increased by 3%
> ICX multi-copy: 508.namd_r increased by 3.5%,
> 507.cact
Christophe Lyon writes:
> On 5/11/23 10:30, Richard Sandiford wrote:
>> Christophe Lyon writes:
>>> On 5/10/23 16:52, Kyrylo Tkachov wrote:
> -Original Message-
> From: Christophe Lyon
> Sent: Wednesday, May 10, 2023 2:31 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo
"juzhe.zh...@rivai.ai" writes:
> Hi， Richard. Since create_iv has been approved and soon will be commited
> after
> we bootstrap && regression.
>
> Now, I plan to send patch for "decrement IV".
>
> After reading your comments, I have several questions:
>
> 1.
>>if (use_bias_adjusted_len)
>>
LGTM
juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:36 寫道：
> LGTM. Plz commit it now. Then I can rebase vec_init patch.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Robin Dapp
> Date: 2023-05-11 18:27
> To: Kito Cheng; Palmer Dabbelt
> CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
> Subject: [PATCH v2]
LGTM
juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:36 寫道：
> LGTM. Plz commit it now. Then I can rebase vec_init patch.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Robin Dapp
> Date: 2023-05-11 18:29
> To: Kito Cheng; Palmer Dabbelt
> CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw
> Subject: [PATCH v2]
From: Pan Li
This patch is going to be commited after bootstrap && regression on X86
PASSED.
Thanks Richards.
gcc/ChangeLog:
* cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
* gimple-loop-interchange.cc
(tree_loop_interchange::map_inductions_to_loop): Ditto
LGTM for v2 as well :)
juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:39 寫道：
> I just saw Kito has LGTM in V1 patch.
> Let's wait for Kito LGTM for V2.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Robin Dapp
> Date: 2023-05-11 18:36
> To: juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; collison; palmer;
> jef
Thanks, LGTM
juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:37 寫道：
> LGTM. Plz commit it now. Then I can rebase vec_init patch.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Robin Dapp
> Date: 2023-05-11 18:33
> To: Palmer Dabbelt
> CC: gcc-patches; juzhe.zhong; Kito Cheng; collison; jeffreyalaw; rdapp.gcc
>
Hi,
In r11-966-g9a182ef9ee011935d827ab5c6c9a7cd8e22257d8 we introduce a
simplification to emit_move_insn that attempts to simplify moves of the form:
(set (subreg:M1 (reg:M2 ...)) (constant C))
where M1 and M2 are of equal mode size. That is problematic for the splitter
vfp.md:no_literal_pool_df
Oh, I see. But I saw there is a variable using_partial_vectors_p
in the loop data structure.
Can I add a variable call using_select_vl_p ?
Since it may increase the size of data structure, I am not sure whether it is
appropriate.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 202
Thomas Schwinge writes:
> Hi!
>
> On 2023-04-14T13:49:20+0100, Gaius Mulley via Gcc-patches
> wrote:
>> Thomas Schwinge writes:
>>> Separately, given that plain 'autoreconf' works, why have 'autogen.sh' at
>>> all?
>>
>> If autoreconf does the same as autogen.sh then yes this can be removed
>
"juzhe.zh...@rivai.ai" writes:
> Oh, I see. But I saw there is a variable using_partial_vectors_p
> in the loop data structure.
>
> Can I add a variable call using_select_vl_p ?
Yeah. Please also add a wrapper macro like
LOOP_VINFO_USING_PARTIAL_VECTORS_P. (I'm not really a fan of the
wrappers,
The trunk patch for this PR corrected the ABI for enums that have
a defined underlying type. We shouldn't change the ABI on the branches
though, so this patch just removes the assertions that highlighed
the problem.
I think the same approach makes sense longer-term: keep the assertions
at maximum
Tested powerpc64le-linux (both -mabi={ibm,ieee}longdouble options) and
x86_64-linux.
Pushed to trunk.
-- >8 --
The current implementation of this non-standard overload of std::abs
incorrectly returns a negative value for negative NaNs and negative
zero, because x < 0 is false in both cases.
Use
Thanks. I have read rgroup descriptions again.
Still I am not fully understand it clearly, bear with me :)
I don't known how to differentiate Case 2 and Case 3.
Case 2 is multiple rgroup for SLP.
Case 3 is multiple rgroup for non-SLP (VEC_PACK_TRUNC)
Is it correct:
case 2: rgc->max_nscalarper_it
This patch adds the unary_widen_acc shape description.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_widen_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_widen_acc): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 34
Factorize vaddlvaq builtins so that they use parameterized names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn): Add vaddlva.
* config/arm/mve.md (mve_vaddlvaq_v4si): Rename into ...
(@mve_q_v4si): ... this.
(mve_vaddlvaq_p_v4si):
This patch adds the binary_acca_int32 shape description.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acca_int32): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc |
Factorize vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq builtins so
that they use parameterized names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VMLxLDAVxQ, MVE_VMLxLDAVxQ_P): New.
(mve_insn): Add vmlaldav, vmlaldavx, vmlsldav, vmlsldavx.
(su
Factorize vmladav, vmladavx, vmlsdav, vmlsdavx, vmladava, vmladavax,
vmlsdava, vmlsdavax builtins so that they use the same parameterized
names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VMLxDAVQ, MVE_VMLxDAVQ_P)
(MVE_VMLxDAVAQ, MVE_VMLxDAVAQ_P): Ne
On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
> On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
> libstd...@gcc.gnu.org> wrote:
>
> > This patch would avoid TSan false positives when using timed waiting
> > functions on mutexes and condvars, but as noted below, i
This patch adds the binary_acc_int32 shape description.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acc_int32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acc_int32): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 27 +
Implement vaddlvaq using the new MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vaddlvaq): New.
* config/arm/arm-mve-builtins-base.def (vaddlvaq): New.
* config/arm/arm-mve-builtins-base.h (vaddlvaq): New.
This patch adds the binary_acca_int64 shape description.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acca_int64): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acca_int64): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 3
Factorize vabavq builtins so that they use parameterized names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn): Add vabav.
* config/arm/mve.md (mve_vabavq_): Rename into ...
(@mve_q_): ... this,.
(mve_vabavq_p_): Rename into ...
Implement vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq using the new
MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm-mve-builtins-base.def (vmlal
Factorize vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqrdmladhq,
vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq builtins so that they use the
same parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VQxDMLxDHxQ_S): New.
(mve_insn): Add vqdmladh,
This patch adds the ternary_n shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_n): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_n): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 27 ++
Implement vmladavq, vmladavxq, vmlsdavq, vmlsdavxq using the new MVE
builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm-mve-builtins-base.def (vmladavq, vml
Factorize vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq
builtins so that they use the same parameterized names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVxQ, MVE_VRMLxLDAVHxQ_P):
New.
(mve_insn): Add vrmlaldavh, vrmlaldavhx,
This patch adds the binary_acc_int64 shape description.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acc_int64): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acc_int64): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 23 +
Implement vabavq using the new MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vabavq): New.
* config/arm/arm-mve-builtins-base.def (vabavq): New.
* config/arm/arm-mve-builtins-base.h (vabavq): New.
* config
Implement vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq vqdmladhq,
vqdmladhxq, vqdmlsdhq, vqdmlsdhxq using the new MVE builtins
framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vqdmladhq, vqdmladhxq)
(vqdmlsdhq, vqdmlsdhxq, vqrdmladhq
Factorize vmlaq_n, vmlasq_n, vqdmlahq_n, vqdmlashq_n, vqrdmlahq_n,
vqrdmlashq_n builtins so that they use the same parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VMLxQ_N): New.
(mve_insn): Add vmla, vmlas, vqdmlah, vqdmlash, vqrdmlah
This patch adds the ternary shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary): New.
* config/arm/arm-mve-builtins-shapes.h (ternary): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 26 +++
gcc
Implement vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq using the
new MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm-mve-builtins-base.de
Factorize vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq builtins so
that they use the same parameterized names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P):
New.
(mve_insn): Add vmlaldava, vmlaldavax, vmlslda
Implement vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq using
the new MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins
Implement vmladavaq, vmladavaxq, vmlsdavaq, vmlsdavaxq using the new
MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm-mve-builtins-base.def (vmlad
Implement vmlaq, vmlasq, vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq
using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaq, vmlasq, vqdmlahq)
(vqdmlashq, vqrdmlahq, vqrdmlashq): New.
* config/arm/arm-mv
From: Pan Li
The VMSET simplification RVV integer comparision has merged already.
This patch would like to update the comments for the cases that the
define_split will act on.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector.md: Add comments for simplifying to vmset.
Signed
ChangeLog:
* MAINTAINERS: Sort.
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c380bef5c5..e4dee76e2df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -521,7 +521,6 @@ James Lemke
Ilya Le
On Thu, 11 May 2023 at 13:19, Mike Crowe wrote:
> On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
> > On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
> > libstd...@gcc.gnu.org> wrote:
> >
> > > This patch would avoid TSan false positives when using timed waiting
>
"juzhe.zh...@rivai.ai" writes:
> Thanks. I have read rgroup descriptions again.
> Still I am not fully understand it clearly, bear with me :)
>
> I don't known how to differentiate Case 2 and Case 3.
>
> Case 2 is multiple rgroup for SLP.
> Case 3 is multiple rgroup for non-SLP (VEC_PACK_TRUNC)
>
> OK, you can go ahead commit patch. I am gonna send another patch to
> fix this.
I agree that we should handle more constants but I'd still rather go
ahead now and fix things later. The patch is more about the test
rather than the actual change anyway.
Jeff already ack'ed v1, maybe waiting for K
From: Pan Li
The decl_or_value is defined as void * before this PATCH. It will take
care of both the tree_node and rtx_def. Unfortunately, given a void
pointer cannot tell the input is tree_node or rtx_def.
Then we have some implicit structure layout requirement similar as
below. Or we will touc
Sorry for disturbing, fixed my silly mistake in PATCH v6 and passed x86
regression test. If no more concern, will commit after pass the x86 regression
test.
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, May 11, 2023 6:56 PM
To: Richard Sandiford
Cc: gcc-patches@gcc.gnu.org; ju
LGTM, thanks :)
On Thu, May 11, 2023 at 8:47 PM Robin Dapp wrote:
>
> > OK, you can go ahead commit patch. I am gonna send another patch to
> > fix this.
> I agree that we should handle more constants but I'd still rather go
> ahead now and fix things later. The patch is more about the test
> ra
On 5/11/23 04:33, Robin Dapp wrote:
"csr_operand" does seem wrong, though, as that just accepts constants.
Maybe "arith_operand" is the way to go? I haven't looked at the
V immediates though.
I was pondering changing the shift-count operand to QImode everywhere
but that indeed does not help
PR 109766 is an interesting case of large code being generated on x86_64,
caused by an interaction/conflict between register allocation and hardreg
cprop, that's tricky to fix/resolve within the middle-end.
The task/challenge is to push a DImode value in an SSE register on to
the stack, when opti
We accept this testcase since r13-806-g221acd67ca50f8.
PR c++/103807
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ1.C: New test.
---
gcc/testsuite/g++.dg/cpp2a/lambda-targ1.C | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/cpp2a/
On 5/11/23 02:29, Robin Dapp via Gcc-patches wrote:
Hi,
this patch allows mklog.py to be called with a commit hash directly.
So, instead of
git show | git gcc-mklog
git gcc-mklog --commit
can be used.
When no is given but --commit is specified, HEAD is used
instead. The behavior w
> From: "Roger Sayle"
> Date: Tue, 2 May 2023 00:37:14 +0100
> Jeff Law wrote:
> > This patch converts the xstormy16 patch to LRA. It introduces a code
> > quality regression in the shiftsi testcase, but it also fixes numerous
> > aborts/errors. IMHO it's a good tradeoff.
>
> I've investigat
While I was looking at differences before and after
r14-569-g21e2ef2dc25de3, I noticed that one phi node was
not being removed.
For an example, while compiling combine.cc, in expand_field_assignment,
we would remove `# pos_51 = PHI `
but we don't any more since pos_51 has more than zero users
but i
> -Original Message-
> From: Richard Biener
> Sent: Thursday, May 11, 2023 6:53 PM
> To: Cui, Lili
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 1/2] PR gcc/98350:Add a param to control the length of
> the chain with FMA in reassoc pass
Hi Richard,
Thanks for helping to review the
From: Lili Cui
Add a param for the chain with FMA in reassoc pass to make it more friendly to
the fma pass later. First to detect if this chain has ability to
generate more than 2 FMAs,if yes and param_reassoc_max_chain_length_with_fma
is enabled, We will rearrange the ops so that they can be com
Pushed to wwwdocs (better late than never).
-- >8 --
---
htdocs/gcc-13/changes.html | 14 ++
1 file changed, 14 insertions(+)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index bd022ed2..39414e18 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/cha
On Thu, May 11, 2023 at 5:21 AM Mike Crowe via Libstdc++ <
libstd...@gcc.gnu.org> wrote:
> On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
> > On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
> > libstd...@gcc.gnu.org> wrote:
> >
> > > This patch would avoid TSan fa
On Fri, 5 May 2023, Jonathan Wakely wrote:
>
>
> On Fri, 5 May 2023 at 10:43, Florian Weimer wrote:
> * Jonathan Wakely via Libstdc:
>
> > We could use strtod for a single-threaded target (i.e.
> > !defined(_GLIBCXX_HAS_GTHREADS) by changing the global locale using
> > s
On Thu, 11 May 2023 at 16:54, Thomas Rodgers wrote:
>
>
> On Thu, May 11, 2023 at 5:21 AM Mike Crowe via Libstdc++ <
> libstd...@gcc.gnu.org> wrote:
>
>> On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
>> > On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
>> > libs
> On May 10, 2023, at 9:15 AM, Jan Hubicka wrote:
>
>> Honza,
>>> Main motivation for this was profiling programs that contain specific
>>> code paths for different CPUs (such as graphics library in Firefox or Linux
>>> kernel). In the situation training machine differs from the machine
>>> pro
From: Ju-Zhe Zhong
1. Fix document description according Jeff && Richard.
2. Add LOOP_VINFO_USING_SELECT_VL_P for single rgroup.
3. Add LOOP_VINFO_USING_SLP_ADJUSTED_LEN_P for SLP multiple rgroup.
gcc/ChangeLog:
* doc/md.texi: Add seletc_vl pattern.
* internal-fn.def (SELECT_VL)
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/24] arm: [MVE intrinsics] factorize vaddlvaq
>
> Factorize vaddlvaq
On Thu, 11 May 2023 at 17:04, Patrick Palka wrote:
> On Fri, 5 May 2023, Jonathan Wakely wrote:
>
> >
> >
> > On Fri, 5 May 2023 at 10:43, Florian Weimer wrote:
> > * Jonathan Wakely via Libstdc:
> >
> > > We could use strtod for a single-threaded target (i.e.
> > > !defined(_GL
As of https://go.dev/cl/476695 the package golang.org/x/sys/unix
expects a syscall.prlimit function to exist. This libgo patch adds
that function. This is for https://go.dev/issue/46279 and
https://go.dev/issue/59712. Since this is a small patch and is needed
to compile the widely used x/sys/uni
> On May 11, 2023, at 11:05 AM, Hans-Peter Nilsson via Gcc-patches
> wrote:
>
> ...
> Yes, very interesting. Thank you for sharing this. I've
> seen regressions with LRA for CRIS too, for
> "double-register-sized" types, which for CRIS, a 32-bit
> target, translates to 64-bit types (DFmode
> Am 11.05.2023 um 17:18 schrieb Andrew Pinski via Gcc-patches
> :
>
> While I was looking at differences before and after
> r14-569-g21e2ef2dc25de3, I noticed that one phi node was
> not being removed.
> For an example, while compiling combine.cc, in expand_field_assignment,
> we would remov
"Roger Sayle" writes:
> An analysis of backend UNSPECs reveals that two of the most common UNSPECs
> across target backends are for copysign and bit reversal. This patch
> adds RTX codes for these expressions to allow their representation to
> be standardized, and them to optimized by the middle-
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