Factorize vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq builtins so
that they use the same parameterized names.
2022-10-25 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P):
New.
(mve_insn): Add vmlaldava, vmlaldavax, vmlsldava, vmlsldavax.
(supf): Add VMLALDAVAXQ_P_S, VMLALDAVAXQ_S, VMLSLDAVAQ_P_S,
VMLSLDAVAQ_S, VMLSLDAVAXQ_P_S, VMLSLDAVAXQ_S.
* config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
(mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>)
(mve_vmlaldavaxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlaldavaq_p_<supf><mode>, mve_vmlaldavaxq_p_<supf><mode>)
(mve_vmlsldavaq_p_s<mode>, mve_vmlsldavaxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 28 +++++++++
gcc/config/arm/mve.md | 121 +++++-------------------------------
2 files changed, 42 insertions(+), 107 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 729127d8586..7a88bc91182 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -741,6 +741,20 @@ (define_int_iterator MVE_VMLxLDAVxQ_P [
VMLSLDAVXQ_P_S
])
+(define_int_iterator MVE_VMLxLDAVAxQ [
+ VMLALDAVAQ_S VMLALDAVAQ_U
+ VMLALDAVAXQ_S
+ VMLSLDAVAQ_S
+ VMLSLDAVAXQ_S
+ ])
+
+(define_int_iterator MVE_VMLxLDAVAxQ_P [
+ VMLALDAVAQ_P_S VMLALDAVAQ_P_U
+ VMLALDAVAXQ_P_S
+ VMLSLDAVAQ_P_S
+ VMLSLDAVAXQ_P_S
+ ])
+
(define_int_iterator MVE_VRMLxLDAVxQ [
VRMLALDAVHQ_S VRMLALDAVHQ_U
VRMLALDAVHXQ_S
@@ -883,6 +897,10 @@ (define_int_attr mve_insn [
(VMLADAVQ_S "vmladav") (VMLADAVQ_U "vmladav")
(VMLADAVXQ_P_S "vmladavx")
(VMLADAVXQ_S "vmladavx")
+ (VMLALDAVAQ_P_S "vmlaldava") (VMLALDAVAQ_P_U "vmlaldava")
+ (VMLALDAVAQ_S "vmlaldava") (VMLALDAVAQ_U "vmlaldava")
+ (VMLALDAVAXQ_P_S "vmlaldavax")
+ (VMLALDAVAXQ_S "vmlaldavax")
(VMLALDAVQ_P_S "vmlaldav") (VMLALDAVQ_P_U "vmlaldav")
(VMLALDAVQ_S "vmlaldav") (VMLALDAVQ_U "vmlaldav")
(VMLALDAVXQ_P_S "vmlaldavx")
@@ -897,6 +915,10 @@ (define_int_attr mve_insn [
(VMLSDAVQ_S "vmlsdav")
(VMLSDAVXQ_P_S "vmlsdavx")
(VMLSDAVXQ_S "vmlsdavx")
+ (VMLSLDAVAQ_P_S "vmlsldava")
+ (VMLSLDAVAQ_S "vmlsldava")
+ (VMLSLDAVAXQ_P_S "vmlsldavax")
+ (VMLSLDAVAXQ_S "vmlsldavax")
(VMLSLDAVQ_P_S "vmlsldav")
(VMLSLDAVQ_S "vmlsldav")
(VMLSLDAVXQ_P_S "vmlsldavx")
@@ -2351,6 +2373,12 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VRMLSLDAVHQ_S "s")
(VRMLSLDAVHXQ_P_S "s")
(VRMLSLDAVHXQ_S "s")
+ (VMLALDAVAXQ_P_S "s")
+ (VMLALDAVAXQ_S "s")
+ (VMLSLDAVAQ_P_S "s")
+ (VMLSLDAVAQ_S "s")
+ (VMLSLDAVAXQ_P_S "s")
+ (VMLSLDAVAXQ_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index e2259aa48e9..c6fd634b5c0 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2550,34 +2550,21 @@ (define_insn "@mve_<mve_insn>q_p_f<mode>"
(set_attr "length""8")])
;;
-;; [vmlaldavaq_s, vmlaldavaq_u])
+;; [vmlaldavaq_s, vmlaldavaq_u]
+;; [vmlaldavaxq_s]
+;; [vmlsldavaq_s]
+;; [vmlsldavaxq_s]
;;
-(define_insn "mve_vmlaldavaq_<supf><mode>"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:MVE_5 3 "s_register_operand" "w")]
- VMLALDAVAQ))
- ]
- "TARGET_HAVE_MVE"
- "vmlaldava.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlaldavaxq_s])
-;;
-(define_insn "mve_vmlaldavaxq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:MVE_5 3 "s_register_operand" "w")]
- VMLALDAVAXQ_S))
+ MVE_VMLxLDAVAxQ))
]
"TARGET_HAVE_MVE"
- "vmlaldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -2600,38 +2587,6 @@ (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vmlsldavaq_s])
-;;
-(define_insn "mve_vmlsldavaq_s<mode>"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:MVE_5 3 "s_register_operand" "w")]
- VMLSLDAVAQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlsldavaxq_s])
-;;
-(define_insn "mve_vmlsldavaxq_s<mode>"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:MVE_5 3 "s_register_operand" "w")]
- VMLSLDAVAXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vmovlbq_m_u, vmovlbq_m_s])
;; [vmovltq_m_u, vmovltq_m_s])
@@ -3336,36 +3291,22 @@ (define_insn "mve_vhcaddq_rot90_m_s<mode>"
(set_attr "length""8")])
;;
-;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
+;; [vmlaldavaq_p_u, vmlaldavaq_p_s]
+;; [vmlaldavaxq_p_s]
+;; [vmlsldavaq_p_s]
+;; [vmlsldavaxq_p_s]
;;
-(define_insn "mve_vmlaldavaq_p_<supf><mode>"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:MVE_5 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLALDAVAQ_P))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmlaldavaxq_p_s])
-;;
-(define_insn "mve_vmlaldavaxq_p_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:MVE_5 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLALDAVAXQ_P))
+ MVE_VMLxLDAVAxQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3432,40 +3373,6 @@ (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vmlsldavaq_p_s])
-;;
-(define_insn "mve_vmlsldavaq_p_s<mode>"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:MVE_5 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLSLDAVAQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmlsldavaxq_p_s])
-;;
-(define_insn "mve_vmlsldavaxq_p_s<mode>"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:MVE_5 2 "s_register_operand" "w")
- (match_operand:MVE_5 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLSLDAVAXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmullbq_poly_m_p])
;;
--
2.34.1
