Factorize vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqrdmladhq,
vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq builtins so that they use the
same parameterized names.
2022-12-12 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VQxDMLxDHxQ_S): New.
(mve_insn): Add vqdmladh, vqdmladhx, vqdmlsdh, vqdmlsdhx,
vqrdmladh, vqrdmladhx, vqrdmlsdh, vqrdmlsdhx.
(supf): Add VQDMLADHQ_S, VQDMLADHXQ_S, VQDMLSDHQ_S, VQDMLSDHXQ_S,
VQRDMLADHQ_S,VQRDMLADHXQ_S, VQRDMLSDHQ_S, VQRDMLSDHXQ_S.
* config/arm/mve.md (mve_vqrdmladhq_s<mode>)
(mve_vqrdmladhxq_s<mode>, mve_vqrdmlsdhq_s<mode>)
(mve_vqrdmlsdhxq_s<mode>, mve_vqdmlsdhxq_s<mode>)
(mve_vqdmlsdhq_s<mode>, mve_vqdmladhxq_s<mode>)
(mve_vqdmladhq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 27 ++++++++
gcc/config/arm/mve.md | 127 ++++--------------------------------
2 files changed, 38 insertions(+), 116 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 7a88bc91182..c23ca7361c1 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -755,6 +755,17 @@ (define_int_iterator MVE_VMLxLDAVAxQ_P [
VMLSLDAVAXQ_P_S
])
+(define_int_iterator MVE_VQxDMLxDHxQ_S [
+ VQDMLADHQ_S
+ VQDMLADHXQ_S
+ VQDMLSDHQ_S
+ VQDMLSDHXQ_S
+ VQRDMLADHQ_S
+ VQRDMLADHXQ_S
+ VQRDMLSDHQ_S
+ VQRDMLSDHXQ_S
+ ])
+
(define_int_iterator MVE_VRMLxLDAVxQ [
VRMLALDAVHQ_S VRMLALDAVHQ_U
VRMLALDAVHXQ_S
@@ -948,11 +959,15 @@ (define_int_attr mve_insn [
(VQADDQ_N_S "vqadd") (VQADDQ_N_U "vqadd")
(VQADDQ_S "vqadd") (VQADDQ_U "vqadd")
(VQDMLADHQ_M_S "vqdmladh")
+ (VQDMLADHQ_S "vqdmladh")
(VQDMLADHXQ_M_S "vqdmladhx")
+ (VQDMLADHXQ_S "vqdmladhx")
(VQDMLAHQ_M_N_S "vqdmlah")
(VQDMLASHQ_M_N_S "vqdmlash")
(VQDMLSDHQ_M_S "vqdmlsdh")
+ (VQDMLSDHQ_S "vqdmlsdh")
(VQDMLSDHXQ_M_S "vqdmlsdhx")
+ (VQDMLSDHXQ_S "vqdmlsdhx")
(VQDMULHQ_M_N_S "vqdmulh")
(VQDMULHQ_M_S "vqdmulh")
(VQDMULHQ_N_S "vqdmulh")
@@ -968,11 +983,15 @@ (define_int_attr mve_insn [
(VQNEGQ_M_S "vqneg")
(VQNEGQ_S "vqneg")
(VQRDMLADHQ_M_S "vqrdmladh")
+ (VQRDMLADHQ_S "vqrdmladh")
(VQRDMLADHXQ_M_S "vqrdmladhx")
+ (VQRDMLADHXQ_S "vqrdmladhx")
(VQRDMLAHQ_M_N_S "vqrdmlah")
(VQRDMLASHQ_M_N_S "vqrdmlash")
(VQRDMLSDHQ_M_S "vqrdmlsdh")
+ (VQRDMLSDHQ_S "vqrdmlsdh")
(VQRDMLSDHXQ_M_S "vqrdmlsdhx")
+ (VQRDMLSDHXQ_S "vqrdmlsdhx")
(VQRDMULHQ_M_N_S "vqrdmulh")
(VQRDMULHQ_M_S "vqrdmulh")
(VQRDMULHQ_N_S "vqrdmulh")
@@ -2379,6 +2398,14 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VMLSLDAVAQ_S "s")
(VMLSLDAVAXQ_P_S "s")
(VMLSLDAVAXQ_S "s")
+ (VQDMLADHQ_S "s")
+ (VQDMLADHXQ_S "s")
+ (VQDMLSDHQ_S "s")
+ (VQDMLSDHXQ_S "s")
+ (VQRDMLADHQ_S "s")
+ (VQRDMLADHXQ_S "s")
+ (VQRDMLSDHQ_S "s")
+ (VQRDMLSDHXQ_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index c6fd634b5c0..bf4d18455fe 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2051,34 +2051,25 @@ (define_insn "mve_vqdmlashq_n_<supf><mode>"
])
;;
-;; [vqrdmladhq_s])
+;; [vqdmladhq_s]
+;; [vqdmladhxq_s]
+;; [vqdmlsdhq_s]
+;; [vqdmlsdhxq_s]
+;; [vqrdmladhq_s]
+;; [vqrdmladhxq_s]
+;; [vqrdmlsdhq_s]
+;; [vqrdmlsdhxq_s]
;;
-(define_insn "mve_vqrdmladhq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQRDMLADHQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqrdmladhxq_s])
-;;
-(define_insn "mve_vqrdmladhxq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")]
- VQRDMLADHXQ_S))
+ MVE_VQxDMLxDHxQ_S))
]
"TARGET_HAVE_MVE"
- "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ "<mve_insn>.s%#<V_sz_elem>\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -2114,38 +2105,6 @@ (define_insn "mve_vqrdmlashq_n_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqrdmlsdhq_s])
-;;
-(define_insn "mve_vqrdmlsdhq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQRDMLSDHQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqrdmlsdhxq_s])
-;;
-(define_insn "mve_vqrdmlsdhxq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQRDMLSDHXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqrshlq_m_n_s, vqrshlq_m_n_u]
;; [vrshlq_m_n_s, vrshlq_m_n_u]
@@ -2228,70 +2187,6 @@ (define_insn "mve_vsriq_n_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqdmlsdhxq_s])
-;;
-(define_insn "mve_vqdmlsdhxq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQDMLSDHXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqdmlsdhq_s])
-;;
-(define_insn "mve_vqdmlsdhq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQDMLSDHQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqdmladhxq_s])
-;;
-(define_insn "mve_vqdmladhxq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQDMLADHXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqdmladhq_s])
-;;
-(define_insn "mve_vqdmladhq_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VQDMLADHQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vabsq_m_f]
;; [vnegq_m_f]
--
2.34.1
