Date: 2023-07-27 17:57
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Enable basic VLS modes support
Hmmm, does it mean we'll have (set (mem) (mem)) after legitimize_move???
Or maybe try to
use define_insn_and_split rathe
ds[0], operands[1]);
gcc_assert (ok_p);
DONE;
}
)
Is it reasonable to you?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-27 17:57
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Enable basic VLS modes support
Hmm
gs
>
>
> It seems that we need a placeholder pattern to hold mem->mem ?
>
> Could you help me with that ?
>
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-07-27 17:19
> To: Juzhe-Zhong
> CC: gcc-patches; kito.che
4]+0 S8 A64])
(mem/u/c:V8QI (reg/f:DI 185) [0 S8 A64])) "auto.c":11:20 -1
(nil))
during RTL pass: vregs
dump file: auto.c.259r.vregs
It seems that we need a placeholder pattern to hold mem->mem ?
Could you help me with that ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date:
Last minor thing :)
> +(define_insn_and_split "*mov"
> + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> + (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> + "TARGET_VECTOR"
Reject (set (mem) (mem)) by adding the check:
TARGET_VECTOR
&& (registe
