Hi, kito.
I tried to reject mem->mem in this pattern:
(define_insn_and_split "*mov<mode>"
[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
(match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
"TARGET_VECTOR
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
"@
#
#
vmv%m1r.v\t%0,%1"
"&& reload_completed
&& (!register_operand (operands[0], <MODE>mode)
|| !register_operand (operands[1], <MODE>mode))"
[(const_int 0)]
{
bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
gcc_assert (ok_p);
DONE;
}
)
It cause ICE in regression during "vregs" (Before RA).
[jzzhong@server1:/work/home/jzzhong/work/insn]$~/work/rvv-opensource/output/gcc-rv64/bin/riscv64-rivai-elf-gcc
-march=rv64gc_zve32f -mabi=lp64d -O3 -S
--param=riscv-autovec-preference=scalable -fdump-rtl-all auto.c
auto.c: In function 'foo0':
auto.c:15:1: error: unrecognizable insn:
15 | }
| ^
(insn 35 34 36 6 (set (mem:V8QI (reg/f:DI 154 [ _64 ]) [0 MEM <vector(8) signed
char> [(int8_t *)_64]+0 S8 A64])
(mem/u/c:V8QI (reg/f:DI 185) [0 S8 A64])) "auto.c":11:20 -1
(nil))
during RTL pass: vregs
dump file: auto.c.259r.vregs
It seems that we need a placeholder pattern to hold mem->mem ?
Could you help me with that ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-27 17:19
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Enable basic VLS modes support
Last minor thing :)
> +(define_insn_and_split "*mov<mode>"
> + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> + (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> + "TARGET_VECTOR"
Reject (set (mem) (mem)) by adding the check:
TARGET_VECTOR
&& (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
|| register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
