Denis Chertykov wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off per default)
[ ] Set it on per default
As soon as the direction is clear, I'll post a follow-up patch to
add the mis
On 11/22/2011 01:15 AM, Georg-Johann Lay wrote:
ldi r30,lo8(1) ; 25*movqi/2[length = 1]
cp r10,r18 ; 26*cmpqi/2[length = 1]
brlo .L2 ; 27branch[length = 1]
ldi r30,lo8(0) ; 28*movqi/1[length = 1]
.L2:
add r11,r19 ;
2011/11/30 Weddington, Eric :
>
>
>> -Original Message-
>> From: Richard Henderson
>> Sent: Tuesday, November 29, 2011 11:30 AM
>> To: Georg-Johann Lay
>> Cc: gcc-patches@gcc.gnu.org; Denis Chertykov; Weddington, Eric;
> Anatoly
>> Sokolov
&g
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, November 29, 2011 11:30 AM
> To: Georg-Johann Lay
> Cc: gcc-patches@gcc.gnu.org; Denis Chertykov; Weddington, Eric;
Anatoly
> Sokolov
> Subject: Re: [Patch,AVR] Light-weight DImode implementation.
>
On 11/29/2011 10:11 AM, Georg-Johann Lay wrote:
> The only question that remains is what the -m64 option should be like?
>
> [ ] Omit it altogether
> [ ] Leave it as is (off per default)
> [ ] Set it on per default
>
> As soon as the direction is clear, I'll post a follow-up patch to add the
> mi
Richard Henderson wrote:
> On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
>> ;; The caveat is that if there are insns for some mode, there must also be a
>> ;; respective move insn that describes reloads. Therefore, this
>> ;; implementation uses an accumulator-based model with two hard-coded,
>>
Richard Henderson schrieb:
On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
;; The caveat is that if there are insns for some mode, there must also be a
;; respective move insn that describes reloads. Therefore, this
;; implementation uses an accumulator-based model with two hard-coded,
;; accu
On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
> ;; The caveat is that if there are insns for some mode, there must also be a
> ;; respective move insn that describes reloads. Therefore, this
> ;; implementation uses an accumulator-based model with two hard-coded,
> ;; accumulator-like registers
