Richard Henderson wrote: > On 11/21/2011 11:31 AM, Georg-Johann Lay wrote: >> ;; The caveat is that if there are insns for some mode, there must also be a >> ;; respective move insn that describes reloads. Therefore, this >> ;; implementation uses an accumulator-based model with two hard-coded, >> ;; accumulator-like registers >> ;; >> ;; A[] = reg:DI 18 >> ;; B[] = reg:DI 10 >> ;; >> ;; so that no DImode insn contains pseudos or needs reloading. >
> Well, rtl loop optimization will not work, but given that SSE optimizations > ought to have been performed, that's probably acceptable. > > It's definitely a hack, but perhaps you'll be able to get away with it. If I understand you correctly, it is "unconventional but safe". So the question is how to proceed with this patch. The only question that remains is what the -m64 option should be like? [ ] Omit it altogether [ ] Leave it as is (off per default) [ ] Set it on per default As soon as the direction is clear, I'll post a follow-up patch to add the missing bits like, e.g., documentation for the new switch. Johann http://gcc.gnu.org/ml/gcc-patches/2011-11/msg02136.html
