When I last worked on fusion, I put a bunch of support to save the insn code of
various functions for creating fusion. I never actually used these functions,
except printing them out with -mdebug=reg. This patch deletes the generator
functions for the insns, but it does not delete the actual insn
This is the last of the infrastructure patches that I have currently done.
This adds a new reg_addr flag to note whether the d-form address is a ds-form
(bottom 2 bits must be 0). At present, nothing uses this, but I have plans for
it in the future.
2018-03-22 Michael Meissner
* confi
In preparing to start work on reorganizing the intermediate address support in
PowerPC, I noticed there were some thinkos in the undocumented toc fusion.
There are three problems with toc fusion. Now, as I start reworking the
address support in general, toc fusion and power9 fusion will likely be
On Thu, Mar 22, 2018 at 11:41:48AM -0500, Segher Boessenkool wrote:
> On Thu, Mar 22, 2018 at 11:18:05AM -0400, Michael Meissner wrote:
> > On Thu, Mar 22, 2018 at 10:03:55AM -0500, Segher Boessenkool wrote:
> > > > callers to pass in the RELOAD_REG_VMX class explicitly.
> > > > (rs
On Thu, Mar 22, 2018 at 11:18:05AM -0400, Michael Meissner wrote:
> On Thu, Mar 22, 2018 at 10:03:55AM -0500, Segher Boessenkool wrote:
> > > callers to pass in the RELOAD_REG_VMX class explicitly.
> > > (rs6000_secondary_reload): Likewise.
> > > (rs6000_preferred_reload_class): Likewise.
> >
Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point regist
Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point regist
Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point regist
Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point regist
Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point regist
On Thu, Mar 22, 2018 at 10:03:55AM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Mar 22, 2018 at 08:16:36AM -0400, Michael Meissner wrote:
> > This match renames the d-form mode support function and makes it more
> > general.
> > It was originally written to test whether we have the ISA 3.0
Hi!
On Thu, Mar 22, 2018 at 08:16:36AM -0400, Michael Meissner wrote:
> This match renames the d-form mode support function and makes it more general.
> It was originally written to test whether we have the ISA 3.0 new D*-form
> instruction, but I believe in the future, I will want to use it also
Hi Mike,
On Thu, Mar 22, 2018 at 08:11:52AM -0400, Michael Meissner wrote:
> This patch renames the mode_supports_vsx_dform_quad function and changes all
> of
> the callers. I'm thinking about enhancing the addressing parts in the
> secondary reload support, and I wanted a more logical naming sc
This patch extends the other mode_supports* function to take an optional
second argument to specificy particular reload register class, and it defaults
to REG_RELOAD_ANY which says some reload register supports the feature.
I have built bootstrap compilers with the first 4 patches including this p
This match renames the d-form mode support function and makes it more general.
It was originally written to test whether we have the ISA 3.0 new D*-form
instruction, but I believe in the future, I will want to use it also for GPR
and tradiational floating point registers.
I have built bootstrap co
This patch just moves two of the mode_supports_* functions so they are all
together.
I have built bootstrap compilers with the first 4 patches including this patch
on both big and little endian power8 systems. There were no regressions.
2018-03-21 Michael Meissner
* config/rs6000/rs6
This patch renames the mode_supports_vsx_dform_quad function and changes all of
the callers. I'm thinking about enhancing the addressing parts in the
secondary reload support, and I wanted a more logical naming scheme. There
will be mode_supports_d_form for offsettable addresses of any form, and
I will be submitting reworked patches for the stuff I want to do in GCC 9. The
initial patches are mostly initial cleanup and slight rework of the support
functions. These patches will be limited to changing one thing at a time,
instead of larger patches like I did in the first set of patches.
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