Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.
I have done both big and little endian bootstrap builds with all 5 patches
installed. There were no regressions.
2018-03-22 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
Reformat alternatives and attributes so it is easier to identify
which constraints/attributes go with which instruction.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 258733)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -7441,16 +7441,25 @@ (define_insn "*mov<mode>_hardfloat32"
4, 4, 4, 4, 8,
8, 8, 8")])
+;; STW LWZ MR G-const H-const F-const
+
(define_insn "*mov<mode>_softfloat32"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
- (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+ "=Y, r, r, r, r, r")
+
+ (match_operand:FMOVE64 1 "input_operand"
+ "r, Y, r, G, H, F"))]
+
"! TARGET_POWERPC64
&& (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT)
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
- [(set_attr "type" "store,load,two,*,*,*")
- (set_attr "length" "8,8,8,8,12,16")])
+ [(set_attr "type"
+ "store, load, two, *, *, *")
+
+ (set_attr "length"
+ "8, 8, 8, 8, 12, 16")])
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
