lgtm Replied Message Fromyanzhang.w...@intel.comDate01/25/2024 21:06 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,kito.ch...@sifive.com,pan2...@intel.com,yanzhang.w...@intel.comSubject[PATCH v2] RISC-V: remove param riscv-vector-abi. [PR113538]
VLA is a known issue for a long time.GCC doesn't have too much cse optimization forVLA vectors. It should be a big work to investigate what's going on.I think most cse optimization for precomputed result are vls loop. So I think as long as we can do a good job on cost model which pick appropriate v
s"
> 抄 送："jim.wilson.gcc"; palmer; andrew; "philipp.tomsich"; "Christoph Müllner"; jinma; Cooper Qu
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> This is Ok from my side.
> But before
ok Replied Message FromLi XuDate12/19/2023 13:31 Togcc-patches@gcc.gnu.org Cckito.ch...@gmail.com,pal...@dabbelt.com,juzhe.zh...@rivai.ai,xuliSubject[PATCH] testsuite: Fix dump checks under different riscv-sim for RVV.
lgtm Replied Message FromLi XuDate12/18/2023 09:04 Togcc-patches@gcc.gnu.org Cckito.ch...@gmail.com,pal...@dabbelt.com,juzhe.zh...@rivai.aiSubject[PATCH] RISC-V: Add viota missed avl_type attribute
lgtm. Replied Message Frompan2...@intel.comDate12/18/2023 08:22 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Fix POLY INT handle bug
lgtm from my side. But I'd like to see Robin's commentsThanks Replied Message Frompan2...@intel.comDate12/13/2023 21:49 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,rdapp@gmail.comSubject[PATCH v1] RISC-V: Refine test cases for both PR112929 and PR112988
OK. will add it later. Replied Message FromRobin DappDate12/13/2023 20:23 Tojuzhe.zhong Ccrdapp@gmail.com,gcc-patches@gcc.gnu.org,kito.ch...@gmail.com,kito.ch...@sifive.com,jeffreya...@gmail.comSubjectRe: [PATCH] RISC-V: Postpone full available optimization [VSETVL PASS]> Do you mean ad
Do you mean add some comments in tests？ Replied Message FromRobin DappDate12/13/2023 20:16 Tojuzhe.zhong Ccrdapp@gmail.com,gcc-patches@gcc.gnu.org,kito.ch...@gmail.com,kito.ch...@sifive.com,jeffreya...@gmail.comSubjectRe: [PATCH] RISC-V: Postpone full available optimization [VSETVL PASS
I don”t choose to run since I didn”t have issue run on my local simulator no matter qemu or spike.So it”s better to check vsetvl asm.full available is not consistent between LCM analysis and earliest fusion，so it”s safe to postpone it. Replied Message FromRobin DappDate12/13/2023 20:08 ToJu
lgtm. Replied Message FromRobin DappDate12/11/2023 21:40 Togcc-patches,palmer,Kito Cheng,jeffreyalaw,juzhe.zh...@rivai.ai,Li, Pan2 Ccrdapp@gmail.comSubject[PATCH] RISC-V: testsuite: Fix strcmp-run.c test.Hi,
this fixes expectations in the strcmp-run test which would sometimes
fail with
Yes. We can defer it Thanks richard. Replied Message FromRichard BienerDate11/30/2023 20:19 Tojuzhe.zh...@rivai.ai Cctamar.christina,gcc-patchesSubjectRe: RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit codeOn Thu, Nov 30, 2023 at 12:11 PM juzhe.zh...@rivai
committed as it passed zvl128/256/512/1024 no regression. Replied Message FromJuzhe-ZhongDate11/27/2023 21:24 Togcc-patches@gcc.gnu.org Cckito.ch...@gmail.com,kito.ch...@sifive.com,jeffreya...@gmail.com,rdapp@gmail.com,Juzhe-ZhongSubject[PATCH] RISC-V: Fix VSETVL PASS regression
ok Replied Message FromRobin DappDate11/21/2023 21:35 Togcc-patches,palmer,Kito Cheng,jeffreyalaw,juzhe.zh...@rivai.ai Ccrdapp@gmail.comSubjectRe: [PATCH] RISC-V: testsuite: Fix popcount test.> Mhm, not so obvious after all. We vectorize 250 instances with
> rv32gcv, 229 with rv64gcv a
lgtm Replied Message Frompan2...@intel.comDate11/10/2023 14:22 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Support vec_init for trailing same element
lgtm Replied Message FromLehua DingDate11/08/2023 21:27 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,kito.ch...@gmail.com,rdapp@gmail.com,pal...@rivosinc.com,jeffreya...@gmail.com,lehua.d...@rivai.aiSubject[PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl
Not sure who is maintaining this branch. I always developing on the master. CCing to other riscv folks Replied Message FromMaxim BlinovDate11/06/2023 21:13 ToRichard Biener Ccgcc-patches@gcc.gnu.org,juzhe.zh...@rivai.ai,maxim.bli...@imgtec.comSubjectRe: [PATCH] RISC-V: VECT: Remember to as
OK。will add it. Replied Message FromKito ChengDate11/06/2023 20:46 Tojuzhe.zh...@rivai.ai Cckito.cheng,gcc-patches,jeffreyalaw,Robin DappSubjectRe: Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 systemI would prefer to add a dedicated test case to test that, so that we
could
lgtm Replied Message Frompan2...@intel.comDate11/05/2023 17:30 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec
lgtm Replied Message Frompan2...@intel.comDate11/02/2023 19:48 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator
lgtm Replied Message Frompan2...@intel.comDate10/13/2023 13:33 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Add test for FP iroundf auto vectorization
I am working on it. Currently, we have about 50+ additional FAILs after enabling vectorization.some of them need fixed on middle-end. E.g richard fixed a missed cse optimization.Some need fix on test case.I am analyzing each fail one by one.I prefer postpone this patch since it will cause some add
Do you mean add a check whether it is vectorized or not？Sounds reasonable， I can add that in another patch. Replied Message FromJeff LawDate10/09/2023 21:51 ToJuzhe-Zhong,gcc-patches@gcc.gnu.org Ccrguent...@suse.deSubjectRe: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV
On
ok Replied Message Frompan2...@intel.comDate09/22/2023 11:47 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Rename the test macro for math autovec test
LGTM Replied Message FromLehua DingDate09/20/2023 13:39 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,kito.ch...@gmail.com,rdapp@gmail.com,pal...@rivosinc.com,jeffreya...@gmail.com,lehua.d...@rivai.aiSubject[PATCH] RISC-V: Fixed ICE caused by missing operand
From: Richard Sandiford
Date: 2023-07-12 17:33
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; jeffreyalaw; gcc-patches; Kito.cheng; Robin Dapp
Subject: Re: [PATCH V5] RISC-V: Support gather_load/scatter RVV
auto-vectorization
Richard Biener writes:
> On Wed, 12 Jul 2023, juzhe.zh...@rivai.ai wr
(reg:QI s0)
(reg:DI s0))
The "avl" operand rtx = (reg:DI s0)
count_occurrences return 1 however the actual regno occurrences should be 2.
Thanks
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-19 03:00
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re:
Yes, like kito said.
We won't enable VNx1DImode in auto-vectorization so it's meaningless to fix it
here.
We dynamic adjust the minimum vector-length for different '-march' according to
RVV ISA specification.
So we strongly suggest that we should drop this fix.
Thanks.
juzhe.zh...@rivai.ai
F
the loop,
then eliminate the vsetvl of this block. (Branch prediction is not that perfect
in VSETVL PASS, I plan to
optimize more when GCC 14 is open).
"f2" function is the normal fuse that we do in Phase 3.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-12 05:14
To: Richard Bi
Another feasible solution: Maybe we can drop supporting segment intrinsics
in upstream GCC.
We let the downstream companies support segment in their own downstream GCC ?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-11 04:42
To: juzhe.zhong; jakub
CC: gcc-patches; kito.cheng; palmer
e.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-11 04:36
To: Jakub Jelinek
CC: juzhe.zhong; gcc-patches; kito.cheng; palmer; richard.sandiford; rguenther
Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to
16-bit
On 4/10/23 09:18, Jakub Jelinek wrote:
> On Mon, Ap
m: Jakub Jelinek
Date: 2023-04-10 23:18
To: Jeff Law
CC: juzhe.zhong; gcc-patches; kito.cheng; palmer; richard.sandiford; rguenther
Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to
16-bit
On Mon, Apr 10, 2023 at 08:54:12AM -0600, Jeff Law wrote:
> This is likely going
explodes.
As well as tuples types in RVV much more than aarch64.
Maybe we need to ask RVV api doc maintainer to reduce types && api of RVV?
Not sure.
I think kito may help for this.
juzhe.zh...@rivai.ai
From: Jakub Jelinek
Date: 2023-04-10 23:18
To: Jeff Law
CC: juzhe.zhong; gcc
like UQQmode, HQQmode, Not sure maybe we can reduce these scalar modes to
make total machine modes less than 256?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-10 22:54
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer; jakub; richard.sandiford; rguenther
Subject: Re: [PATCH] machine_mode
.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-10 22:54
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer; jakub; richard.sandiford; rguenther
Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to
16-bit
On 4/10/23 08:48, juzhe.zh...@rivai.ai wrote:
> From: Juzhe
bad comments in the codes. Currently, I am working on the first patch
of auto-vectorization. After I sent the first patch of auto-vectorization for
you to
review. I would like to re-check all the comments and code style of VSETVL PASS.
And refine them.
juzhe.zh...@rivai.ai
From: Jeff Law
Date
issue
when I start to implement VSETVL PASS.
I leaved it to be fixed after I finished all target GCC 13 features. And Kito
postpone this patch to be merged after GCC 14 is open.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-03 03:41
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subje
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-03-28 22:26
To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong;
jeffreyalaw
CC: Kito Cheng
Subject: [PATCH] RISC-V: Define __riscv_v_intrinsic [PR109312]
RVV intrinsic has defined a macro to identity the version of
nce you can see "vd" to match "vm", vd doesn't include mask register (v0).
This trivial optimization can allow our RA have 1 more register to allocate.
It's overall beneficial to the RA.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-03-15 02:05
To: juzhe.
Address comment and fix it in this V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613608.html
juzhe.zh...@rivai.ai
From: Bernhard Reutner-Fischer
Date: 2023-03-09 05:16
To: juzhe.zhong; gcc-patches
CC: kito.cheng; Ju-Zhe Zhong
Subject: Re: [PATCH] RISC-V: Add fault first load
>> This series of patches adds foundational support for RISC-V
>> autovectorization. These patches are based on the current upstream rvv
>> vector intrinsic support and is not a new implementation. Most of the
>> implementation consists of adding the new vector cost model, the
>> autovectorizat
as long as we can emit appropriate vsetvl + vlm/vsm, it's totally fine
for RVV even though in some case, their memory allocation
is not accurate in compiler.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-02 00:14
To: Li\, Pan2
CC: juzhe.zhong\@rivai.ai; rguenther; gcc-patches; Pa
g precision even though
they have same bytesize.
First we emit vsetvl e8mf8 +vsm for VNx1BI
Then we emit vsetvl e8mf8 + vlm for VNx2BI
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-01 22:03
To: juzhe.zhong
CC: richard.sandiford; gcc-patches; Pan Li; pan2.li; kito.cheng
Subject: R
and GCC will not do th incorrect elimination for RVV.
I think it can work fine even though these 4 modes consume inaccurate memory
storage size
but accurate data memory access load store behavior.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 21:19
To: Pan Li via
d Sandiford
Date: 2023-03-01 21:19
To: Pan Li via Gcc-patches
CC: Richard Biener; Pan Li; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Pan Li via Gcc-patches writes:
> I am not very familiar with the memory patter
safe to support in current stage of GCC 13.
juzhe.zh...@rivai.ai
From: Michael Collison
Date: 2023-02-23 01:54
To: juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; richard.sandiford; richard.guenther
Subject: Re: [PATCH] vect: Check that vector factor is a compile-time constant
Juzhe,
I
h fully support
intrinsic && auto-vec.
You can either wait for the upstream GCC or develop base rvv-next.
juzhe.zh...@rivai.ai
From: Michael Collison
Date: 2023-02-23 01:54
To: juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; richard.sandiford; richard.guenther
Subject: Re: [PATCH] vect: C
> gcc/
>
> * tree-vect-loop-manip.cc (vect_do_peeling): Verify
> that vectorization factor is a compile-time constant.
>
> ---
> gcc/tree-vect-loop-manip.cc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.c
LGTM
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-02-12 19:33
To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH] RISC-V: Handle vlenb correctly in unwinding
gcc/ChangeLog:
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New
gives "v3 = VIEW_CONVERT
(vbool8_t) v4" in gimple.
We failed to fix it in RISC-V backend. Can you help us with this? Thanks.
juzhe.zh...@rivai.ai
From: incarnation.p.lee
Date: 2023-02-11 16:46
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rguenther; Pan Li
Subject: [PATCH] RISC-V: Bugfix
) NUNTTS
VNx8BImode (8,8) NUNTTS
juzhe.zh...@rivai.ai
From: incarnation.p.lee
Date: 2023-02-11 16:46
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rguenther; Pan Li
Subject: [PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types
From: Pan Li
Fix the bug for mode tieable of the rvv bool
We set VL/VTYPE these 2 implicit global status denpency register as fixed reg.
Then CSE can do the optimization now.
>> Yea. I'm wondering about when the right place to introduce these
>>dependencies might be. I'm still a few months out from worrying about
>>RVV, but it's not too far away.
You d
this patch, we hope this can be done
in GCC 14.
Thank you so much.
juzhe.zh...@rivai.ai
From: lehua.ding
Date: 2023-01-13 17:42
To: gcc-patches
CC: richard.sandiford; juzhe.zhong; Lehua Ding
Subject: [PATCH 1/1] [fwprop]: Add the support of forwarding the vec_duplicate
rtx
From: Lehua Ding
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