Matthias Klose 于2025年1月23日周四 22:39写道：
>
LGTM.
Jeff Law 于2025年1月8日周三 07:06写道：
>
>
>
> On 1/1/25 6:42 PM, YunQiang Su wrote:
> > Matthias Klose 于2025年1月1日周三 22:37写道：
> >>
> >> in https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641619.html
> >>
> >> there are two typos in the patc
Matthias Klose 于2025年1月1日周三 22:37写道：
>
> in https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641619.html
>
> there are two typos in the patch, compared to the local Debian patch,
>
Oh, sorry it is not duplicated.
> - the subst macro has an additional parameter
> - the multilib subdirs
Matthias Klose 于2025年1月1日周三 22:37写道：
>
> in https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641619.html
>
> there are two typos in the patch, compared to the local Debian patch,
>
> - the subst macro has an additional parameter
> - the multilib subdirs are not subdirs in lib, but have
>
LLVM introduced this triple support. Let's sync with it.
gcc
* config.gcc: Add mips*64*-linux-muslabi64 triple support.
---
gcc/config.gcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index f09ce9f63a0..848fe7da717 100644
--- a/gcc/c
ChangeLog
* .gitignore: Add .vscode.
---
.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitignore b/.gitignore
index 93a16b0b950..f044fe16b5f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,6 +38,7 @@ cscope.out
.local.vimrc
.lvimrc
+.vscode
.clang-format
.clang-ti
commit b5c2aae48723c9098a8a3dab1409b30fd87bbf56
Author: YunQiang Su
Date: Thu Sep 5 15:14:43 2024 +0800
RISC-V: Lookup reversely in riscv_select_multilib_by_abi
The last element should use index
multilib_infos.size () - 1
gcc
* common/config/riscv/riscv-common.cc
-print-multi-directory`
has same problem.
> (I guess should be -print-multi-directory per your output)
>
> Anyway, you can go ahead and push that after the fix:)
>
>
> On Thu, Sep 5, 2024 at 3:30 PM YunQiang Su wrote:
> >
> > From: YunQiang Su
> >
> > W
From: YunQiang Su
When use --print-multilib-os-dir, gcc outputs different value
with full -march option and the base one only.
$ ./gcc/xgcc --print-multilib-os-dir -mabi=lp64d -march=rv64gc
lib64/lp64d
$ ./gcc/xgcc --print-multilib-os-dir -mabi=lp64d -march=rv64gc_zba
.
The reason is that in
Jie Mei 于2024年7月26日周五 14:50写道：
>
> This patch adds some floating point instructiions from mips32r6,
> for instance, MINA/MAXA.fmt, RINT.fmt, CLASS.fmt etc.
>
> Also add built-in functions to MIPSr6 to better handle tests
> for MIPSr6.
>
> gcc/ChangeLog:
>
> * config/mips/i6400.md (i6400_fp
Victor Do Nascimento 于2024年8月28日周三 23:15写道：
>
> Hello,
>
> Gentle reminder for this simple renaming patch :)
>
Approved, but, it will be better if we can add a test case for it.
> Thanks,
> Victor
>
>
> On 8/15/24 09:44, Victor Do Nascimento wrote:
> > Following the migration of the dot_prod opt
From: YunQiang Su
We have SHF.fmt and HADD_S/U.fmt with MSA, which can be used for
vector reduc.
For min/max for U8/S8, we can
SHF.B W1, W0, 0xb1 # swap byte inner every half
MIN.B W1, W1, W0
SHF.H W2, W1, 0xb1 # swap half inner every word
MIN.B W2, W2, W1
mips16.S was missing since
commit 29b74545531f6afbee9fc38c267524326dbfbedf
Date: Thu Jun 1 10:14:24 2023 +0800
MIPS: Add speculation_barrier support
Without mips16.S included, some symbols will miss for mips16, and
so some software will fail to build.
libgcc/ChangeLog:
* config/mi
YunQiang Su 于2024年7月5日周五 16:14写道：
>
> Ping again.
Ping.
Richard Biener 于2024年7月11日周四 20:21写道：
>
> On Thu, Jul 11, 2024 at 2:13 PM YunQiang Su wrote:
> >
> > From: YunQiang Su
> >
> > PR target/115840.
> >
> > In riscv_preferred_else_value, we create an uninitialized tmp var
> > for else value, i
From: YunQiang Su
PR target/115840.
In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.
The problem is that `warn_uninit` will emit a
From: YunQiang Su
Uninitialized internal temp variable may be useful in some case,
such as for COND_LEN_MUL etc on RISC-V with V extension: If an
const or pre-exists VAR is used, we have to use "undisturbed"
policy; if an uninitialized VAR is used, we can use "agnostic".
From: YunQiang Su
PR target/115840.
In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.
The problem is that `warn_uninit` will emit a
Ping again.
We have done so for MIPSr6, which removes the support of condtional
trap with IMM. To be consistent, Let's do so for pre-R6.
We also add 2 new tests
1) be sure that $0 is used.
2) be sure we expand the condtional trap compare with constant,
instead of leaving it to GAS.
We decide to so so for
With some recent optimization, -O1/-O2/-O3 can archive almost same
performace/size by stack load/store. Thus lwm/swm will save/store
less callee-saved register. In fact only $16 is saved with swm.
To be sure that this optimization does exist, let's add 2 more
function calls. So that lwm/swm can
The scan-assembler-times rules only fit for -mfp32 and -mfpxx.
It fails if we are configured as FP64 by default, as it has
one less sdc1/ldc1 pair.
gcc/testsuite
* gcc.target/mips/call-clobbered-1.c: Add -mfpxx.
---
gcc/testsuite/gcc.target/mips/call-clobbered-1.c | 2 +-
1 file changed,
Currently, we support the cases that strictly fit for the instructions.
For example, for V16QImode, we only support shuffle like
(0<=N0, N1, N2, N3<=3 here)
N0, N1, N2, N3
N0+4N1+4N2+4, N3+4
N0+8N1+8N2+8, N3+8
N0+12 N1+12 N2+12, N
BNEGI.W/D are used for test7_v2f64 and test7_v4f32 now. It is
an improvment since that we can save a instruction.
ILVR.D is used for test43_v2i64 now, instead of INSVE.D.
gcc/testsuite
gcc.target/mips/msa.c: Fix test7_v2f64, test7_v4f32 and
test43_v2i64.
---
gcc/testsuite/gcc.ta
Maciej W. Rozycki 于2024年6月28日周五 01:01写道：
>
> On Thu, 27 Jun 2024, YunQiang Su wrote:
>
> > > The missed optimisation in GAS, which used not to trigger pre-R6, is
> > > irrelevant from this change's point of view and just adds noise. I'm
> > > surpri
Maciej W. Rozycki 于2024年6月27日周四 00:07写道：
>
> On Thu, 20 Jun 2024, YunQiang Su wrote:
>
> > MIPSr6 removes condition trap instructions with imm, so the instruction
> > like `teq $2,imm` will be converted to
> > li $at, imm
> > teq $2, $at
> >
> > Th
Just FYI. This patch does something to gcc.target/mips/madd-8.c, and
gcc.target/mips/msub-8.c.
-PASS: gcc.target/mips/madd-8.c -O2 scan-assembler \tmul\t
-PASS: gcc.target/mips/madd-8.c -O2 scan-assembler-not \tmadd\t
-PASS: gcc.target/mips/madd-8.c -O2 scan-assembler-not \tmflo\t
-PAS
YunQiang Su 于2024年6月14日周五 20:12写道：
>
> PR 115416
>
> When we build a cross toolchain, while without --with-sysroot,
> target headers are expected in
> ${test_exec_prefix}/${target_noncanonical}/sys-include
> while it is true only with --with-headers option is used. In ot
> >
> > And FAOD I think a stub check has to remain even after the removal and
> > just cause `configure' to bail out if an unsupported obsolete version of
> > GAS has been identified.
> >
Ohh, I think that we shouldn't remove it now, as I have figure out
the PCREL patch,
and I am still waiting
Maciej W. Rozycki 于2024年6月21日周五 22:00写道：
>
> On Fri, 21 Jun 2024, Maciej W. Rozycki wrote:
>
> > > Yeah, agreed FWIW. This was necessary while the feature was relatively
> > > new, and while we still supported IRIX as, but I can't see any reasonable
> > > justification for using such an ancient b
Maciej W. Rozycki 于2024年6月21日周五 20:55写道：
>
> On Fri, 21 Jun 2024, Richard Sandiford wrote:
>
> > > We check gcc_cv_as_mips_explicit_relocs if
> > > gcc_cv_as_mips_explicit_relocs_pcrel
> > > only, while gcc_cv_as_mips_explicit_relocs is used by later code.
> > >
> > > Maybe, it is time for use to
>
> Then GCC emits the wrong trap instruction, wherever it comes from and
> whatever has caused it. The correct ones for integer division by zero
Thanks so much. It is not the bug of Linux kernel or GCC.
It is a bug of me ;) and qemu.
Qemu didn't pass the code of TEQ correctly; and I haven't ru
The DIV instructions of MIPS won't be trapped themself if the divisor
is zero. The compiler will emit a conditional trap instruct for it.
So the signal will be SIGTRAP instead of SIGFPE.
gcc/testsuite
* c-c++-common/ubsan/overflow-div-3.c: Use SIGTRAP for MIPS.
---
gcc/testsuite/c-c++-co
YunQiang Su 于2024年6月20日周四 11:20写道：
>
> Maciej W. Rozycki 于2024年6月20日周四 01:24写道：
> >
> > On Wed, 19 Jun 2024, YunQiang Su wrote:
> >
> > > MIPSr6 removes condition trap instructions with imm, so the instruction
> > > like `teq $2,imm` will be converted
MIPSr6 removes condition trap instructions with imm, so the instruction
like `teq $2,imm` will be converted to
li $at, imm
teq $2, $at
The current version of Gas cannot detect if imm is zero, and output
teq $2, $0
Let's do it in GCC.
gcc
* config/mips/mips.md(conditional_trap_reg):
Maciej W. Rozycki 于2024年6月20日周四 01:24写道：
>
> On Wed, 19 Jun 2024, YunQiang Su wrote:
>
> > MIPSr6 removes condition trap instructions with imm, so the instruction
> > like `teq $2,imm` will be converted to
> > li $at, imm
> > teq $2, $at
> >
> > Th
Collin Funk 于2024年6月20日周四 07:40写道：
>
> I've just fixed the quotes and that typo in one patch. I hope you don't
> mind. When using Autoconf 2.69 and Automake 1.15.1 that copyright diff
> goes away. I'm not familiar with the gcc-autoregen bot but I think this
> should make it happy.
>
> -- >8 --
We check gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel
only, while gcc_cv_as_mips_explicit_relocs is used by later code.
Maybe, it is time for use to set gcc_cv_as_mips_explicit_relocs always now,
as it has been in Binutils for more than 20 years.
gcc
* configure.
Thanks. Sorry for the noise. I have reverted
8088374a868aacab4dff208ec3e3fde790a1d9a3
c6a9ab8c920f297c4efd289182aef9fbc73f5906
I will submit and back port the modification of gcc_cv_as_mips_explicit_relocs
separately.
@Collin Funk Can you sent a new correct/full patch?
Currently, we have `mips_expand_vec_cond_expr`, which calculate
cmp_res first. We can just add a new extra argument to ask it
to use operands[3] as cmp_res instead of calculating from operands[4]
and operands[5].
gcc
* config/mips/mips.cc(mips_expand_vec_cond_expr): Add extra
argu
MIPSr6 removes condition trap instructions with imm, so the instruction
like `teq $2,imm` will be converted to
li $at, imm
teq $2, $at
The current version of Gas cannot detect if imm is zero, and output
teq $2, $0
Let's do it in GCC.
gcc
* config/mips/mips.cc(mips_expand_conditional
On most uarch, the cost condmove is same as other noraml integer,
and it should be COSTS_N_INSNS(1).
In GCC12 or previous, the condmove is always enabled, and from
GCC13, we start to compare the cost.
The generic rtx_cost give the result of COSTS_N_INSN(2).
Let's define it to COSTS_N_INSN(1) in m
OK for trunk?
--
YunQiang Su
PR target/111376.
Currently, we are using LUI/ANDI/BEQZ for on-bit-test if the bitpos>=16,
while in fact we can use SLL/BGEZ.
Note:
1) if bitpos<16, we can use ANDI/BEQZ.
2) For R2+, we have EXT.
Known problems:
1. On some uarch, SLL has more delay, such as 74K:
See the talk in https://gcc
Richard Biener 于2024年6月6日周四 14:20写道：
>
> On Thu, 6 Jun 2024, YunQiang Su wrote:
>
> > Richard Biener 于2024年5月28日周二 17:47写道：
> > >
> > > The following avoids accounting single-lane SLP to the discovery
> > > limit. As the two testcases show this makes di
Xi Ruoyao 于2024年6月9日周日 21:50写道：
>
> A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and
> pair, and twice fast as a srli/slli pair. When the src reg and the dst
Just want to know that why not adjust the RTX cost of bstrins vs srli/slli?
It may benefit more cases.
> reg happ
PR 115416
When we build a cross toolchain, while without --with-sysroot,
target headers are expected in
${test_exec_prefix}/${target_noncanonical}/sys-include
while it is true only with --with-headers option is used. In other
cases, the path should be
${test_exec_prefix}/${target_noncanonical}
Sam James 于2024年6月14日周五 09:02写道：
>
> Collin Funk writes:
>
> > When dlopen and pthread_create are in libc the variable is
> > set to "none required", therefore running configure will show
> > the following errors:
> >
> > ./configure: line 8997: test: too many arguments
> > ./configure: line 8999
Richard Sandiford 于2024年6月6日周四 17:54写道：
>
> YunQiang Su writes:
> > YunQiang Su 于2024年5月29日周三 10:02写道：
> >>
> >> Richard Sandiford 于2024年5月29日周三 05:28写道：
> >> >
> >> > YunQiang Su writes:
> >> > > If `find_a_progra
HLIKELY_ALWAYS)
MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
Here PROCESSOR_4KC and PROCESSOR_5KC are both FPU-less.
> Jeff
>
--
YunQiang Su
YunQiang Su 于2024年6月9日周日 18:25写道：
>
> > >
> > > gcc/ChangeLog:
> > >
> > > * ifcvt.cc (cond_move_process_if_block):
> > > Consider the result of targetm.noce_conversion_profitable_p()
> > > when replacing the original se
nk.
>
Sorry for the delay report. With this patch the test
gcc.target/mips/movcc-3.c fails.
> Jeff
--
YunQiang Su
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
c.lt.fmt will signal for all NaN, including qNaN;
cmp.lt.fmt will only signal sNaN, while not qNaN;
cmp.slt.fmt has the same semantic as c.lt.fmt;
lt/le of RTL will signaling qNaN.
while in `s__using_
In mips.cc(mips_reorg_process_insns), there is this claim:
Also delete cache barriers if the last instruction
was an annulled branch. INSN will not be speculatively
executed.
And with -O1 on mips64, we can generate binary code like this,
which fails this test.
gcc/testsuite
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
c.lt.fmt will signal for all NaN, including qNaN;
cmp.lt.fmt will only signal sNaN, while not qNaN;
cmp.slt.fmt has the same semantic as c.lt.fmt;
lt/le of RTL will signaling qNaN.
while in `s__using_
From: YunQiang Su
In mips_insn_cost, COSTS_N_INSNS is missing when we return the cost
if count * ratio > 0.
gcc
* config/mips/mips.cc(mips_insn_cost): Add missing COSTS_N_INSNS
to count.
---
gcc/config/mips/mips.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
*/
> + SLP_TREE_SCALAR_STMTS (res) = vNULL;
> + SLP_TREE_DEF_TYPE (res) = vect_uninitialized_def;
> + res->failed = XNEWVEC (bool, group_size);
> + memset (res->failed, 0, sizeof (bool) * group_size);
> + memset (matches, 0, sizeof (bool) * group_size);
> + return NULL;
> + }
> + --*limit;
> }
> - --*limit;
>
>if (dump_enabled_p ())
> dump_printf_loc (MSG_NOTE, vect_location,
> --
> 2.35.3
--
YunQiang Su
YunQiang Su 于2024年5月29日周三 10:02写道：
>
> Richard Sandiford 于2024年5月29日周三 05:28写道：
> >
> > YunQiang Su writes:
> > > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > > toolchain,
> > > the final fallback is `as/ld` of system.
Richard Sandiford 于2024年6月5日周三 23:20写道：
>
> YunQiang Su writes:
> > Richard Sandiford 于2024年6月5日周三 22:14写道：
> >>
> >> YunQiang Su writes:
> >> > PR target/113179.
> >> >
> >> > In `store_bit_field_using_insv`, we just
Richard Sandiford 于2024年6月5日周三 22:14写道：
>
> YunQiang Su writes:
> > PR target/113179.
> >
> > In `store_bit_field_using_insv`, we just use SUBREG if value_mode
> >>= op_mode, while in some ports, a sign_extend will be needed,
> > such as MIPS64:
> >
Kewen Lin 于2024年6月3日周一 11:03写道：
>
> This is to add new port specific hook implementation
> mips_c_mode_for_floating_type, remove macros FLOAT_TYPE_SIZE
> and DOUBLE_TYPE_SIZE, rename LONG_DOUBLE_TYPE_SIZE to
> MIPS_LONG_DOUBLE_TYPE_SIZE since we poison LONG_DOUBLE_TYPE_SIZE
> but some subtarget wa
Richard Sandiford 于2024年5月29日周三 05:28写道：
>
> YunQiang Su writes:
> > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try with
> > -as/ld/objcopy before fa
YunQiang Su 于2024年5月22日周三 17:54写道：
>
> If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
> the final fallback is `as/ld` of system. In fact, we can have a try with
> -as/ld/objcopy before fallback to native as/ld/objcopy.
>
> This patch is derivat
PR Target/84790.
The gp init sequence
li $2,%hi(_gp_disp)
addiu $3,$pc,%lo(_gp_disp)
sll $2,16
addu$2,$3
is generated directly in `mips_output_function_prologue`, and does
not appear in the RTL.
So the IRA/IPA passes are not aware that $2/$3 have been
commit 05daf617ea22e1d818295ed2d037456937e23530
Author: Jeff Law
Date: Sat May 25 12:39:05 2024 -0600
[committed] [v2] More logical op simplifications in simplify-rtx.cc
does some simplifications, and then `bseli.b $w1,$w0,255` is found that
it is same with `or.v $w1,$w0,$w1`. So there wil
When looking for as/ld/objcopy, `find_a_program/file_at_path` only
try to find the raw name, but won't find the one with -
prefix.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(for_each_path): Add more space for -.
(file_at_path): S
If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try with
-as/ld/objcopy before fallback to native as/ld/objcopy.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
Jakub Jelinek 于2024年5月22日周三 17:33写道：
>
> On Wed, May 22, 2024 at 05:23:33PM +0800, YunQiang Su wrote:
> > Jakub Jelinek 于2024年5月22日周三 17:14写道：
> > >
> > > On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > > > --- gcc/gcc.cc
Jakub Jelinek 于2024年5月22日周三 17:14写道：
>
> On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > --- gcc/gcc.cc.jj 2024-02-09 14:54:09.141489744 +0100
> > > +++ gcc/gcc.cc 2024-02-09 22:04:37.655678742 +0100
> > > @@ -2410,8 +2410,7 @@ read_sp
ision (pp, *text->m_args_ptr, precision,
> + int, "d");
> break;
>
> case 'o':
> @@ -1579,8 +1614,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, "%" HOST_WIDE_INT_PRINT "o",
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "o");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "o");
> break;
>
> case 's':
> @@ -1599,8 +1634,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_UNSIGNED,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "u");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "u");
> break;
>
> case 'f':
> @@ -1629,8 +1664,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_HEX,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "x");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "x");
> break;
>
> case '.':
> @@ -2774,6 +2809,18 @@ test_pp_format ()
>ASSERT_PP_FORMAT_2 ("17 12345678", "%wo %x", (HOST_WIDE_INT)15,
> 0x12345678);
>ASSERT_PP_FORMAT_2 ("0xcafebabe 12345678", "%wx %x",
> (HOST_WIDE_INT)0xcafebabe,
> 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%zd %x", (ssize_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%zi %x", (ssize_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%zu %x", (size_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%zo %x", (size_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("cafebabe 12345678", "%zx %x", (size_t)0xcafebabe,
> + 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%td %x", (ptrdiff_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%ti %x", (ptrdiff_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%tu %x", (ptrdiff_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%to %x", (ptrdiff_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("1afebabe 12345678", "%tx %x", (ptrdiff_t)0x1afebabe,
> + 0x12345678);
>ASSERT_PP_FORMAT_2 ("1.00 12345678", "%f %x", 1.0, 0x12345678);
>ASSERT_PP_FORMAT_2 ("A 12345678", "%c %x", 'A', 0x12345678);
>ASSERT_PP_FORMAT_2 ("hello world 12345678", "%s %x", "hello world",
>
> Jakub
>
--
YunQiang Su
Andrew Pinski 于2024年5月21日周二 20:23写道：
>
> On Tue, May 21, 2024 at 5:12 AM YunQiang Su wrote:
> >
> > If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try
> > with -as/ld b
If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try
with -as/ld before fallback to native as/ld.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(execute): Lo
PR target/113955
The `-mlra` option was introduced in 2014 for MIPS, and was set to
default since then. It's time for us to drop no-lra support by
dropping -m(no-)lra options.
gcc:
* config/mips/mips.cc(mips_option_override):
Drop mips_lra_flag variable;
(mips_lra_p): Remo
Support syntax like:
asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));
gcc
* config/mips/constraints.md: Add new constraint 'w'.
gcc/testsuite
* gcc.target/mips/msa-inline-asm.c: New test.
---
gcc/config/mips/constraints.md | 3 +++
gcc/tes
I will apply this patch.
While we still have a problem about
```
float max(float a, float b) { return a>=b?a:b; }
```
If it is compiled with `-ffinite-math-only -fsigned-zeros -O2
-mips32r6 -mabi=32`,
`max.s` can be used.
The max.fmt/min.fmt of MIPSr6 can process +0/-0 correctly.
Xi Ruoyao 于2024年3月26日周二 18:10写道：
>
> On Tue, 2024-03-26 at 11:15 +0800, YunQiang Su wrote:
>
> /* snip */
>
> > With -ffinite-math-only -fno-signed-zeros, it does work with
> > x >= y ? x : y
> > while without `-ffinite-math-only -fno-signed-zeros`, it cann
Jeff Law 于2024年1月3日周三 01:00写道：
>
>
>
> On 1/1/24 09:48, YunQiang Su wrote:
> > When building multilib libraries, CC/CXX etc are set with an option
> > -B*/lib/, instead of -B/lib/.
> > This will make some trouble in some case, for example building
> > cro
PR target/113179.
In `store_bit_field_using_insv`, we just use SUBREG if value_mode
>= op_mode, while in some ports, a sign_extend will be needed,
such as MIPS64:
If either GPR rs or GPR rt does not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is
Xi Ruoyao 于2024年3月20日周三 15:12写道：
>
> We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
> arguments and there is nothing to advance, but that is not the case
> for (...) functions returning by hidden reference which have one such
> artificial argument. This is causing gcc.dg/c23-st
Jie Mei 于2024年3月25日周一 17:46写道：
>
> This patch adds the smin/smax RTL mode for the
> min/max.fmt instructions.
>
> Also, since the min/max.fmt instrucions applies to the
> IEEE 754-2008 "minNum" and "maxNum" operations, this
> patch also provides the new "fmin3" and
> "fmax3" modes.
>
> gcc/ChangeL
Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid.
Let's define __mips_strict_alignment for MIPSr6 and -mstrict-align
is used.
Not that, this macro is always defined for pre-R6.
gcc
config/mips/mips.h (TARGET_CPU_CPP_BUILTIN
Sam James 于2024年3月17日周日 14:04写道：
>
> YunQiang Su writes:
>
> > Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
> > and RISC-V predefines __riscv_misaligned_avoid, while other ports
> > that support -mstrict-align/-mno-unaligned-access don'
Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access,
and RISC-V predefines __riscv_misaligned_avoid, while other ports
that support -mstrict-align/-mno-unaligned-access don't have such
macro, and these backend macros are only avaiable for c-family.
Note: Arm64 always predefine __ARM_F
Fixes: acc38ff59976 ("MIPS: Add -m(no-)strict-align option")
gcc/ChangeLog:
* config/riscv/riscv.opt.urls: Regenerated.
* config/rs6000/sysv4.opt.urls: Likewise.
* config/xtensa/xtensa.opt.urls: Likewise.
---
gcc/config/riscv/riscv.opt.urls | 2 +-
gcc/config/rs6000/sys
actice for this cases?
Should I push a new commit? Or in fact a single commit is preferred?
--
YunQiang Su
We support options -m(no-)unaligned-access 2 years ago, while
currently most of other ports prefer -m(no-)strict-align.
Let's support -m(no-)strict-align, and keep -m(no-)unaligned-access
as alias.
gcc
* config/mips/mips.opt: Support -mstrict-align, and use
TARGET_STRICT_ALIGN as t
The problem is that, there are these lines in mips.opt.urls:
; skipping UrlSuffix for 'mabi=' due to finding no URLs
; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs
; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs
These lines is not fixed by this patch due
e documentation.
>
> But we should first apply this diff. Could you double check it is
> sane/correct?
>
> Thanks,
>
> Mark
--
YunQiang Su
Xi Ruoyao 于2024年2月5日周一 02:01写道：
>
> We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
> wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
> fail when Python is built with MSA enabled.
>
> Use the bnegi.df instructions to simply reverse the sign bit instead.
>
>
GAS introduced explicit relocs since 2001, and %pcrel_hi/low were
introduced in 2014. In future, we may introduce more.
Let's convert -mexplicit-relocs option, and accpet options:
none, base, pcrel.
We also update gcc/configure.ac to set the value to option
the gas support when GCC itself is
From: YunQiang Su
Currently, almost all of the shared libraries of MIPS, rely on $t9
to get the address of current function, instead of PCREL instructions,
even on MIPSr6. So we have to set $t9 properly.
To get the address of preemptible function, we need the help of GOT.
MIPS/O32 has .cpload
++ b/gcc/testsuite/gcc.c-torture/execute/pr113010.c
> @@ -0,0 +1,9 @@
> +int minus_1 = -1;
> +
> +int
> +main ()
> +{
> + if ((0, 0xul) >= minus_1)
There is a warning option:
-Wsign-compare
Warn when a comparison between signed and unsigned values could
produce an incorrect result when the signed value is converted to unsigned.
> +__builtin_abort ();
> + return 0;
> +}
> --
> 2.34.1
>
--
YunQiang Su
e option is needed to
> > enable vectorizations. For example, ia64,x86,aarch64, and riscv
> > architectures, vectorization is enabled by default.
>
> But no. The default baseline of 32-bit x86 is i686, which is basically
> a Pentium III launched in 1999 without any vector instructions.
>
> We are still missing something here.
>
There is a line
#define vector __attribute__((vector_size(4*sizeof(int
I guess it is the syntax needs to be supported.
--
YunQiang Su
YunQiang Su 于2023年8月25日周五 15:16写道：
>
> When working on LLVM, I found this problem
> https://github.com/llvm/llvm-project/issues/64974.
> Maybe it's time for us to reconsider the way of getting GOT address
> for PIC code.
>
I have my draft patch pushed to GitHub:
htt
$GP is used for expanding GOT load, and in the afterward passes,
we will try to use a temporary register instead.
If sucess, we have no need to store and reload $gp. The example
of failure is that the function calls a preemtive function.
We shouldn't use $GP for any other purpose in the code we g
ltilib \
--with-arch-32=mips32r2 --with-fp-32=xx \
--enable-multiarch --enable-targets=all \
--with-arch-64=mips64r2 --prefix=/usr --disable-libsanitizer
4. make -j
--
YunQiang Su
Fix build warning:
mips.cc: warning: unused parameter 'decl'.
gcc
* config/mips/mips.cc (mips_start_function_definition):
Add ATTRIBUTE_UNUSED.
---
gcc/config/mips/mips.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/mips/mips.cc b/gcc/config/
I have tested this patch on mips64el: No regression.
gcc/testsuite
* gcc.c-torture/compile/mipscop-1.c: Include stdio.h.
* gcc.c-torture/compile/mipscop-2.c: Ditto.
* gcc.c-torture/compile/mipscop-3.c: Ditto.
* gcc.c-torture/compile/mipscop-4.c: Ditto.
---
gcc/testsuite/gcc.c-torture/compile/mipscop-1.c | 1 +
gcc/te
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
For SI mode, if the sign-bit is modified by bitops, we will need a
sign-extend operation. Since 32bit INS instruction can be sure that
result is sign-extended, and the Q
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