We have done so for MIPSr6, which removes the support of condtional
trap with IMM. To be consistent, Let's do so for pre-R6.
We also add 2 new tests
1) be sure that $0 is used.
2) be sure we expand the condtional trap compare with constant,
instead of leaving it to GAS.
We decide to so so for MIPSr6 is that, we find a problem for code
.set noreorder
.set nomacro
teq $2,0
GAS expands it instead of converting it to `teq $2,$0`:
li $3,0
teq $2,$3
It is wrong, as we ask for `nomacro`.
GCC works well with `teq $2,IMM`, if IMM is not zero. To be
sure that it will always be so in future, Let's add a test for it.
gcc
* config/mips/mips.md(conditional_trap): Output $0 instead of
IMM0.
gcc/testsuite:
* gcc.target/mips/trap-compare-0.c: Testcase to be sure that
$0 is used instead of IMM0 for conditional trap.
* gcc.target/mips/trap-compare-imm-r6.c: Testcase to be sure
that we expand condtional trap compare with constant.
---
gcc/config/mips/mips.md | 2 +-
.../gcc.target/mips/trap-compare-0.c | 31 ++++++++++++++++
.../gcc.target/mips/trap-compare-imm-r6.c | 36 +++++++++++++++++++
3 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/mips/trap-compare-0.c
create mode 100644 gcc/testsuite/gcc.target/mips/trap-compare-imm-r6.c
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index fd64d3d001a..591ae3cb438 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1254,7 +1254,7 @@ (define_insn "*conditional_trap<mode>"
(match_operand:GPR 2 "arith_operand" "dI")])
(const_int 0))]
"ISA_HAS_COND_TRAPI"
- "t%C0\t%z1,%2"
+ "t%C0\t%z1,%z2"
[(set_attr "type" "trap")])
;;
diff --git a/gcc/testsuite/gcc.target/mips/trap-compare-0.c
b/gcc/testsuite/gcc.target/mips/trap-compare-0.c
new file mode 100644
index 00000000000..fb0078d34f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/trap-compare-0.c
@@ -0,0 +1,31 @@
+/* Check that we use $0 instead of 0 in conditional trap. */
+/* { dg-do compile } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16
+void teq0 (int i) {
+ if (i == 0)
+ __builtin_trap();
+}
+
+NOMIPS16
+void tne0 (int i) {
+ if (i != 0)
+ __builtin_trap();
+}
+
+NOMIPS16
+void tge0 (int i) {
+ if (i >= 0)
+ __builtin_trap();
+}
+NOMIPS16
+void tlt0 (int i) {
+ if (i < 0)
+ __builtin_trap();
+}
+
+/* { dg-final { scan-assembler "teq0:.*\tteq\t\\\$4,\\\$0" } } */
+/* { dg-final { scan-assembler "tne0:.*\ttne\t\\\$4,\\\$0" } } */
+/* { dg-final { scan-assembler "tge0:.*\ttge\t\\\$4,\\\$0" } } */
+/* { dg-final { scan-assembler "tlt0:.*\ttlt\t\\\$4,\\\$0" } } */
diff --git a/gcc/testsuite/gcc.target/mips/trap-compare-imm-r6.c
b/gcc/testsuite/gcc.target/mips/trap-compare-imm-r6.c
new file mode 100644
index 00000000000..b12e40672d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/trap-compare-imm-r6.c
@@ -0,0 +1,36 @@
+/* Check that no teq $2,imm macro is used for R6. */
+/* { dg-do compile } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-options "isa_rev>=6" } */
+
+NOMIPS16
+void teq5 (int i) {
+ if (i == 5)
+ __builtin_trap();
+}
+
+NOMIPS16
+void tne5 (int i) {
+ if (i != 5)
+ __builtin_trap();
+}
+
+NOMIPS16
+void tge5 (int i) {
+ if (i >= 5)
+ __builtin_trap();
+}
+NOMIPS16
+void tlt5 (int i) {
+ if (i < 5)
+ __builtin_trap();
+}
+
+/* { dg-final { scan-assembler "teq5:.*\tli\t\\\$2,5.*\tteq\t\\\$4,\\\$2" } }
*/
+/* { dg-final { scan-assembler-not "teq5:.*\tteq\t\\\$4,5" } } */
+/* { dg-final { scan-assembler "tne5:.*\tli\t\\\$2,5.*\ttne\t\\\$4,\\\$2" } }
*/
+/* { dg-final { scan-assembler-not "tne5:.*\ttne\t\\\$4,5" } } */
+/* { dg-final { scan-assembler "tge5:.*\tli\t\\\$2,4.*\ttge\t\\\$2,\\\$4" } }
*/
+/* { dg-final { scan-assembler-not "tge5:.*\ttge\t\\\$4,5" } } */
+/* { dg-final { scan-assembler "tlt5:.*\tli\t\\\$2,4.*\ttge\t\\\$2,\\\$4" } }
*/
+/* { dg-final { scan-assembler-not "tlt5:.*\ttlt\t\\\$4,5" } } */
--
2.39.3 (Apple Git-146)
