[COMMITTED] Re: Re: [PATCH] RISC-V: Add an implicit dependency for Zawrs

2024-09-30 14:32  Kito Cheng wrote: > >LGTM, and let me know if you need my help to commit that :) Thank you, Kito. Recently, I received permission from Jeff. > >On Mon, Sep 30, 2024 at 9:37 AM Xiao Zeng wrote: >> >> There is a description in >> <https://githu

[PATCH] RISC-V: Add an implicit dependency for Zawrs

uded that: zawrs -> zalrsc. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: zawrs -> zalrsc. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-38.c: New test. * gcc.target/riscv/predef-39.c: New test. Signed-off-by: Xiao Zeng --- gcc/common/config/riscv/riscv-co

Re: Re: [PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

2024-08-13 15:53  Jakub Jelinek wrote: > >On Tue, Aug 13, 2024 at 11:14:47AM +0800, Xiao Zeng wrote: >> Thank you very much for the in-depth discussion between Jakub Jelinek and >> jeff. >> My knowledge is narrow, and I am not familiar with architectures other than >&

Re: Re: [PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

inning, I had planned to only add the __mulbc3/__divbc3 interface in libgcc. After exploration, it was found that libgcc already has a complete infrastructure, and adding only the __mulbc3/__divbc3 interfaces would cause a lot of trouble. In this context, it was decided to add a new data type BF16 to the infrastructure of libgcc, similar to FP16. Perhaps I can get some suggestions to complete the addition of __mulbc3/__divbc3 and eliminate errors when linking. Thanks Xiao Zeng

Re: [PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

2024-08-07 11:13  Xiao Zeng wrote: The existing test cases 'gcc.dg/portal/float16 complex.c' for gcc are already good, so no new test cases were added. Of course, more test cases are always good, and if necessary, I will supplement the test cases. > >gcc/ChangeLog: >

[PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

. (CEXT): Ditto. (NOTRUNC): Ditto. * libgcc2.h (LIBGCC2_HAS_BF_MODE): Support BF16. (__attribute__): Ditto. (__divbc3): Add __divbc3 declaration. (__mulbc3): Add __mulbc3 declaration. Signed-off-by: Xiao Zeng --- gcc/builtin-types.def| 30

[PATCH v2 0/1] RISC-V: Support BF16 interfaces in libgcc

3 This modification will have an impact on all architectures that support BF16. I have completed the following tests: x86_64 bootstrap based on 18eb6ca136fcd22b381d222cab81265d812ea7b9 passed. riscv64 bootstrap based on a59c4e496fa916cb9a484a649aa1b4cebd6550f2 passed. The riscv64 regres

Re: Re: [PATCH] RISC-V: Minimal support for Zimop extension.

d version #s for the spec and handles the implied extensions. >> Let's go with Xiao's version. >> >> Xiao, the Zimop/Zcmop patches are OK for binutils. >> >> Jiawei, the GCC patches are OK once Xiao pushes his changes to the >> binutils repo.  Alternately if you have permissions in the binutils >> repo, you can push them for Xiao. >> >> Jeff > >Thanks Jeff! I think I do not have the permissions in the binutils repo, >let me contact Nelson to ask him give  some help. I am glad that the patch previously submitted can still be discussed and may be accepted. If you have any questions, please feel free to contact me. > > >BR, > >Jiawei Thanks Xiao Zeng

[COMMITTED] Re: Re: [PATCH] RISC-V: NFC: Do not use zicond for pr105314 testcases

2024-08-01 09:53  Jeff Law wrote: > > > >On 7/30/24 7:05 PM, Xiao Zeng wrote: >> 2024-07-31 03:10  Jeff Law wrote: >>> >>> >>> >>> On 7/28/24 7:58 PM, Xiao Zeng wrote: >>>> gcc/testsuite/ChangeLog: >>>> >>>&g

Re: Re: [PATCH] RISC-V: NFC: Do not use zicond for pr105314 testcases

2024-07-31 03:10  Jeff Law wrote: > > > >On 7/28/24 7:58 PM, Xiao Zeng wrote: >> gcc/testsuite/ChangeLog: >> >>  * gcc.target/riscv/pr105314-rtl.c: Skip zicond. >>  * gcc.target/riscv/pr105314-rtl32.c: Dotto. >>  * gcc.target/ri

[PATCH] RISC-V: NFC: Do not use zicond for pr105314 testcases

gcc/testsuite/ChangeLog: * gcc.target/riscv/pr105314-rtl.c: Skip zicond. * gcc.target/riscv/pr105314-rtl32.c: Dotto. * gcc.target/riscv/pr105314.c: Dotto. Signed-off-by: Xiao Zeng --- gcc/testsuite/gcc.target/riscv/pr105314-rtl.c | 2 +- gcc/testsuite/gcc.target/riscv

Re: Re: [PATCH] RISC-V: Support __mulbc3 and __divbc3 in libgcc for __bf16

2024-07-18 01:53  Jeff Law wrote: > > > >On 7/17/24 2:01 AM, Xiao Zeng wrote: >> libgcc/ChangeLog: >> >> * Makefile.in: Support __divbc3 and __mulbc3. >> * libgcc2.c (if): Support BC mode for __bf16. >> (defined): Ditto. >> (MTYPE): Ditto. >>

[PATCH] RISC-V: Support __mulbc3 and __divbc3 in libgcc for __bf16

. * libgcc2.h (LIBGCC2_HAS_BF_MODE): Ditto. (__attribute__): Ditto. (__divbc3): Add __divbc3 for __bf16. (__mulbc3): Add __mulbc3 for __bf16. gcc/testsuite/ChangeLog: * gcc.target/riscv/bf16-mulbc3-divbc3.c: New test. Signed-off-by: Xiao Zeng

[COMMITTED] [PATCH v2] RISC-V: Add Zfbfmin extension

2024-06-04 04:30  Jeff Law wrote: > > > >On 6/1/24 1:45 AM, Xiao Zeng wrote: >> 1 In the previous patch, the libcall for BF16 was implemented: >> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8c7cee80eb50792e57d514be1418c453ddd1073e> >> >> 2 Riscv provi

Re: Re: [PING] [PATCH] RISC-V: Add Zfbfmin extension

2024-06-01 12:34  Jeff Law wrote: > > > >On 5/30/24 5:38 AM, Xiao Zeng wrote: >> 1 In the previous patch, the libcall for BF16 was implemented: >> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8c7cee80eb50792e57d514be1418c453ddd1073e> >> >> 2 Riscv provi

[PATCH v2] RISC-V: Add Zfbfmin extension

1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

[PING] [PATCH] RISC-V: Add Zfbfmin extension

1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

[PATCH] RISC-V: Add Zfbfmin extension

1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

[COMMITTED] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

2024-05-18 09:57  Jeff Law wrote: > > > >On 5/15/24 7:55 PM, Xiao Zeng wrote: >> 1 According to unpriv-isa spec: >> <https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-221bd85-2024-05-14/unpriv-isa-asciidoc.pdf> >>    1.1 "FMV.H

Re: Re: [PATCH] RISC-V: Modify _Bfloat16 to __bf16

you need for a change that is isolated to RISC-V code. > >jeff Thanks Xiao Zeng

[COMMITTED] RISC-V: Modify _Bfloat16 to __bf16

2024-05-17 16:19  Kito Cheng wrote: > >LGTM, thanks for fixing this :) 1 Passed CI testing: <https://patchwork.sourceware.org/project/gcc/patch/20240517081013.12611-1-zengx...@eswincomputing.com/> 2 pushed to trunk. > >On Fri, May 17, 2024 at 4:05 PM Xiao Zeng wrote: >

[PATCH] RISC-V: Modify _Bfloat16 to __bf16

According to the description in: , the type representation symbol of BF16 has been corrected. Kito Cheng pointed out relevant information in the email: gcc/ChangeLog:

Re: Re: [NOT CODE REVIEW] [PATCH v3 1/1] [RISC-V] Add support for _Bfloat16

2024-05-16 16:55  Kito Cheng wrote: > >Hi Xiao Zeng: > >Just wondering why use _Bfloat16 rather than __bf16? you mention >__bf16 in comment, but implementation use _Bfloat16? Obviously, this is a mistake. This patch has spanned a considerable amount of time locally. I will submit

[PATCH] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

1 According to unpriv-isa spec: 1.1 "FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to t

[COMMITTED] RISC-V: Add Zvfbfwma extension to the -march= option

ct/gcc/patch/20240515054029.52476-1-zengx...@eswincomputing.com/> 2 After fixing the format, pushed to trunk. > >On Wed, May 15, 2024 at 1:35 PM Xiao Zeng wrote: >> >> This patch would like to add new sub extension (aka Zvfbfwma) to the >> -march= option. It introduces a new dat

[PATCH] RISC-V: Add Zvfbfwma extension to the -march= option

This patch would like to add new sub extension (aka Zvfbfwma) to the -march= option. It introduces a new data type BF16. 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In EmbeddedProcessor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Z

Re: [COMMITED] MAINTAINERS: Fix an entry using spaces instead of tabs

| 2 +- > contrib/check-MAINTAINERS.py | 8 > 2 files changed, 9 insertions(+), 1 deletion(-) > >diff --git a/MAINTAINERS b/MAINTAINERS >index 361059fd55c..8bb435dd54e 100644 >--- a/MAINTAINERS >+++ b/MAINTAINERS >@@ -738,7 +738,7 @@ Kwok Cheung

MAINTAINERS: Add myself to write after approval

David Yuste Adhemerval Zanella +Xiao Zeng Dennis Zhang Yufeng Zhang Qing Zhao

Re: Re: [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

2024-05-09 04:01  Jeff Law wrote: > > > >On 5/7/24 6:38 PM, Xiao Zeng wrote: >> 1 This patch implements the Nan-box of bf16. >> >> 2 Please refer to the Nan-box implementation of hf16 in: >> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660

[PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

1 This patch implements the Nan-box of bf16. 2 Please refer to the Nan-box implementation of hf16 in: 3 The discussion about Nan-box can be found on the website:

[PATCH v1 0/1] RISC-V: Nan-box the result of movbf on soft-bf16

sation: --- On 5/7/24 01:25, Xiao Zeng wrote: > Hi, during the use of CI, I discovered a possible issue and am now providing > feedback to you > > https://github.com/ewlu/gcc-precommit-ci/issues/1481 > > The RISCV_Nanbox_the_result_of_movbf_on_softbf16 rel

[PATCH] RISC-V: Nan-box the result of movbf on soft-bf16

1 This patch implements the Nan-box of bf16. 2 Please refer to the Nan-box implementation of hf16 in: 3 The discussion about Nan-box can be found on the website:

Re: Re: [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

2024-05-07 06:40  Jeff Law wrote: >   > > >On 4/11/24 9:32 PM, Xiao Zeng wrote: >> This patch would like to add new sub extension (aka Zfbfmin) to the >> -march= option. It introduces a new data type BF16. >> >> 1 The Zfbfmin extension depend on 'F&#x

[NOT CODE REVIEW] [PATCH v3 1/1] [RISC-V] Add support for _Bfloat16

1 At point , BF16 has already been completed "post public review". 2 LLVM has also added support for RISCV BF16 in and . 3 According to the discussion

[NOT CODE REVIEW] [PATCH v3 0/1] [RISC-V] Add support for _Bfloat16

d into trunk. Detailed information can be found: <https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650716.html> Xiao Zeng (1): [RISC-V] Add support for _Bfloat16 gcc/config/riscv/iterators.md | 2 + gcc/config/riscv/riscv-builtins.cc| 16 gcc/config

Re: Re: [PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

2024-05-04 23:23  Jeff Law wrote: >   > > >On 4/2/24 3:22 AM, Xiao Zeng wrote: >> 1 At point <https://github.com/riscv/riscv-bfloat16>, >>    BF16 has already been completed "post public review". >> >> 2 LLVM has also added support for RIS

[PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

This patch would like to add new sub extension (aka Zfbfmin) to the -march= option. It introduces a new data type BF16. 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instruc

Re: Re:[PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

s, we must ensure that running tests is also feasible. A great testcase has already been provided in the gcc test suite: gcc/testsuite/g++.dg/cpp23/ext-floating14.C So, I didn't add any test cases to run the tests. > >BR, >Jin   Thanks Xiao Zeng

[PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

1 At point , BF16 has already been completed "post public review". 2 LLVM has also added support for RISCV BF16 in and . 3 According to the discussion

[PATCH v2 0/1] [RISC-V] Add support for _Bfloat16

ring the non-standard commit information, this submission was made. Patch v2 fixed failed test cases. *** BLURB HERE *** Xiao Zeng (1): [RISC-V] Add support for _Bfloat16 gcc/config/riscv/iterators.md | 2 + gcc/config/riscv/riscv-builtins.cc| 16 gcc/config

[PATCH 1/1] [RISC-V] Add support for _Bfloat16

1 At point , BF16 has already been completed "post public review". 2 LLVM has also added support for RISCV BF16 in and . 3 According to the discussion

[PATCH 0/1] [RISC-V] Add support for _Bfloat16

ring the non-standard commit information, this submission was made. Xiao Zeng (1): [RISC-V] Add support for _Bfloat16 gcc/config/riscv/iterators.md | 2 + gcc/config/riscv/riscv-builtins.cc| 16 gcc/config/riscv/riscv-modes.def | 3 + gcc/config/ri

[PATCH 1/1] [RISCV] Add support for _Bfloat16

1 At point , BF16 has already been completed "post public review". 2 LLVM has also added support for RISCV BF16 in and . 3 According to the discussion

[PATCH 0/1] [RISCV] Add support for _Bfloat16

been provided on the flow of data type conversion. The basis of this patch is: <https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630858.html> Xiao Zeng (1): [RISCV] Add support for _Bfloat16 gcc/config/riscv/iterators.md | 2 + gcc/config/riscv/riscv-built

Re: Re: [PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

2023-12-16 03:27  Jeff Law wrote: >   > > >On 12/12/23 20:24, Xiao Zeng wrote: >> This patch would like to add new sub extension (aka Zvfbfmin) to the >> -march= option. It introduces a new data type BF16. >> >> Depending on different usage scenarios, the Zv

Re: Re: [PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

rror "__riscv_f" >> +#endif >> + >> +#if !defined(__riscv_zvfbfmin) >> +#error "__riscv_zvfbfmin" >> +#endif >> + >> +#if defined(__riscv_v) >> +#error "__riscv_v" >> +#endif >> + >> +#if defined(__riscv_d) >> +#error "__riscv_d" >> +#endif >> + >> +#if defined(__riscv_c) >> +#error "__riscv_c" >> +#endif >> + >> +#if defined(__riscv_a) >> +#error "__riscv_a" >> +#endif >> + >> +  return 0; >> +} >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c >> b/gcc/testsuite/gcc.target/riscv/predef-33.c >> new file mode 100644 >> index 000..74d05bc9719 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c >> @@ -0,0 +1,43 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow >> -misa-spec=20191213" } */ >> + >> +int main () { >> + >> +#ifndef __riscv_arch_test >> +#error "__riscv_arch_test" >> +#endif >> + >> +#if __riscv_xlen != 64 >> +#error "__riscv_xlen" >> +#endif >> + >> +#if !defined(__riscv_i) >> +#error "__riscv_i" >> +#endif >> + >> +#if !defined(__riscv_f) >> +#error "__riscv_f" >> +#endif >> + >> +#if !defined(__riscv_d) >> +#error "__riscv_d" >> +#endif >> + >> +#if !defined(__riscv_v) >> +#error "__riscv_v" >> +#endif >> + >> +#if !defined(__riscv_zvfbfmin) >> +#error "__riscv_zvfbfmin" >> +#endif >> + >> +#if defined(__riscv_c) >> +#error "__riscv_c" >> +#endif >> + >> +#if defined(__riscv_a) >> +#error "__riscv_a" >> +#endif >> + >> +  return 0; >> +} > >Reviewed-by: Palmer Dabbelt Thank you for Palmer's code review   Thanks Xiao Zeng

Re: Re: [PING^1][PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

gt;, Palmer Dabbelt has already completed the review. > >But I will be available on reviewing the following real vector BF16 intrinsic >and auto-vectorization support. > Of course, in the upcoming patch support for BF16, we need to request your code review. >Thanks. > > > >

[PING^1][PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

This patch would like to add new sub extension (aka Zvfbfmin) to the -march= option. It introduces a new data type BF16. Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scena

[PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

This patch would like to add new sub extension (aka Zvfbfmin) to the -march= option. It introduces a new data type BF16. Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scena

Re: Re: [PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On Sat, Aug 05, 2023 at 05:31:00 AM  Jeff Law wrote: > >On 8/1/23 19:38, Xiao Zeng wrote: >> This patch recognizes Zicond patterns when the select pattern >> with condition eq or neq to 0 (using eq as an example), namely: >> >> 1 rd = (rs2 == 0) ? non-imm : 0 >&g

Re: [committed] [RISC-V] Avoid sub-word mode comparisons with Zicond

cc's passe. 6 I'm wondering about transforms like this: In test.c.c.301r.ira (insn 36 34 42 2 (set (reg:DI 153)         (if_then_else:DI (eq:DI (subreg:SI (reg:DI 145) 0)                 (const_int 0 [0]))             (reg:DI 149)             (const_int 0 [0]))) "test.c":4:12 13599 {*czero.nez.disi}      (expr_list:REG_DEAD (reg:DI 149)         (nil))) In test.c.c.302r.reload it becomes (insn 36 34 42 2 (set (reg:DI 11 a1 [153])         (if_then_else:DI (eq:DI (reg:SI 15 a5 [145])                 (const_int 0 [0]))             (reg:DI 10 a0 [149])             (const_int 0 [0]))) "test.c":4:12 13599 {*czero.nez.disi}      (nil)) Obviously, (subreg:SI (reg:DI 145) 0) is transformed into (reg:SI 15 a5 [145]) after passing through reload pass. This conversion is wrong, why did gcc not warn? 7 I'm not very familiar with reload pass, maybe someone can give me a brief introduction, or tell me where to find relevant information? Thanks.   Thanks Xiao Zeng

Re: [committed][RISC-V] Fix 20010221-1.c with zicond

o two of the patterns are just totally bogus as they are not >implementable with zicond.  They are removed.  The asm template for the >.opt3 pattern is fixed to use czero.nez and its name is changed to .opt2. > >This fixes the known issues with the zicond.md bits.  Onward to the rest >of the expansion work :-) > >Committed to the trunk, > >jeff > Yes, two of these four optimization patterns are wrong. In the wrong two optimization modes, I only considered the case of satisfying the ELSE branch, but in fact, like the correct two optimization modes, I should consider the case of satisfying both the THAN and ELSE branches. By the way, I was assigned other tasks during the week and didn't have time to reply to emails, sorry. Although I can't reply in time to the emails received from the gcc community, I will definitely reply when I am free. At the same time, I will improve my time management skills, keep the same frequency with the community as much as possible, and work better with everyone. Thanks Xiao Zeng

Re: Re: [PATCH V2] [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On Tue, Aug 01, 2023 at 02:06:00 PM Jeff Law wrote: > > > >On 7/29/23 03:13, Xiao Zeng wrote: >> This patch recognizes Zicond patterns when the select pattern >> with condition eq or neq to 0 (using eq as an example), namely: >> >> 1 rd = (rs2 == 0) ? non-im

[PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

This patch recognizes Zicond patterns when the select pattern with condition eq or neq to 0 (using eq as an example), namely: 1 rd = (rs2 == 0) ? non-imm : 0 2 rd = (rs2 == 0) ? non-imm : non-imm 3 rd = (rs2 == 0) ? reg : non-imm 4 rd = (rs2 == 0) ? reg : reg gcc/ChangeLog: * config/risc

Re: Re: [PATCH 0/5] Recognize Zicond extension

On Fri, Jul 28, 2023 at 11:03:00 PM  Jeff Law wrote: > > > >On 7/28/23 00:34, Xiao Zeng wrote: > >>>> >>>> Does that work for you? >>> I'm going to look at 3/5 today pretty closely.  Exposing zicond to >>> movcc is something we had

Re: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On Fri, Jul 28, 2023 at 11:09:00 PM  Jeff Law wrote: > > > >On 7/25/23 11:55, Andreas Schwab wrote: >> On Jul 19 2023, Xiao Zeng wrote: >> >>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >>> index 38d8eb2fcf5..7e6b24bd232 100644 >

Re: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On Sat, Jul 29, 2023 at 04:59:00 AM  Jeff Law wrote: > > > >On 7/19/23 04:11, Xiao Zeng wrote: > >> +  else if (TARGET_ZICOND >> +   && (code == EQ || code == NE) >> +   && GET_MODE_CLASS (mode) == MODE_INT) >> +  

[PATCH V2] [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

This patch recognizes Zicond patterns when the select pattern with condition eq or neq to 0 (using eq as an example), namely: 1 rd = (rs2 == 0) ? non-imm : 0 2 rd = (rs2 == 0) ? non-imm : non-imm 3 rd = (rs2 == 0) ? reg : non-imm 4 rd = (rs2 == 0) ? reg : reg gcc/ChangeLog: * config/risc

Re: Re: [PATCH 0/5] Recognize Zicond extension

On Thu, Jul 27, 2023 at 10:43:00 PM  Jeff Law wrote: > > > >On 7/27/23 02:43, Xiao Zeng wrote: > >> >> 2. According to your opinions, I have modified the code, but out of caution >> for upstream, I conducted a complete regression tests on patch V2, which took &g

Re: Re: [PATCH 0/5] Recognize Zicond extension

On Wed, Jul 26, 2023 at 01:51:00 AM  Jeff Law wrote: > > > >On 7/19/23 04:11, Xiao Zeng wrote: >> Hi all RISC-V folks: >> >> This series of patches completes support for the riscv architecture's >> Zicond standard extension instruction set. >> >&

Re: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On Wed, Jul 26, 2023 at 01:55:00 AM Andreas Schwab wrote: > >On Jul 19 2023, Xiao Zeng wrote: > >> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >> index 38d8eb2fcf5..7e6b24bd232 100644 >> --- a/gcc/config/riscv/riscv.cc >> +++ b/gcc/co

[PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

This patch completes the recognition of Zicond when the select pattern with condition eq or neq to 0 (using equality as an example), namely: 1 rd = (rs2 == 0) ? non-imm : 0 2 rd = (rs2 == 0) ? non-imm : non-imm 3 rd = (rs2 == 0) ? reg : non-imm 4 rd = (rs2 == 0) ? reg : reg gcc/ChangeLog:

[PATCH 1/5] [RISC-V] Recognize Zicond extension

This patch is the minimal support for Zicond extension, include the extension name, mask and target defination. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * config/riscv/riscv-opts.h (MASK_ZICOND): New mask. (TARGET_ZICOND): New target. gcc/tests

[PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution

This patch completes the recognition of conditional execution (using equality as an example), namely: 1 rd = (rc == 0) ? (rs1 arith_op rs2) : rs1 Here, arith_op represents the arithmetic operation symbol, which has 8 possibilities: + - | ^ << >>(Shift Right Arithmetic) >>(Shift Right Logical) &

[PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero

This patch completes the recognition of Zicond when the select pattern with condition eq or neq to non-zero (using equality as an example), namely: 1 rd = (rs2 == non-imm) ? 0 : rs1 2 rd = (rs2 == reg) ? 0 : rs1 At the same time, more Zicond non basic semantic test cases have been added. gcc/Cha

[PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics

This patch completes the recognition of the basic semantics defined in the spec, namely: Conditional zero, if condition is equal to zero rd = (rs2 == 0) ? 0 : rs1 Conditional zero, if condition is non zero rd = (rs2 != 0) ? 0 : rs1 gcc/ChangeLog: * config/riscv/riscv.md: Include zico

[PATCH 0/5] Recognize Zicond extension

icond-v1.0-rc2.pdf Prior to this, other community members have also done related work, as shown in: https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611767.html https://sourceware.org/pipermail/binutils/2023-January/125773.html Xiao Zeng (5): [RISC-V] Recognize Zicond extension [R