On Fri, Jul 28, 2023 at 11:09:00 PM Jeff Law <jeffreya...@gmail.com> wrote: > > > >On 7/25/23 11:55, Andreas Schwab wrote: >> On Jul 19 2023, Xiao Zeng wrote: >> >>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >>> index 38d8eb2fcf5..7e6b24bd232 100644 >>> --- a/gcc/config/riscv/riscv.cc >>> +++ b/gcc/config/riscv/riscv.cc >>> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int >>> outer_code, int opno ATTRIBUTE_UN >>> *total = COSTS_N_INSNS (1); >>> return true; >>> } >>> + else if (TARGET_ZICOND && outer_code == SET && >>> + ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == >>> const0_rtx) || >>> + (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == >>> const0_rtx) || >>> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) && >>> + XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) || >>> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) && >>> + XEXP (x, 2) == XEXP (XEXP (x, 0), 0)))) >> >> Line breaks before the operator, not after. >Also note that && GET_CODE (XEXP (x, 2)) && that appears twice.
This is an error that I will fix in patch[cost] and provide a detailed explanation. > >That just verifies the code isn't RTX_UNKNOWN which I suspect isn't what >the author intended. It probably needs to be adjusted for SUBREGs and >the pointer equality issues with REGs after reload. > >I'll take care of these goofs since the costing ought to be able to move >forward independently of the improvements Xiao made to generating >conditional move sequences. > >Jeff After V2-patch[3/5] is accepted, a patch[cost] will be submitted to provide detailed explanation of this issue. Of course, as Jeff mentioned, some issues will also be fixed. Thanks Xiao Zeng
