2023-12-13 11:55 Palmer Dabbelt <pal...@dabbelt.com> wrote:
>
>On Tue, 12 Dec 2023 19:24:51 PST (-0800), zengx...@eswincomputing.com wrote:
>> This patch would like to add new sub extension (aka Zvfbfmin) to the
>> -march= option. It introduces a new data type BF16.
>>
>> Depending on different usage scenarios, the Zvfbfmin extension may
>> depend on 'V' or 'Zve32f'. This patch only implements dependencies
>> in scenario of Embedded Processor. In scenario of Application
>> Processor, it is necessary to explicitly indicate the dependent
>> 'V' extension.
>>
>> You can locate more information about Zvfbfmin from below spec doc.
>>
>> https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc:
>> (riscv_implied_info): Add zvfbfmin item.
>> (riscv_ext_version_table): Ditto.
>> (riscv_ext_flag_table): Ditto.
>> * config/riscv/riscv.opt:
>> (MASK_ZVFBFMIN): New macro.
>> (MASK_VECTOR_ELEN_BF_16): Ditto.
>> (TARGET_ZVFBFMIN): Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/arch-31.c: New test.
>> * gcc.target/riscv/arch-32.c: New test.
>> * gcc.target/riscv/predef-32.c: New test.
>> * gcc.target/riscv/predef-33.c: New test.
>> ---
>> gcc/common/config/riscv/riscv-common.cc | 4 ++
>> gcc/config/riscv/riscv.opt | 4 ++
>> gcc/testsuite/gcc.target/riscv/arch-31.c | 5 +++
>> gcc/testsuite/gcc.target/riscv/arch-32.c | 5 +++
>> gcc/testsuite/gcc.target/riscv/predef-32.c | 43 ++++++++++++++++++++++
>> gcc/testsuite/gcc.target/riscv/predef-33.c | 43 ++++++++++++++++++++++
>> 6 files changed, 104 insertions(+)
>> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
>> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c
>> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-32.c
>> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-33.c
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc
>> b/gcc/common/config/riscv/riscv-common.cc
>> index 4d5a2f874a2..370d00b8f7a 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -151,6 +151,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>>
>> {"zfa", "f"},
>>
>> + {"zvfbfmin", "zve32f"},
>> {"zvfhmin", "zve32f"},
>> {"zvfh", "zve32f"},
>> {"zvfh", "zfhmin"},
>> @@ -313,6 +314,7 @@ static const struct riscv_ext_version
>> riscv_ext_version_table[] =
>>
>> {"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
>> + {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0},
>>
>> @@ -1657,6 +1659,7 @@ static const riscv_ext_flag_table_t
>> riscv_ext_flag_table[] =
>> {"zve64x", &gcc_options::x_riscv_vector_elen_flags,
>>MASK_VECTOR_ELEN_64},
>> {"zve64f", &gcc_options::x_riscv_vector_elen_flags,
>>MASK_VECTOR_ELEN_FP_32},
>> {"zve64d", &gcc_options::x_riscv_vector_elen_flags,
>>MASK_VECTOR_ELEN_FP_64},
>> + {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags,
>> MASK_VECTOR_ELEN_BF_16},
>> {"zvfhmin", &gcc_options::x_riscv_vector_elen_flags,
>>MASK_VECTOR_ELEN_FP_16},
>> {"zvfh", &gcc_options::x_riscv_vector_elen_flags,
>>MASK_VECTOR_ELEN_FP_16},
>>
>> @@ -1692,6 +1695,7 @@ static const riscv_ext_flag_table_t
>> riscv_ext_flag_table[] =
>>
>> {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>> {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
>> + {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
>> {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>> {"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
>>
>> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> index 59ce7106ecf..b7c0b72265e 100644
>> --- a/gcc/config/riscv/riscv.opt
>> +++ b/gcc/config/riscv/riscv.opt
>> @@ -285,6 +285,8 @@ Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags)
>>
>> Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)
>>
>> +Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)
>> +
>> TargetVariable
>> int riscv_zvl_flags
>>
>> @@ -366,6 +368,8 @@ Mask(ZFHMIN) Var(riscv_zf_subext)
>>
>> Mask(ZFH) Var(riscv_zf_subext)
>>
>> +Mask(ZVFBFMIN) Var(riscv_zf_subext)
>> +
>> Mask(ZVFHMIN) Var(riscv_zf_subext)
>>
>> Mask(ZVFH) Var(riscv_zf_subext)
>> diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c
>> b/gcc/testsuite/gcc.target/riscv/arch-31.c
>> new file mode 100644
>> index 00000000000..5180753b905
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
>> @@ -0,0 +1,5 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */
>> +int foo()
>> +{
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c
>> b/gcc/testsuite/gcc.target/riscv/arch-32.c
>> new file mode 100644
>> index 00000000000..49616832512
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c
>> @@ -0,0 +1,5 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */
>> +int foo()
>> +{
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c
>> b/gcc/testsuite/gcc.target/riscv/predef-32.c
>> new file mode 100644
>> index 00000000000..7417e0d996f
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/predef-32.c
>> @@ -0,0 +1,43 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow
>> -misa-spec=20191213" } */
>> +
>> +int main () {
>> +
>> +#ifndef __riscv_arch_test
>> +#error "__riscv_arch_test"
>> +#endif
>> +
>> +#if __riscv_xlen != 32
>> +#error "__riscv_xlen"
>> +#endif
>> +
>> +#if !defined(__riscv_i)
>> +#error "__riscv_i"
>> +#endif
>> +
>> +#if !defined(__riscv_f)
>> +#error "__riscv_f"
>> +#endif
>> +
>> +#if !defined(__riscv_zvfbfmin)
>> +#error "__riscv_zvfbfmin"
>> +#endif
>> +
>> +#if defined(__riscv_v)
>> +#error "__riscv_v"
>> +#endif
>> +
>> +#if defined(__riscv_d)
>> +#error "__riscv_d"
>> +#endif
>> +
>> +#if defined(__riscv_c)
>> +#error "__riscv_c"
>> +#endif
>> +
>> +#if defined(__riscv_a)
>> +#error "__riscv_a"
>> +#endif
>> +
>> + return 0;
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c
>> b/gcc/testsuite/gcc.target/riscv/predef-33.c
>> new file mode 100644
>> index 00000000000..74d05bc9719
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c
>> @@ -0,0 +1,43 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow
>> -misa-spec=20191213" } */
>> +
>> +int main () {
>> +
>> +#ifndef __riscv_arch_test
>> +#error "__riscv_arch_test"
>> +#endif
>> +
>> +#if __riscv_xlen != 64
>> +#error "__riscv_xlen"
>> +#endif
>> +
>> +#if !defined(__riscv_i)
>> +#error "__riscv_i"
>> +#endif
>> +
>> +#if !defined(__riscv_f)
>> +#error "__riscv_f"
>> +#endif
>> +
>> +#if !defined(__riscv_d)
>> +#error "__riscv_d"
>> +#endif
>> +
>> +#if !defined(__riscv_v)
>> +#error "__riscv_v"
>> +#endif
>> +
>> +#if !defined(__riscv_zvfbfmin)
>> +#error "__riscv_zvfbfmin"
>> +#endif
>> +
>> +#if defined(__riscv_c)
>> +#error "__riscv_c"
>> +#endif
>> +
>> +#if defined(__riscv_a)
>> +#error "__riscv_a"
>> +#endif
>> +
>> + return 0;
>> +}
>
>Reviewed-by: Palmer Dabbelt <pal...@rivosinc.com>
Thank you for Palmer's code review
Thanks
Xiao Zeng
