The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78580
The patch was successfully tested and bootstrapped on x86-64.
Committed to the trunk as rev. 243875.
Index: ChangeLog
===
--- ChangeLog (revision 2438
On 12/13/2016 05:05 PM, Eric Botcazou wrote:
Hi,
the Ada runtime library doesn't build on SPARC 32-bit with LRA because of an
ICE on a couple of files:
eric@polaris:~/build/gcc/sparc-sun-solaris2.10> gcc/gnat1 -I gcc/ada/rts -
quiet -dumpbase g-debpoo.adb -auxbase g-debpoo -O2 -gnatpg -fPIC -
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78671
The patch was successfully bootstrapped and tested on x86-64.
Committed as rev. 243462.
Index: ChangeLog
===
--- ChangeLog (revision 243461)
+++ ChangeL
On 12/01/2016 12:40 PM, Thomas Preudhomme wrote:
Hi,
When considering a candidate for rematerialization, LRA verifies if
the candidate clobbers a live register before going forward with the
rematerialization (see code starting with comment "Check clobbers do
not kill something living."). To
On 12/06/2016 01:10 PM, Bernd Schmidt wrote:
In this PR, we have two registers with "replace" set for them. When
processing the first, we delete its setter, which happens to be the
only use of the other register. In the second iteration we then assert
that the other register has a use, which
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77856
The bug was in a new code for invariant inheritance I added this summer.
The patch was successfully bootstrapped and tested on x86-64.
Committed as rev. 243038.
Index: ChangeLog
=
Uros pointed me out that I should use another target for the PR test.
Here is the patch committed as rev. 242881.
2016-11-25 Vladimir Makarov
PR rtl-optimization/77541
* gcc.target/i386/pr77541.c: Change target to int128.
Index: gcc.target/i386/pr77541.c
===
The patch in the attachment fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77541
The patch was successfully tested and bootstrapped on x86-64.
Committed as rev. 242848
Index: ChangeLog
===
--- ChangeLog (revision 242713)
+++
On 11/10/2016 11:27 AM, Andrew Senkevich wrote:
Hi,
this patch enabled AVX512_4FMAPS and AVX512_4VNNIW instructions.
It requires additional patch for register allocator from Vladimir
Makarov to be committed before.
I've just committed the necessary patch.
Hi, the following patch is necessary for generation of new Intel insns
requiring 4 aligned zmm regs.
Committed as rev. 242043.
Index: ChangeLog
===
--- ChangeLog (revision 242040)
+++ ChangeLog (working copy)
@@ -1,3 +1,12 @@
+2016
On 11/04/2016 12:18 PM, Pat Haugen wrote:
While working to get -fsched-pressure profitable on PowerPC, one of the things
I noticed causing problems was the selection of pressure classes. Understanding
that getting the computation of pressure classes correct for all targets in the
machine ind
I've created a new branch ira-select for work on experimental
algorithm of calculations of pseudo register classes.
The current algorithm in IRA (file ira-costs.c) was adopted from old
regclass.c. It has a big disadvantage which is in ignoring a fact
that operands should be in the same alternati
On 09/26/2016 09:55 AM, Bernd Edlinger wrote:
Bootstrapped and reg-tested on x86_64-pc-linux-gnu.
Is it OK for trunk?
Yes. Thank you for working on the problem, Bernd.
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77416
The patch was tested on ppc64 and bootstrapped on x86-64.
Committed as rev. 240247.
Index: ChangeLog
===
--- ChangeLog (revision 240246)
+++ ChangeLog
On 07/08/2016 11:07 AM, Thomas Preudhomme wrote:
Hi,
While investigating the root cause a testsuite regression for the
ARM/embedded-5-branch GCC in gcc.dg/vect/slp-perm-5.c, we found that the bug
seems to also affect trunk. The bug manifests itself as an ICE in cselib due to
a parallel insn wi
On 09/06/2016 11:22 AM, Matthew Fortune wrote:
There is an implementation that optimises a single set but not one for
a REG_EQUAL. Do you have any recollection of this code and do you think
there was a reason you didn't implement the REG_EQUAL case? Either way
any advice on my approach is welco
On 08/09/2016 04:41 AM, Alan Modra wrote:
On Tue, Aug 02, 2016 at 11:02:56PM +0930, Alan Modra wrote:
This is a patch for a problem in lra, triggered by the rs6000
backend not allowing SImode in floating point registers.
Ping? https://gcc.gnu.org/ml/gcc-patches/2016-08/msg00113.html
Note th
On 08/08/2016 01:04 PM, Jiong Wang wrote:
[...]
There is very tiny performance regression on SPEC2K6INT
464.h264ref. Checking the codegen, there are some bad instruction
scheduling, it looks to me caused by REG_ALLOC_ORDER is not used
consistently inside IRA that parts of the code are using new
On 08/06/2016 03:11 PM, Jakub Jelinek wrote:
On Wed, Aug 03, 2016 at 02:59:30PM -0400, Vladimir N Makarov wrote:
--- lra-spills.c(revision 239000)
+++ lra-spills.c(working copy)
@@ -686,16 +686,40 @@ return_regno_p (unsigned int regno)
return false;
}
-/* Return true
This is a patch to fix some testsuite failures reported for arm:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69847
The patch was bootstrapped and tested on x86-64 and ppc64.
Committed as rev. 239180.
Index: ChangeLog
===
---
The following patch fixes a bug reported by Uros on a bootstrap with
golang:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72778
The patch was bootstrapped on x86-64 with golang.
Committed as rev. 239091.
Index: ChangeLog
===
-
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70689
The patch was successfully tested and bootstrapped on x86/x86-64.
Committed to the trunk as rev. 235184.
Index: ChangeLog
===
--- ChangeLog (revision 2351
22 matches
Mail list logo
