On 08/08/2016 01:04 PM, Jiong Wang wrote:
[...]
There is very tiny performance regression on SPEC2K6INT
464.h264ref. Checking the codegen, there are some bad instruction
scheduling, it looks to me caused by REG_ALLOC_ORDER is not used
consistently inside IRA that parts of the code are using new allocation
order while some other parts are still using original order.
I see in ira.c:setup_class_hard_regs we are checking whether
REG_ALLOC_ORDER is defined:
#ifdef REG_ALLOC_ORDER
hard_regno = reg_alloc_order[i];
#else
hard_regno = i;
#endif
but in ira-color.c:assign_hard_reg, there is no similar check:
/* We don't care about giving callee saved registers to allocnos no
living through calls because call clobbered registers are
allocated first (it is usual practice to put them first in
REG_ALLOC_ORDER). */
mode = ALLOCNO_MODE (a);
for (i = 0; i < class_size; i++)
{
hard_regno = ira_class_hard_regs[aclass][i];
We might want to use reg_alloc_order to map above "i" if REG_ALLOC_ORDER is
defined?
Vlad, any comments?
The order is already present in ira_class_hard_regs. So there is no
need to use it in ira-color.c::assign_hard_reg.
