On 16/06/2017 15:37:18, Richard Earnshaw (lists) wrote:
> On 16/06/17 08:48, Prakhar Bahuguna wrote:
> > On 15/06/2017 17:23:43, Richard Earnshaw (lists) wrote:
> >> On 14/06/17 10:35, Prakhar Bahuguna wrote:
> >>> The ARM ACLE defines the __ARM_FEATURE_COPR
Patch updated with code style fixes.
--
Prakhar Bahuguna
>From f1d76a6309a1fe16711b800507938eaa4f78852e Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna
Date: Tue, 2 May 2017 13:43:40 +0100
Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature
macro
---
gcc/config/
On 15/06/2017 17:23:43, Richard Earnshaw (lists) wrote:
> On 14/06/17 10:35, Prakhar Bahuguna wrote:
> > The ARM ACLE defines the __ARM_FEATURE_COPROC macro which indicates which
> > coprocessor intrinsics are available for the target. If
> > __ARM_FEATURE_COPROC is
> >
Prakhar Bahuguna
* config/arm/arm-c.c (arm_cpu_builtins): New block to define
__ARM_FEATURE_COPROC according to support.
2017-06-14 Prakhar Bahuguna
* gcc/testsuite/gcc.target/arm/acle/cdp.c: Add feature macro bitmap
test.
* gcc/testsuite/gcc.target/arm
ter on in the split1
stage, this veneer insn pattern will be turned into normal thumb1_addsi3_addgeu
pattern for future code generation.
gcc/ChangeLog:
2017-06-05 Prakhar Bahuguna
* config/arm/arm.md (cstoresi_leu_thumb1): New define_insn_and_split
pattern.
(cstoresi4): Use ab
s a result. The patch now emits a diagnostic in TLS-enabled
toolchains if a TLS symbol is found when -mpure-code or -mslow-flash-data are
enabled.
2017-06-02 Prakhar Bahuguna
Backport from mainline
2017-05-05 Andre Vieira
Prakhar Bahuguna
gcc/
On 01/06/2017 07:15:47, Richard Sandiford wrote:
> Prakhar Bahuguna writes:
> > On 31/05/2017 14:11:43, Richard Sandiford wrote:
> >> Prakhar Bahuguna writes:
> >> > On 31/05/2017 09:19:40, Richard Sandiford wrote:
> >> >> const_ints are supposed to
On 31/05/2017 14:11:43, Richard Sandiford wrote:
> Prakhar Bahuguna writes:
> > On 31/05/2017 09:19:40, Richard Sandiford wrote:
> >> const_ints are supposed to be stored in sign-extended form, so a 32-bit
> >> integer with the MSB set should be 0x8000|x i
using negative doubles and
floats but haven't succeeded.
Thanks,
--
Prakhar Bahuguna
We have decided to apply the following patch to ARM/embedded-7-branch and
ARM/embedded-6-branch to enable Purecode support for ARMv8-M Baseline targets.
ChangeLog:
2017-05-31 Prakhar Bahuguna
Backport from mainline
2017-05-04 Prakhar Bahuguna
Andre
I have added myself to the Write After Approval section of the MAINTAINERS
list.
ChangeLog:
2017-05-31 Prakhar Bahuguna
* MAINTAINERS: Add self to Write After Approval
--
Prakhar Bahuguna
On 30/05/2017 14:11:22, Christophe Lyon wrote:
> On 30 May 2017 at 09:44, Prakhar Bahuguna wrote:
> > On 29/05/2017 14:23:05, Christophe Lyon wrote:
> >> On 19 May 2017 at 14:29, Prakhar Bahuguna wrote:
> >> > On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
>
On 29/05/2017 14:23:05, Christophe Lyon wrote:
> On 19 May 2017 at 14:29, Prakhar Bahuguna wrote:
> > On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
> >> tls-disable-literal-pool.c should only be run if the toolchain and target
> >> support native thread-local stora
s a result. The patch now emits a diagnostic in TLS-enabled
toolchains if a TLS symbol is found when -mpure-code or -mslow-flash-data are
enabled.
2017-05-25 Prakhar Bahuguna
Backport from mainline
2017-05-05 Andre Vieira
Prakhar Bahuguna
gcc/
On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
> tls-disable-literal-pool.c should only be run if the toolchain and target
> support native thread-local storage rather than emulated TLS. This patch also
> improves the matching of the error message.
>
> testsuite/ChangeLog:
On 11/05/2017 10:58:52, Kyrill Tkachov wrote:
>
> On 11/05/17 10:56, Prakhar Bahuguna wrote:
> > Resolve the regressions introduced on non-Thumb targets by the Purecode for
> > ARMv8-M Baseline patch. The TARGET_32BIT conditional has been re-added to
> > the
> >
tls-disable-literal-pool.c should only be run if the toolchain and target
support native thread-local storage rather than emulated TLS. This patch also
improves the matching of the error message.
testsuite/ChangeLog:
2017-05-11 Prakhar Bahuguna
* gcc.target/arm/tls-disable-literal
Resolve the regressions introduced on non-Thumb targets by the Purecode for
ARMv8-M Baseline patch. The TARGET_32BIT conditional has been re-added to the
movsi expander and splitter in addition to TARGET_HAVE_MOVT.
gcc/ChangeLog:
2017-05-11 Prakhar Bahuguna
* config/arm/arm.md (movsi
On 03/05/2017 11:30:13, Richard Earnshaw (lists) wrote:
> On 20/04/17 10:54, Prakhar Bahuguna wrote:
> > [ARM] PR71607: Fix ICE when loading constant
> >
> > gcc/ChangeLog:
> >
> > 2017-04-18 Andre Vieira
> > Prakhar Bahuguna
> >
> &
On 02/05/2017 16:20:50, Ramana Radhakrishnan wrote:
> On Tue, May 02, 2017 at 11:45:48AM +0100, Prakhar Bahuguna wrote:
> > This patch adds support for purecode to ARMv8-M Baseline, in addition to the
> > existing support for ARMv7-M and ARMv8-M Mainline.
> >
> > gcc/
This patch adds support for purecode to ARMv8-M Baseline, in addition to the
existing support for ARMv7-M and ARMv8-M Mainline.
gcc/ChangeLog:
2017-01-11 Prakhar Bahuguna
Andre Simoes Dias Vieira
* config/arm/arm.md (movsi): Change TARGET_32BIT to TARGET_HAVE_MOVT
[ARM] PR71607: Fix ICE when loading constant
gcc/ChangeLog:
2017-04-18 Andre Vieira
Prakhar Bahuguna
PR target/71607
* config/arm/arm.md (use_literal_pool): Removes.
(64-bit immediate split): No longer takes cost into consideration
if
On 22/03/2017 10:46:30, Prakhar Bahuguna wrote:
> The GCC documentation in section 6.60.8 ARM Floating Point Status and Control
> Intrinsics states that the FPSCR register can be read and written to using the
> intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr. However, th
not recognised.
This patch corrects the intrinsic names to match the documentation, and adds
tests to verify these intrinsics generate the correct instructions.
Testing done: Ran regression tests on arm-none-eabi for Cortex-M4.
2017-03-09 Prakhar Bahuguna
gcc/ChangeLog:
* gcc/config
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