On 02/05/2017 16:20:50, Ramana Radhakrishnan wrote:
> On Tue, May 02, 2017 at 11:45:48AM +0100, Prakhar Bahuguna wrote:
> > This patch adds support for purecode to ARMv8-M Baseline, in addition to the
> > existing support for ARMv7-M and ARMv8-M Mainline.
> >
> > gcc/ChangeLog:
> >
> > 2017-01-11 Prakhar Bahuguna <prakhar.bahug...@arm.com>
> > Andre Simoes Dias Vieira <andre.simoesdiasvie...@arm.com>
> >
> > * config/arm/arm.md (movsi): Change TARGET_32BIT to TARGET_HAVE_MOVT.
> > (movt splitter): Likewise.
> > * config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2
> > to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check.
> > (const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else
> > block for Thumb-1 with MOVT.
> > (thumb2_legitimate_address_p): Move code block ...
> > (can_avoid_literal_pool_for_label_p): ... into this new function.
> > (thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and
> > literal pool.
> > (thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT
> >
> > doc/ChangeLog:
> >
> > 2017-01-11 Prakhar Bahuguna <prakhar.bahug...@arm.com>
> > Andre Simoes Dias Vieira <andre.simoesdiasvie...@arm.com>
> >
> > * invoke.texi (-mpure-code): Change "ARMv7-M targets" for
> > "Thumb-only targets with the MOVT instruction".
> >
> > testsuite/ChangeLog:
> >
> > 2017-01-11 Prakhar Bahuguna <prakhar.bahug...@arm.com>
> > Andre Simoes Dias Vieira <andre.simoesdiasvie...@arm.com>
> >
> > * gcc.target/arm/pure-code/pure-code.exp: Add conditional for
> > check_effective_target_arm_thumb1_movt_ok.
> >
> > Testing done: Ran regression tests for arm-eabi-none targeting Cortex-M23,
> > both
> > with and without -mpure-code.
> >
> > Okay for stage 1?
> >
> > --
> >
> > Prakhar Bahuguna
>
> > From a77336404fdbdc9ed9b836e4e164803915aa3b22 Mon Sep 17 00:00:00 2001
> > From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
> > Date: Wed, 15 Mar 2017 10:25:03 +0000
> > Subject: [PATCH] Enable Purecode for ARMv8-M Baseline.
> >
> > ---
> > gcc/config/arm/arm.c | 77
> > ++++++++++++++--------
> > gcc/config/arm/arm.md | 6 +-
> > gcc/doc/invoke.texi | 3 +-
> > .../gcc.target/arm/pure-code/pure-code.exp | 5 +-
> > 4 files changed, 57 insertions(+), 34 deletions(-)
> >
> > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> > index d719020dcde..1088895e7e5 100644
> > --- a/gcc/config/arm/arm.c
> > +++ b/gcc/config/arm/arm.c
> > @@ -2833,16 +2833,15 @@ arm_option_check_internal (struct gcc_options *opts)
> > flag_pic = 0;
> > }
> >
> > - /* We only support -mslow-flash-data on armv7-m targets. */
> > - if (target_slow_flash_data
> > - && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
> > - || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
> > - error ("-mslow-flash-data only supports non-pic code on armv7-m
> > targets");
> > -
> > - /* We only support pure-code on Thumb-2 M-profile targets. */
> > - if (target_pure_code
> > - && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON))
> > - error ("-mpure-code only supports non-pic code on armv7-m targets");
> > + /* We only support -mpure-code and -mslow-flash-data on Thumb-only
> > targets
> > + with MOVT. */
>
>
> It would be good to support this with movw / movt but without
> new relocations it's not possible.
>
>
>
> > + if ((target_pure_code || target_slow_flash_data)
> > + && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
> > + {
> > + const char *flag = (target_pure_code ? "-mpure-code" :
> > "-mslow-flash-data");
>
> Check line length here.
>
> const char *flag = (target_pure_code ? "-mpure-code"
> : "-mslow-flash-data");
>
> > + error ("%s only supports non-pic code on Thumb-only targets with the
> > "
> > + "MOVT instruction", flag);
>
> I'd prefer the error message to be direct and say
> "M profile targets" instead of "Thumb-only targets" ?
>
>
> > + }
>
>
>
> >
> > }
> >
> > @@ -4077,7 +4076,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
> > || (i & ~0xfc000003) == 0))
> > return TRUE;
> > }
> > - else
> > + else if (TARGET_THUMB2)
> > {
> > HOST_WIDE_INT v;
> >
> > @@ -4093,6 +4092,14 @@ const_ok_for_arm (HOST_WIDE_INT i)
> > if (i == v)
> > return TRUE;
> > }
> > + else if (TARGET_HAVE_MOVT)
> > + {
> > + /* Thumb-1 Targets with MOVT. */
> > + if (i > 0xffff)
> > + return FALSE;
> > + else
> > + return TRUE;
> > + }
> >
> > return FALSE;
> > }
> > @@ -7736,6 +7743,32 @@ arm_legitimate_address_outer_p (machine_mode mode,
> > rtx x, RTX_CODE outer,
> > return 0;
> > }
> >
> > +/* Return true if we can avoid creating a constant pool entry for x. */
> > +bool
> > +can_avoid_literal_pool_for_label_p (rtx x)
>
> This can be static, no ?
>
> > +{
> > + /* Normally we can assign constant values to target registers without
> > + the help of constant pool. But there are cases we have to use
> > constant
> > + pool like:
> > + 1) assign a label to register.
> > + 2) sign-extend a 8bit value to 32bit and then assign to register.
> > +
> > + Constant pool access in format:
> > + (set (reg r0) (mem (symbol_ref (".LC0"))))
> > + will cause the use of literal pool (later in function arm_reorg).
> > + So here we mark such format as an invalid format, then the compiler
> > + will adjust it into:
> > + (set (reg r0) (symbol_ref (".LC0")))
> > + (set (reg r0) (mem (reg r0))).
> > + No extra register is required, and (mem (reg r0)) won't cause the use
> > + of literal pools. */
> > + if (arm_disable_literal_pool && GET_CODE (x) == SYMBOL_REF
> > + && CONSTANT_POOL_ADDRESS_P (x))
> > + return 1;
> > + return 0;
> > +}
> > +
> > +
> > /* Return nonzero if X is a valid Thumb-2 address operand. */
> > static int
> > thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
> > @@ -7799,23 +7832,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx
> > x, int strict_p)
> > && thumb2_legitimate_index_p (mode, xop0, strict_p)));
> > }
> >
> > - /* Normally we can assign constant values to target registers without
> > - the help of constant pool. But there are cases we have to use
> > constant
> > - pool like:
> > - 1) assign a label to register.
> > - 2) sign-extend a 8bit value to 32bit and then assign to register.
> > -
> > - Constant pool access in format:
> > - (set (reg r0) (mem (symbol_ref (".LC0"))))
> > - will cause the use of literal pool (later in function arm_reorg).
> > - So here we mark such format as an invalid format, then the compiler
> > - will adjust it into:
> > - (set (reg r0) (symbol_ref (".LC0")))
> > - (set (reg r0) (mem (reg r0))).
> > - No extra register is required, and (mem (reg r0)) won't cause the use
> > - of literal pools. */
> > - else if (arm_disable_literal_pool && code == SYMBOL_REF
> > - && CONSTANT_POOL_ADDRESS_P (x))
> > + else if (can_avoid_literal_pool_for_label_p (x))
> > return 0;
> >
> > else if (GET_MODE_CLASS (mode) != MODE_FLOAT
> > @@ -8094,6 +8111,9 @@ thumb1_index_register_rtx_p (rtx x, int strict_p)
> > int
> > thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
> > {
> > + if (TARGET_HAVE_MOVT && can_avoid_literal_pool_for_label_p (x))
> > + return 0;
> > +
> > /* ??? Not clear if this is right. Experiment. */
> > if (GET_MODE_SIZE (mode) < 4
> > && !(reload_in_progress || reload_completed)
> > @@ -8706,6 +8726,7 @@ thumb_legitimate_constant_p (machine_mode mode
> > ATTRIBUTE_UNUSED, rtx x)
> > return (CONST_INT_P (x)
> > || CONST_DOUBLE_P (x)
> > || CONSTANT_ADDRESS_P (x)
> > + || (TARGET_HAVE_MOVT && GET_CODE (x) == SYMBOL_REF)
> > || flag_pic);
> > }
> >
> > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> > index 21cfe3a4c31..d50059b28ab 100644
> > --- a/gcc/config/arm/arm.md
> > +++ b/gcc/config/arm/arm.md
> > @@ -5972,7 +5972,7 @@
> > {
> > rtx base, offset, tmp;
> >
> > - if (TARGET_32BIT)
> > + if (TARGET_HAVE_MOVT)
> > {
> > /* Everything except mem = const or mem = mem can be done easily. */
> > if (MEM_P (operands[0]))
> > @@ -5996,7 +5996,7 @@
> > }
> > }
> > }
> > - else /* TARGET_THUMB1... */
> > + else /* Target doesn't have MOVT... */
> > {
> > if (can_create_pseudo_p ())
> > {
> > @@ -6096,7 +6096,7 @@
> > (define_split
> > [(set (match_operand:SI 0 "arm_general_register_operand" "")
> > (match_operand:SI 1 "const_int_operand" ""))]
> > - "TARGET_32BIT
> > + "TARGET_HAVE_MOVT
> > && (!(const_ok_for_arm (INTVAL (operands[1]))
> > || const_ok_for_arm (~INTVAL (operands[1]))))"
> > [(clobber (const_int 0))]
> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index 0eeea7b3b87..283ce5001ee 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -15454,7 +15454,8 @@ by default.
> > Do not allow constant data to be placed in code sections.
> > Additionally, when compiling for ELF object format give all text sections
> > the
> > ELF processor-specific section attribute @code{SHF_ARM_PURECODE}. This
> > option
> > -is only available when generating non-pic code for ARMv7-M targets.
> > +is only available when generating non-pic code for Thumb-only targets with
> > the
> > +MOVT instruction.
>
> M profile targets with the MOVT instruction ?
>
> >
> > @item -mcmse
> > @opindex mcmse
> > diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
> > b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
> > index 6a5dc552bf3..a5109231926 100644
> > --- a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
> > +++ b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
> > @@ -26,8 +26,9 @@ if ![info exists DEFAULT_CFLAGS] then {
> > }
> >
> > # The -mpure-code option is only available for M-profile targets that
> > support
> > -# thumb2.
> > -if {[check_effective_target_arm_thumb2_ok]
> > +# the MOVT instruction.
> > +if {([check_effective_target_arm_thumb2_ok]
> > + || [check_effective_target_arm_thumb1_movt_ok])
> > && [check_effective_target_arm_cortex_m]} then {
> > # Initialize `dg'.
> > dg-init
> > --
> > 2.11.0
> >
>
>
> Otherwise ok. Please respin and test with an armhf thumb32 bootstrap
> and regression test run.
>
> regards
> Ramana
I've respun this patch with the suggested changes, along with a new changelog
for docs:
doc/ChangeLog:
2017-01-11 Prakhar Bahuguna <prakhar.bahug...@arm.com>
Andre Simoes Dias Vieira <andre.simoesdiasvie...@arm.com>
* invoke.texi (-mpure-code): Change "ARMv7-M targets" for
"M-profile targets with the MOVT instruction".
--
Prakhar Bahuguna
>From e0f62c9919ceb9cfc6b4cc49615fb7188ae50519 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Wed, 15 Mar 2017 10:25:03 +0000
Subject: [PATCH] Enable Purecode for ARMv8-M Baseline.
---
gcc/config/arm/arm.c | 78 ++++++++++++++--------
gcc/config/arm/arm.md | 6 +-
gcc/doc/invoke.texi | 3 +-
.../gcc.target/arm/pure-code/pure-code.exp | 5 +-
4 files changed, 58 insertions(+), 34 deletions(-)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 83914913433..e0a7cabcb2e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2833,16 +2833,16 @@ arm_option_check_internal (struct gcc_options *opts)
flag_pic = 0;
}
- /* We only support -mslow-flash-data on armv7-m targets. */
- if (target_slow_flash_data
- && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
- || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
- error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
-
- /* We only support pure-code on Thumb-2 M-profile targets. */
- if (target_pure_code
- && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON))
- error ("-mpure-code only supports non-pic code on armv7-m targets");
+ /* We only support -mpure-code and -mslow-flash-data on M-profile targets
+ with MOVT. */
+ if ((target_pure_code || target_slow_flash_data)
+ && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
+ {
+ const char *flag = (target_pure_code ? "-mpure-code" :
+ "-mslow-flash-data");
+ error ("%s only supports non-pic code on M-profile targets with the "
+ "MOVT instruction", flag);
+ }
}
@@ -4077,7 +4077,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
|| (i & ~0xfc000003) == 0))
return TRUE;
}
- else
+ else if (TARGET_THUMB2)
{
HOST_WIDE_INT v;
@@ -4093,6 +4093,14 @@ const_ok_for_arm (HOST_WIDE_INT i)
if (i == v)
return TRUE;
}
+ else if (TARGET_HAVE_MOVT)
+ {
+ /* Thumb-1 Targets with MOVT. */
+ if (i > 0xffff)
+ return FALSE;
+ else
+ return TRUE;
+ }
return FALSE;
}
@@ -7736,6 +7744,32 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx
x, RTX_CODE outer,
return 0;
}
+/* Return true if we can avoid creating a constant pool entry for x. */
+static bool
+can_avoid_literal_pool_for_label_p (rtx x)
+{
+ /* Normally we can assign constant values to target registers without
+ the help of constant pool. But there are cases we have to use constant
+ pool like:
+ 1) assign a label to register.
+ 2) sign-extend a 8bit value to 32bit and then assign to register.
+
+ Constant pool access in format:
+ (set (reg r0) (mem (symbol_ref (".LC0"))))
+ will cause the use of literal pool (later in function arm_reorg).
+ So here we mark such format as an invalid format, then the compiler
+ will adjust it into:
+ (set (reg r0) (symbol_ref (".LC0")))
+ (set (reg r0) (mem (reg r0))).
+ No extra register is required, and (mem (reg r0)) won't cause the use
+ of literal pools. */
+ if (arm_disable_literal_pool && GET_CODE (x) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (x))
+ return 1;
+ return 0;
+}
+
+
/* Return nonzero if X is a valid Thumb-2 address operand. */
static int
thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
@@ -7799,23 +7833,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x,
int strict_p)
&& thumb2_legitimate_index_p (mode, xop0, strict_p)));
}
- /* Normally we can assign constant values to target registers without
- the help of constant pool. But there are cases we have to use constant
- pool like:
- 1) assign a label to register.
- 2) sign-extend a 8bit value to 32bit and then assign to register.
-
- Constant pool access in format:
- (set (reg r0) (mem (symbol_ref (".LC0"))))
- will cause the use of literal pool (later in function arm_reorg).
- So here we mark such format as an invalid format, then the compiler
- will adjust it into:
- (set (reg r0) (symbol_ref (".LC0")))
- (set (reg r0) (mem (reg r0))).
- No extra register is required, and (mem (reg r0)) won't cause the use
- of literal pools. */
- else if (arm_disable_literal_pool && code == SYMBOL_REF
- && CONSTANT_POOL_ADDRESS_P (x))
+ else if (can_avoid_literal_pool_for_label_p (x))
return 0;
else if (GET_MODE_CLASS (mode) != MODE_FLOAT
@@ -8094,6 +8112,9 @@ thumb1_index_register_rtx_p (rtx x, int strict_p)
int
thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
{
+ if (TARGET_HAVE_MOVT && can_avoid_literal_pool_for_label_p (x))
+ return 0;
+
/* ??? Not clear if this is right. Experiment. */
if (GET_MODE_SIZE (mode) < 4
&& !(reload_in_progress || reload_completed)
@@ -8706,6 +8727,7 @@ thumb_legitimate_constant_p (machine_mode mode
ATTRIBUTE_UNUSED, rtx x)
return (CONST_INT_P (x)
|| CONST_DOUBLE_P (x)
|| CONSTANT_ADDRESS_P (x)
+ || (TARGET_HAVE_MOVT && GET_CODE (x) == SYMBOL_REF)
|| flag_pic);
}
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 21cfe3a4c31..d50059b28ab 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5972,7 +5972,7 @@
{
rtx base, offset, tmp;
- if (TARGET_32BIT)
+ if (TARGET_HAVE_MOVT)
{
/* Everything except mem = const or mem = mem can be done easily. */
if (MEM_P (operands[0]))
@@ -5996,7 +5996,7 @@
}
}
}
- else /* TARGET_THUMB1... */
+ else /* Target doesn't have MOVT... */
{
if (can_create_pseudo_p ())
{
@@ -6096,7 +6096,7 @@
(define_split
[(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_32BIT
+ "TARGET_HAVE_MOVT
&& (!(const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1]))))"
[(clobber (const_int 0))]
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 438e553b340..68a558e9992 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15421,7 +15421,8 @@ by default.
Do not allow constant data to be placed in code sections.
Additionally, when compiling for ELF object format give all text sections the
ELF processor-specific section attribute @code{SHF_ARM_PURECODE}. This option
-is only available when generating non-pic code for ARMv7-M targets.
+is only available when generating non-pic code for M-profile targets with the
+MOVT instruction.
@item -mcmse
@opindex mcmse
diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
index 6a5dc552bf3..a5109231926 100644
--- a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
+++ b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
@@ -26,8 +26,9 @@ if ![info exists DEFAULT_CFLAGS] then {
}
# The -mpure-code option is only available for M-profile targets that support
-# thumb2.
-if {[check_effective_target_arm_thumb2_ok]
+# the MOVT instruction.
+if {([check_effective_target_arm_thumb2_ok]
+ || [check_effective_target_arm_thumb1_movt_ok])
&& [check_effective_target_arm_cortex_m]} then {
# Initialize `dg'.
dg-init
--
2.11.0
