-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.
Signed-off-by: Edwin Lu
---
v2: fix ztso mappings
- Removed .aq annotation on load acquire
- Removed .rl annotation on store release
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config
-cst.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: New test.
* gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv.opt| 2 +
gcc
When the dg brackets were added, they forgot to add the brackets for the
scan-assembler-times directive.
Committed as obvious.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Fix typo
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls
On 2/24/2025 4:34 PM, Jeff Law wrote:
On 2/24/25 5:07 PM, Edwin Lu wrote:
See [1] thread for original patch which spawned this one.
We are currently seeing the following code where we perform a vsetvl
before a branching instruction against the avl.
vsetvli a5,a1,e32,m1,tu,ma
): Define Hook.
* config/riscv/riscv.opt: New flag.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Signed-off-by: Edwin Lu
Co-authored-by: Palmer Dabbelt
---
gcc/config/riscv/riscv.cc | 103 ++
gcc/config/r
LATE_INSN): Implement.
* config/riscv/riscv.opt: Add temporary opt.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Signed-off-by: Edwin Lu
---
V2: add testcase
V3: add opt flag to test performance
---
gcc/config/riscv/riscv.cc
On 2/13/2025 4:12 AM, Vineet Gupta wrote:
On 2/13/25 14:17, Robin Dapp wrote:
Other thoughts?
The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
we can't/don't model in the pipeline, but I have no idea how to model
the VL=0 case there.
Maybe so, but what Edwin is doing
igned-off-by: Edwin Lu
---
Changes in V2:
- Add testcase
---
gcc/config/riscv/riscv.cc | 20 +++
.../gcc.target/riscv/rvv/vsetvl/pr117974.c| 16 +++
2 files changed, 36 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl
tcase ?
juzhe.zh...@rivai.ai
*From:* Edwin Lu <mailto:e...@rivosinc.com>
*Date:* 2025-02-13 07:27
*To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* gnu-toolchain <mailto:gnu-toolch...@rivosinc.com>; vineetg
<mailto:vine...@rivosinc.com>; juzhe.zhong
cessarily updating the vinfo at the end of a basic block.
PR/117974
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_can_speculate_insn):
(TARGET_SCHED_CAN_SPECULATE_INSN): Implement.
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 20 +++
Thanks! Committed.
Edwin
On 1/9/2025 1:04 PM, Jeff Law wrote:
On 1/9/25 11:33 AM, Edwin Lu wrote:
The effective-target selector for riscv on sync_char_short did not
check to see if atomics were enabled. As a result, these test cases were
ran on targets without the a extension. Add
: Fix effective target sync_char_short
for riscv*-*-*
Signed-off-by: Edwin Lu
---
gcc/testsuite/lib/target-supports.exp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index a89f531f887
: Fix selector.
* gcc.target/riscv/crc-builtin-zbc64.c: Ditto.
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/crc-builtin-zbc32.c | 2 +-
gcc/testsuite/gcc.target/riscv/crc-builtin-zbc64.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite
Pushed.
Edwin
On 11/19/2024 1:11 PM, Jeff Law wrote:
On 11/19/24 2:08 PM, Edwin Lu wrote:
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr117595.c: Restrict to non vector targets.
Signed-off-by: Edwin
.
Signed-off-by: Edwin Lu
---
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
I took a look at the CI errors today since I remember Jeff checking the
CI output. I don't remember if the errors were the main things blocking
the patch or if there just wasn't any follow up.
I'll look into having the CI output some additional test log information
to make understanding failur
Committed!
Edwin
On 11/11/2024 11:02 AM, Jeff Law wrote:
On 11/11/24 11:16 AM, Edwin Lu wrote:
Since r15-4981-g5c34f02ba7e these tests have been failing on vector
targets with excess errors due to the new deprecation warning message.
Remove the header.
gcc/testsuite/ChangeLog:
* g
.
* g++.target/riscv/rvv/base/bug-6.C: Ditto.
* g++.target/riscv/rvv/base/bug-7.C: Ditto.
* g++.target/riscv/rvv/base/bug-8.C: Ditto.
* g++.target/riscv/rvv/base/bug-9.C: Ditto.
Signed-off-by: Edwin Lu
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-10.C | 1 -
gcc/testsuite
From: Greg McGary
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes,
vec_mask_len_store_lanes):
On 8/22/2024 5:35 AM, Richard Biener wrote:
On Thu, Aug 22, 2024 at 1:03 AM Edwin Lu wrote:
Hi,
Just wanted to ping this for more guidance.
It's difficult for me as long as I cannot investigate this with a testcase. Can
we go ahead with the other parts so the testcase can be added an
Hi,
Just wanted to ping this for more guidance.
Edwin
On 7/24/2024 12:03 PM, Edwin Lu wrote:
On 7/24/2024 3:52 AM, Richard Biener wrote:
On Wed, Jul 24, 2024 at 1:31 AM Edwin Lu wrote:
On 7/23/2024 11:20 AM, Richard Sandiford wrote:
Edwin Lu writes:
On 7/23/2024 4:56 AM, Richard
Thanks!
Edwin
On 8/19/2024 1:17 PM, Jeff Law wrote:
On 8/19/24 2:14 PM, Edwin Lu wrote:
The testcase has been modified to include the -fwrapv flag which now
causes the test to pass. Remove the xfail exception
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: Remove riscv xfail exception
The testcase has been modified to include the -fwrapv flag which now
causes the test to pass. Remove the xfail exception
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-5.c: Remove riscv xfail exception
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.dg/signbit-5.c | 1 -
1 file changed, 1
Thanks!
Edwin
On 8/8/2024 12:24 AM, Robin Dapp wrote:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index d150f20b5d9..02814183dbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
+++ b/gcc/
-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index d150f20b5d9..02814183dbb 100644
Thanks! Committed
Edwin
On 7/29/2024 6:37 AM, Kito Cheng wrote:
LGTM, although I said no binutils check for zacas and zabha, but B is
a different situation since GCC will add that if zba, zbb and zbs are
all present.
On Thu, Jul 25, 2024 at 7:51 AM Edwin Lu wrote:
Binutils 2.42 and before
b in march string
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add B assembler check
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 8 +++
gcc/config.in | 6 +
gcc/conf
On 7/24/2024 3:03 AM, Robin Dapp wrote:
Thanks for the explanation! I have a few clarification questions about this.
If I understand correctly, B would represent the number of elements the
vector can have (for 128b vector operating on 32b elements, B == 4, but if
operating on 64b elements B ==
On 7/24/2024 3:03 AM, Robin Dapp wrote:
Thanks for the explanation! I have a few clarification questions about this.
If I understand correctly, B would represent the number of elements the
vector can have (for 128b vector operating on 32b elements, B == 4, but if
operating on 64b elements B ==
On 7/24/2024 3:52 AM, Richard Biener wrote:
On Wed, Jul 24, 2024 at 1:31 AM Edwin Lu wrote:
On 7/23/2024 11:20 AM, Richard Sandiford wrote:
Edwin Lu writes:
On 7/23/2024 4:56 AM, Richard Biener wrote:
On Tue, Jul 23, 2024 at 1:03 AM Edwin Lu wrote:
Hi Richard,
On 5/31/2024 1:48 AM
On 7/23/2024 11:20 AM, Richard Sandiford wrote:
Edwin Lu writes:
On 7/23/2024 4:56 AM, Richard Biener wrote:
On Tue, Jul 23, 2024 at 1:03 AM Edwin Lu wrote:
Hi Richard,
On 5/31/2024 1:48 AM, Richard Biener wrote:
On Thu, May 30, 2024 at 2:11 AM Patrick O'Neill wrote:
From: Greg M
On 7/23/2024 4:56 AM, Richard Biener wrote:
On Tue, Jul 23, 2024 at 1:03 AM Edwin Lu wrote:
Hi Richard,
On 5/31/2024 1:48 AM, Richard Biener wrote:
On Thu, May 30, 2024 at 2:11 AM Patrick O'Neill wrote:
From: Greg McGary
Still a NACK. If remain ends up zero
Hi Kito,
On 7/22/2024 8:19 AM, Kito Cheng wrote:
Corresponding implementation in compiler-rt already merged in LLVM
side, so I plan to merge this into trunk tomorrow if no strong
objections.
NOTE: This has been tested with clang/llvm within our internal CI.
On Mon, Jul 22, 2024 at 10:16 PM
Committed! Thanks!
Edwin
On 7/17/2024 1:14 AM, Kito Cheng wrote:
LGTM :)
On Wed, Jul 17, 2024 at 9:15 AM Edwin Lu wrote:
The C + F extentions implies the zcf extension on rv32. Add missing zcf
extension for the rv32 target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr
The C + F extentions implies the zcf extension on rv32. Add missing zcf
extension for the rv32 target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr-16.c: Update expected assembly
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
1 file
Committed!
Edwin
On 7/12/2024 3:40 PM, Jeff Law wrote:
On 7/12/24 12:37 PM, Edwin Lu wrote:
The following testcase was not properly testing anything due to an
uninitialized variable. As a result, the loop was not iterating through
the testing data, but instead on undefined values which
/binop/vec_sat_binary_vx.h:
initialize variable
Signed-off-by: Edwin Lu
---
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h | 1 +
1 file changed, 1 insertion(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
b/gcc/testsuite/gcc.target
Hi Pan,
This patch appears to be tripping up our postcommit for building linux
with vector https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1325.
FAIL: gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c
execution test
Looking at the logs, the test fails due to the __builtin
Committed!
Edwin
On 7/9/2024 12:07 PM, Jeff Law wrote:
On 7/9/24 11:44 AM, Edwin Lu wrote:
This patch adds support for recognizing the B standard extension to
be the
collection of Zba, Zbb, Zbs extensions for consistency and
conciseness across
toolchains
* https://github.com/riscv/riscv
riscv/synthesis-7.c: Ditto
* gcc.target/riscv/synthesis-8.c: Ditto
* gcc.target/riscv/zba_zbs_and-1.c: Ditto
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch
Signed-off-by: Edwin Lu
---
V2: no change
---
gcc/testsuite/g++.target/
extension
* config/riscv/arch-canonicalize: Ditto
Signed-off-by: Edwin Lu
---
V2: Add b to riscv_combine_info
---
gcc/common/config/riscv/riscv-common.cc | 7 +++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv
Support for recognizing B as the collection of zba, zbb, zbs extensions
https://github.com/riscv/riscv-b/tags
V2: add b to riscv_combine_info
Edwin Lu (2):
RISC-V: Add support for B standard extension
RISC-V: Update testsuite to use b
gcc/common/config/riscv/riscv-common.cc
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch
Signed-off-by: Edwin Lu
---
gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C | 2
extension
* config/riscv/arch-canonicalize: Ditto
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 6 ++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 7 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config
Support for recognizing B as the collection of zba, zbb, zbs extensions
https://github.com/riscv/riscv-b/tags
Edwin Lu (2):
RISC-V: Add support for B standard extension
RISC-V: Update testsuite to use b
gcc/testsuite/ChangeLog:
gcc/common/config/riscv/riscv-common.cc | 6
Thanks!
Edwin
On 6/17/2024 5:33 PM, Jeff Law wrote:
On 6/17/24 12:33 PM, Edwin Lu wrote:
When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does n
Committed. Thanks!
Edwin
On 6/17/2024 5:31 PM, Jeff Law wrote:
On 6/17/24 12:33 PM, Edwin Lu wrote:
On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI
ert out of conditional block
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: change assert to internal error
V3: No change
---
gcc/config/riscv/riscv-v.cc | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/
v32/64 gcv newlib. Letting CI perform additional testing
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: Remove subreg check
V3: Update _trunc_scalar splitter as well
---
gcc/config/riscv/autovec-opt.md | 6
ernal error
V3: Update the _trunc_scalar splitter as well
Edwin Lu (2):
RISC-V: Fix vwsll combine on rv32 targets
RISC-V: Move mode assertion out of conditional branch in emit_insn
gcc/config/riscv/autovec-opt.md | 6 ++
gcc/config/riscv/riscv-v.cc | 25 +++--
2
ert out of conditional block
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: change assert to internal error
---
gcc/config/riscv/riscv-v.cc | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/
/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2: Remove subreg check
---
gcc/config/riscv/autovec-opt.md | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/ris
ernal error
Edwin Lu (2):
RISC-V: Fix vwsll combine on rv32 targets
RISC-V: Move mode assertion out of conditional branch in emit_insn
gcc/config/riscv/autovec-opt.md | 3 +--
gcc/config/riscv/riscv-v.cc | 25 +++--
2 files changed, 20 insertions(+), 8 dele
On 6/12/2024 12:39 AM, Robin Dapp wrote:
Hi Edwin,
this LGTM but I just remembered I intended to turn the assert
into a more descriptive error.
The attached patch has been sitting on my local branch for a
while. Maybe we should rather fold yours into it?
That's fine with me! Having more desc
Hi Robin,
I did a test run without the subreg condition and it also appears to
work when running on rv32gcv and rv64gcv newlib. Would it be better to
remove the subreg?
Edwin
On 6/12/2024 12:42 AM, Robin Dapp wrote:
Hi Edwin,
this is OK but did you check if we can get rid of the subreg
con
that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.
Make the assert unconditional
gcc/ChangeLog:
* config/riscv/riscv-v.cc: Move assert out of conditional block
Signed-off-by: Edwin Lu
---
gcc/co
/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
gcc/config/riscv/autovec-opt.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6a2eabbd854..b9e5ccfe
bug and also robustify our emit_insn by making an assertion
check unconditional
I'm not sure if this ICE warrants its own separate testcase since it is
already being tested. I do have a minimal testcase on hand if we would
like to add one.
Edwin Lu (2):
RISC-V: Fix vwsll combine on rv32 ta
Some testcases still had --param=riscv-autovec-preference=_,
update to use -mrvv-vector-bits=_. Also add missing period
in riscv.opt which caused a compiler driver error.
gcc/ChangeLog:
* config/riscv/riscv.opt: Add missing period
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/
On 4/11/2024 5:45 AM, Li, Pan2 wrote:
Thanks for reporting this. Just take a look from my test log that 930623-1.c is
all pass.
Thus I bet this difference comes from the build option --with-arch=rv32imac but
my test script take rv64gcv.
I've built the git revision f3fdcf4a37a with
../gcc-tru
On 4/4/2024 7:40 AM, Palmer Dabbelt wrote:
On Thu, 04 Apr 2024 07:37:56 PDT (-0700), ja...@redhat.com wrote:
On Thu, Apr 04, 2024 at 07:28:40AM -0700, Palmer Dabbelt wrote:
I'm not sure if we need release maintainer approval,
For cherry-picking one's own non-risky bugfixes for regression or
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and
there is nothing to advance, but that is not the case for (...) functions
returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail
Fix the issue by checking if a
On 3/18/2024 8:14 PM, Jeff Law wrote:
On 3/12/24 3:56 PM, Edwin Lu wrote:
Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.
gcc/testsuite/ChangeLog
On 3/18/2024 8:07 PM, Jeff Law wrote:
On 3/18/24 12:54 PM, Edwin Lu wrote:
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
arguments and
there is nothing to advance, but that is not the case for (...)
functions
returning by hidden reference which have one such artif
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and
there is nothing to advance, but that is not the case for (...) functions
returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail
Fix the issue by checking if a
: Ditto
Signed-off-by: Edwin Lu
---
V1: Change tests to scan for range of vsetvls instead of specific number
V2: Add -fno-schedule-insns and -fno-schedule-insns2 to testcases that
were missing them. Those that had disabled insn scheduling, update
testcases to match current outputs to pass
* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
Recalculate dominator info when adding new_preheader to cfg
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr114197.c: New test.
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.dg/vect/pr114197.c | 18 ++
gcc/tree-vect-loop-manip.cc
/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
Signed-off-by: Edwin Lu
---
.../costmodel/riscv/rvv/dynamic-lmul4-6.c
On 2/21/2024 10:57 AM, Robin Dapp wrote:
For calling-convention-*.c, LGTM but one nit about change log. Take
**Update** here may make others not easy to learn what you did about
the file. You can say similar to "Rearrange and adjust the
asm-checker times" or likewise. Of course, you can refine
Committed
Edwin
On 2/20/2024 5:36 PM, Kito Cheng wrote:
LGTM, thanks for fixing that issue :)
On Wed, Feb 21, 2024 at 6:03 AM Edwin Lu wrote:
The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'
Specify
R target/113742
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113742.c: change mcpu to mtune and add march
Signed-off-by: Edwin Lu
---
V1: use require-effective-target
V2: switch to specifying march and mtune
---
gcc/testsuite/gcc.target/riscv/pr113742.c | 4 ++--
1 file changed, 2 inser
Thanks! Committed
Edwin
On 2/15/2024 9:27 AM, Mike Stump wrote:
On Feb 12, 2024, at 11:38 AM, Edwin Lu wrote:
There is currently no support for matching at least x lines of assembly
(only scan-assembler-times). This patch would allow setting upper or lower
bounds.
Use case: using different
On 2/15/2024 1:25 AM, Li, Pan2 wrote:
Sorry for late reply due to holiday. I double-checked the
calling-convernsion-*.c dump, it is safe to adjust the asm check to the number
as you mentioned.
Hi Pan,
I hope you had a good holiday! I already changed the numbers and added a
bit more checks
/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: change expected vsetvl
Signed-off-by: Edwin Lu
---
V1-3:
- Patch did not exist
V4:
- New patch
- improve calling-convention testcases (calling-conventions
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu
---
V2:
- New patch
V3/V4
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md: include generic-vector-ooo
* config/riscv/generic-vector-ooo.md: New file. to here
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2:
- Remove
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu
---
V2:
- No changes
V3:
- Remove debug statements
V4:
- no changes
---
gcc/config/riscv
(sifive_p400_clmul): ditto
* config/riscv/sifive-p600.md (sifive_p600_clmul): ditto
* config/riscv/vector.md: change rdfrm to fmove
* config/riscv/zc.md: change pushpop to load/store
Signed-off-by: Edwin Lu
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
V3
edule-insn -fno-schedule-insn2 to some test cases
V3:
- Separate vector pipelines to separate file which all tunes have access to
V4:
- Add insn reservations to sifive-p400 and sifive-p600 series
- Update test cases with new code generation
---
Edwin Lu (5):
RISC-V: Add non-vector types to dfa
On 2/14/2024 12:09 PM, Robin Dapp wrote:
On 2/14/24 20:46, Edwin Lu wrote:
The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'
I think we usually just add exactly this to the test options (so
it is always
ned-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/pr113742.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c
b/gcc/testsuite/gcc.target/riscv/pr113742.c
index ab8934c2a8a..9cea92ed97c 100644
--- a/gcc/testsuite/gcc.target/riscv/pr113742.c
+++ b/gcc
as granular towards specific cpu tuning.
gcc/ChangeLog:
* doc/sourcebuild.texi: add scan-assembler-bound
gcc/testsuite/ChangeLog:
* lib/scanasm.exp: add scan-assembler-bound
Signed-off-by: Edwin Lu
---
gcc/doc/sourcebuild.texi | 4 +++
gcc/testsuite/lib/scanasm.exp |
enabled
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-1.c: change selector
* gcc.target/riscv/rvv/base/pragma-2.c: ditto
* gcc.target/riscv/rvv/base/pragma-3.c: ditto
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c | 2 +-
gcc/testsuite
extension
* config/riscv/arch-canonicalize: ditto
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 7 +++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv
On 2/2/2024 11:10 PM, Li, Pan2 wrote:
Hi Edwin
I believe the only problematic failures are the 5 vls calling convention
ones where only 24 ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) are found.
Does this "only 24" comes from calling-convention-1.c?
Oops sorry about that. I said I would include all the
On 2/1/2024 8:28 PM, Li, Pan2 wrote:
Hi Edwin,
Just rerun the newlib and there is no ICE but still 160 dump failures as below.
Pan
Hi Pan,
Thanks for confirming! Having dump failures is expected. There are
around 7 more unique failures than I expected
(https://github.com/patrick-rivos/gcc
oduce the error.
The new scan dump failures are a result of now having a vector
scheduling pipeline.
Edwin
*From:* Edwin Lu <mailto:e...@rivosinc.com>
*Date:* 2024-02-01 14:13
*To:* juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai>;
gcc-patches <mailto:gcc-pat
idn't
find anything unexpected.
Edwin
*From:*juzhe.zh...@rivai.ai
*Sent:* Thursday, February 1, 2024 3:06 PM
*To:* Edwin Lu ; gcc-patches
*Cc:* Robin Dapp ; kito.cheng
; jeffreyalaw ; palmer
; vineetg ; Patrick O'Neill
*Subject:* Re: Re: [COMMITTED V3 1/4] RISC-V: Add non-vecto
test runs using our full gcc postcommit testing configurations and
should have those results in tomorrow. Hopefully it was just a missed
config target I didn't test and wasn't tested on the precommit ci.
Edwin
On 1/31/2024 9:42 PM, Edwin Lu wrote:
Hi Juzhe,
I didn't see an
Hi Juzhe,
I didn't see any ICEs when I tested locally (tested on
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d).
Can you tell me what config you're using?
Edwin
On 1/31/2024 6:57 PM, juzhe.zh...@rivai.ai wrote:
Hi, all.
https://gcc.gnu.org/git/?p=gc
I recently committed changes modifying the scheduling reservations. Some
things may need to be retested with the newly enabled asserts.
Edwin
On 1/31/2024 1:40 AM, Monk Chiang wrote:
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650
On 1/31/2024 12:28 PM, Robin Dapp wrote:
LGTM, thanks.
Regards
Robin
Committed!
Edwin
On 1/25/2024 9:06 AM, Robin Dapp wrote:
/* If we ever encounter an insn without an insn reservation, trip
an assert so we can find and fix this problem. */
-#if 0
+ if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type (insn
On 1/25/2024 9:06 AM, Robin Dapp wrote:
Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series
On 1/25/2024 9:06 AM, Robin Dapp wrote:
LGTM, thanks.
Regards
Robin
Committed!
Edwin
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md: include generic-vector-ooo
* config/riscv/generic-vector-ooo.md: New file. to here
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2:
- Remove
/rvv/base/pragma-2.c: ditto
* gcc.target/riscv/rvv/base/pragma-3.c: ditto
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c| 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c | 2 +-
3 files
On 1/25/2024 9:06 AM, Robin Dapp wrote:
/* If we ever encounter an insn without an insn reservation, trip
an assert so we can find and fix this problem. */
-#if 0
+ if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type (insn
On 1/25/2024 9:06 AM, Robin Dapp wrote:
39 additional unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?
Currently, without vector op latency, th
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