[PATCH v4] rs6000: Use vector addition when left shifting by 1[PR119702]

Hi, Following is version 4 of the patch proposed for master to fix PR119702. This patch has been bootstrapped and regtested on powerpc64le-linux. Kindly review the patch. Thanks and regards, Avinash Jayakar Changes from v3: 1. Add author information before changelog. 2. Right

[PATCH][PR104116] Add vectorization logic for floor_{mod,div}

Hi, The following patch implements the vectorization logic for FLOOR_MOD_EXPR and FLOOR_DIV_EXPR. According to the logic mentioned in the PR, we have For signed operands, r = x %[fl] y;

Re: [PATCH v3][PR119702] rs6000: Use vector addition when left shifting by 1

FYI, this patch has been bootstrapped and regtested on powerpc64le- linux.

[PATCH v3][PR119702] rs6000: Use vector addition when left shifting by 1

Hi, This is the third version of the patch proposed for master aiming to fix PR119702. Requesting review of this patch. The following sequence of assembly in powerpc64le vspltisw 0,1 vsld 2,2,0 is replaced by this vaddudm 2,2,2 whenever there is a vector left shift by a c

[PATCH][PR119702] rs6000: Use vector addition when left shifting by 1

Hi, This is the third version of the patch proposed for master aiming to fix PR119702. Requesting review of this patch. The following sequence of assembly in powerpc64le vspltisw 0,1 vsld 2,2,0 is replaced by this vaddudm 2,2,2 whenever there is a vector left shift by a c

[PATCH v2][PR119702] rs6000: Use vector addition when left shifting by 1

Hello, This is the second version of the patch proposed for master aiming to fix PR119702. I request the review of this patch. The following sequence of assembly in powerpc64le vspltisw 0,1 vsld 2,2,0 is replaced by this vaddudm 2,2,2 whenever there is a vector left shi

Re: [PATCH] rs6000: Use vector add when left shifting by 1

a vector operand of all 1's in predicate.md +(define_predicate "shift_constant_1" + (match_code "const_vector") +{ + unsigned nunits = GET_MODE_NUNITS (mode), i; + for (i = 1; i < nunits; i++) { +if (INTVAL (CONST_VECTOR_ELT(op, i)) != 1) + return 0; + } + return 1; +}) + Actually this particular node is a vector constant, so we need to check if all its elements are 1. Please correct me if I am wrong, but I believe the const1_rtx does not work for vectors? Thanks and regards, Avinash Jayakar

Re: [PATCH] rs6000: Use vector add when left shifting by 1

; is initialized with "default_target_expmed", where these costs are defined. Ideally in case of powerpc and in vector mode, the shift_cost should be more than add_cost right, since we need to first splat the constant operand into a register and then do the shift. I think this cost is not accounted for.  Thank you, Avinash Jayakar

Re: [PATCH] rs6000: Use vector add when left shifting by 1

operands[1], +operands[2]))); +DONE; + } +}) This way it is easy to recognize in define_insn as follows diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 7edc288a656..3f678f2e666 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2107,6 +2107,17 @@ "vsrv %0,%1,%2" [(set_attr "type" "vecsimple")]) + +(define_insn "" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") + (const_vector:V2DI [(const_int 1) (const_int 1)])))] + "" + { +return "vaddum %0,%1,%1"; + } +) + As you mentioned I will have to add patterns for various sizes as well. Regards, Avinash Jayakar

[PING 2] [PR119702] [PATCH] rs6000: Use vector add when left shifting by 1

Ping. Requesting review of this patch. Thank you, Avinash Jayakar On Thu, 2025-08-21 at 19:54 +0530, Avinash Jayakar wrote: > On Thu, 2025-08-14 at 11:27 +0530, Avinash Jayakar wrote: > > PR119702 > Ping 1. Request review of this patch. > > Thanks and regards, > Avinash

Re: [PR119702][PATCH] rs6000: Use vector add when left shifting by 1

On Thu, 2025-08-14 at 11:27 +0530, Avinash Jayakar wrote: > PR119702 Ping 1. Request review of this patch. Thanks and regards, Avinash

[COMMITTED] MAINTAINERS: Add myself to write after approval

2025-08-12 Avinash Jayakar * MAINTAINERS: Add myself to write after approval. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index dd31eed0251..07359c5d7ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,7 @@ Fariborz Jahanian

[PATCH] rs6000: Use vector add when left shifting by 1

generate ashift op. 2025-08-13 Avinash Jayakar PR target/119702 gcc: * config/rs6000/vector.md (vashl3): Generate add when operand 2 is a constant with value 1. gcc/testsuite: * gcc.target/powerpc/pr119702-1.c: New test (for checking generation of add for