Hi Segher,
On Wed, 2025-09-03 at 12:30 -0500, Segher Boessenkool wrote:
>
>
> At least combine will merge that together with the move from the
> const_int. What happened there? The dump file will tell you.
>
Thanks for this information. My thought process was a bit convoluted. I
did not pay attention to the combine pass, so I thought we had to scan
for the complete pattern (along with what is in register operand #2). I
removed the define_expand, and it does work!
So I updated the define_insn as follows
diff --git a/gcc/config/rs6000/altivec.md
b/gcc/config/rs6000/altivec.md
index 7edc288a656..8b1beb8f713 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2107,6 +2107,14 @@
"vsrv %0,%1,%2"
[(set_attr "type" "vecsimple")])
+(define_insn ""
+ [(set (match_operand:VI2 0 "register_operand" "=v")
+ (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
+ (match_operand:VI2 2 "shift_constant_1" "")))]
+ "<VI_unit>"
+ "vaddu<VI_char>m %0,%1,%1"
+)
+
> > ;; Expanders for arithmetic shift left on each vector element
> > (define_expand "vashl<mode>3"
> > [(set (match_operand:VEC_I 0 "vint_operand")
> > (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand")
> > - (match_operand:VEC_I 2 "vint_operand")))]
> > + (match_operand:VEC_I 2 "general_operand")))]
> > "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
> > - "")
> > +{
> > + rtx op2 = operands[2];
> > + if (CONSTANT_P(op2) && INTVAL(const_vector_elt (op2, 0)) != 1) {
> > + operands[2] = copy_to_mode_reg (<MODE>mode, op2);
> > + emit_insn (gen_rtx_SET (operands[0],
> > + gen_rtx_ASHIFT (<MODE>mode,
> > + operands[1],
> > + operands[2])));
> > + DONE;
> > + }
> > +})
>
> CONSTANT_P is much more general than what you want here. Just check
> for
> const_int more directly?
>
> But, don't do that at all! Tou do not want to use INTVAL, you want
> to
> check if the node is equal to const1_rtx directly! That is the
> canonical representation for (const_int 1), it is a unique RTX,
> wherever
> (const_int 1) is used it always will use const1_rtx. As it says in
> emit-rtl.cc:
>
Would it be ok to add a predicate instead like this
Added the predicate to recognize a vector operand of all 1's in
predicate.md
+(define_predicate "shift_constant_1"
+ (match_code "const_vector")
+{
+ unsigned nunits = GET_MODE_NUNITS (mode), i;
+ for (i = 1; i < nunits; i++) {
+ if (INTVAL (CONST_VECTOR_ELT(op, i)) != 1)
+ return 0;
+ }
+ return 1;
+})
+
Actually this particular node is a vector constant, so we need to check
if all its elements are 1. Please correct me if I am wrong, but I
believe the const1_rtx does not work for vectors?
Thanks and regards,
Avinash Jayakar
