On 5/16/25 11:32 AM, Jeff Law wrote:
On 5/16/25 11:21 AM, Richard Sandiford wrote:
This pattern used operands[2] to hold the shift amount, even though
the pattern doesn't have an operand 2 (not even as a match_dup).
This caused a build failure with -Werror:
array subscript 2 is above ar
On Sat, 2025-05-17 at 10:55 -0600, Jeff Law wrote:
>
> On 5/10/25 11:12 AM, Quentin Boswank wrote:
> > From 6462f1e6a2565c5d4756036d9bc2f39dce9bd768 Mon Sep 17 00:00:00 2001
> > From: QBos07
> > Date: Sat, 10 May 2025 16:56:28 +
> > Subject: [PATCH] libgcc SH: fix alignment for relaxation
On Sat, May 17, 2025 at 5:04 AM Archit Jindal
wrote:
>
> Hi GCC community,
>
> I'm working on a change to allow ASan to use file-backed memory allocations
> for both the Primary and Secondary allocators. This would be particularly
> helpful on systems with limited system memory, where ASan’s cur
Hello all,
The attached patch revises the logic of the checks in
gfc_check_c_associated to handle previous cases that ICE'ed as seen in
the PR. There are multiple gotchas in these cases, particularly with the
optional c_ptr_2 argument.
I factored the logic into two new helper functions. This
On 5/9/25 11:21 AM, Sam James wrote:
Sam James writes:
When working on xz, I set `-Werror=suggest-attribute=returns_nonnull`, and
the build failed (as I expected it to), but with no visible error from
the compiler. There's a mysterious '>/dev/null 2>&1' on the second line where
liblzma_la-c
On 5/10/25 11:12 AM, Quentin Boswank wrote:
From 6462f1e6a2565c5d4756036d9bc2f39dce9bd768 Mon Sep 17 00:00:00 2001
From: QBos07
Date: Sat, 10 May 2025 16:56:28 +
Subject: [PATCH] libgcc SH: fix alignment for relaxation
when relaxation is enabled we can not infer the alignment
from the p
On 5/12/25 5:20 AM, Umesh Kalappa wrote:
---
gcc/config/riscv/mips-p8700.md | 139 +++
gcc/config/riscv/riscv-cores.def | 5 ++
gcc/config/riscv/riscv-opts.h| 3 +-
gcc/config/riscv/riscv.cc| 22 +
gcc/config/riscv/riscv.md| 3
On 5/14/25 12:06 PM, Vineet Gupta wrote:
On 5/13/25 10:07, Vineet Gupta wrote:
On 5/10/25 07:20, Jeff Law wrote:
On 5/9/25 2:27 PM, Vineet Gupta wrote:
This is effectively reverting e5d1f538bb7d
"(RISC-V: Allow different dynamic floating point mode to be merged)"
while retaining the testc
On 5/10/25 9:46 PM, Vineet Gupta wrote:
Frankly I'm surprised we need FRM adjustments as much as we do, though
presumably there's some builtin or somesuch that we need to twiddle FRM
to implement and as a result if the builtin ever gets used it leads to
FRM games. But it still seems high.
Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk/15?
-- >8 --
When we import a pending instantiation that matches an existing partial
specialisation, we don't find the slot in the entity map because for
partial specialisations we register the TEMPLATE_DECL but for normal
implicit i
On Wed, May 14, 2025 at 02:22:23PM +, Yuao Ma wrote:
> If approved, I suggest committing this foundational change first. Constant
> folding for these builtins will be addressed in subsequent patches.
Note, not just constant folding is needed, but I think the builtins should
be handled in
tree-
On 5/14/25 2:22 PM, Joseph Myers wrote:
On Wed, 14 May 2025, Yuao Ma wrote:
Hi Joseph,
I have updated the patch based on your review comments. I added the
newly introduced builtin to extend.texi and mentioned the PR in the
commit message. Could you please take another look when you have a
m
On 5/14/25 9:20 PM, Kito Cheng wrote:
This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose register
(x8-x15) in inline asm.
Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102
gcc/ChangeLog:
On 5/14/25 9:14 PM, Kito Cheng wrote:
This commit adds the code gen support for Zilsd, which is a
newly added extension for RISC-V. The Zilsd extension allows
for loading and storing 64-bit values using even-odd register
pairs.
We only try to do miminal code gen support for that, which means
Found this while setting up the risc-v coordination branch off of
gcc-15. Not sure why I didn't use rtvec_alloc directly here since we're
going to initialize the whole vector ourselves. Using gen_rtvec was
just wrong as it's walking down a non-existent varargs list. Under the
"right" circums
Hi GCC community,
I'm working on a change to allow ASan to use file-backed memory allocations
for both the Primary and Secondary allocators. This would be particularly
helpful on systems with limited system memory, where ASan’s current use of
private anonymous mmaps puts direct pressure on availab
Hi, I meet that symbol '__gg__space' generated '\x7f\x7fgg\x7f\x7fspace'
in asm. I learn that _tolower to give the expected results, __isascii and
isupper must both return nonzero. So consider use the TOLOWER in safe-ctype.h.
gcc/cobol:
* genapi.cc: replace _tolower with TOLOWER
---
gcc/
> Am 16.05.2025 um 19:37 schrieb Richard Sandiford :
>
> genemit has traditionally used open-coded gen_rtx_FOO sequences
> to build up the instruction pattern. This is now the source of
> quite a bit of bloat in the binary, and also a source of slow
> compile times.
>
> Two obvious ways of t
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