On 5/14/25 9:20 PM, Kito Cheng wrote:
This commit introduces a new operand constraint `cR` for the RISC-V architecture, which allows the use of an even-odd RVC general purpose register (x8-x15) in inline asm. Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102 gcc/ChangeLog: * config/riscv/constraints.md (cR): New constraint. * doc/md.texi (Machine Constraints::RISC-V): Document the new cR constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/constraint-cR.c: New test case.
OK jeff
