Re: [PATCH 1/2]middle-end: Add new tbranch optab to add support for bit-test-and-branch operations

On Mon, Nov 14, 2022 at 4:57 PM Tamar Christina via Gcc-patches wrote: > > > -Original Message- > > From: Richard Biener > > Sent: Saturday, November 5, 2022 2:23 PM > > To: Aldy Hernandez > > Cc: Tamar Christina ; Jeff Law > > ; gcc-patches@gcc.gnu.org; nd ; > > MacLeod, Andrew > > Sub

[committed] c++: Fix a typo in function name

Hi! I've noticed I've made a typo in the name of the function. Fixed thusly. Bootstrapped/regtested on x86_64-linux and i686-linux, committed as obvious to trunk. 2022-11-15 Jakub Jelinek * cp-tree.h (next_common_initial_seqence): Rename to ... (next_common_initial_sequence):

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On Tue, Nov 15, 2022 at 12:01 AM Philipp Tomsich wrote: > > On Mon, 14 Nov 2022 at 23:47, Palmer Dabbelt wrote: > > > > [Trying to join the threads here.] > > > > On Mon, 14 Nov 2022 13:28:23 PST (-0800), philipp.toms...@vrull.eu wrote: > > > Jeff, > > > > > > On Mon, 14 Nov 2022 at 22:23, Jeff L

Re: [PATCH] [PR68097] Try to avoid recursing for floats in tree_*_nonnegative_warnv_p.

On Mon, Nov 14, 2022 at 8:05 PM Aldy Hernandez wrote: > > > > On 11/14/22 10:12, Richard Biener wrote: > > On Sat, Nov 12, 2022 at 7:30 PM Aldy Hernandez wrote: > >> > >> It irks me that a PR named "we should track ranges for floating-point > >> hasn't been closed in this release. This is an att

[PATCH, V1 1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard

From: zengxiao This patch makes R_RISCV_SUB6 conforms to riscv abi standard. R_RISCV_SUB6 only the lower 6 bits of the code are valid. The proposed specification which can be found in 8.5. Relocations of, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pd

[PATCH, V1 0/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard

From: zengxiao Hi all RISC-V folks: When riscv-objdump is used to generate dwarf information, problems are found, like: DW_CFA_??? (User defined call frame op: 0x3c) This error is related to that riscv-objdump does not follow the riscv R_RISCV_SUB6 standard. Riscv-readelf is correct because

[PATCH, V1 1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard

From: zengxiao This patch makes R_RISCV_SUB6 conforms to riscv abi standard. R_RISCV_SUB6 only the lower 6 bits of the code are valid. The proposed specification which can be found in 8.5. Relocations of, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pd

[PATCH, V1 0/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard

From: zengxiao Hi all RISC-V folks: When riscv-objdump is used to generate dwarf information, problems are found, like: DW_CFA_??? (User defined call frame op: 0x3c) This error is related to that riscv-objdump does not follow the riscv R_RISCV_SUB6 standard. Riscv-readelf is correct because

[PATCH] Remove Score documentation

From: Andrew Pinski Score target support was removed in r5-3909-g3daa7bbf791203 but it looks like some of the documentation was missed. This removes it. Committed as obvious after a "make html". Thanks, Andrew gcc/ChangeLog: * doc/invoke.texi: Remove Score option section. --- gcc/doc

[PATCH v4] OpenMP: Generate SIMD clones for functions with "declare target"

Here is yet another attempt at a patch to auto-generate SIMD clones for functions that already have the "declare target" attribute. This version v4 is derived from the previous v2 version, since v3 seemed to be a dead end. I have added conditionals to restrict the auto-generation at -O2 to th

[PATCH] Remove the picoChip documentation

From: Andrew Pinski PicoChip support was removed in r5-3431-g157e859ffe3b5d but the documentation was missed it seems. Committed as obvious after running "make html" to make sure the building of the documentation still works. Thanks, Andrew Pinski gcc/ChangeLog: * doc/extend.texi: Rem

[PATCH] Remove documentation for MeP

From: Andrew Pinski MeP support was removed in r7-1614-g0609abdad81e26 but it looks like the documentation for the target was missed. Committed as obvious after doing "make html" to make sure the documentation is fine. Thanks, Andrew Pinski gcc/ChangeLog: * doc/extend.texi: Remove MeP

[PATCH] Fix @opindex for mcall-aixdesc and mcall-openbsd

From: Andrew Pinski For mcall-aixdesc, the opindex was just m which was wrong. For mcall-openbsd, the opindex was mcall-netbsd which was wrong. This two have been broken since the options were added to the documentation back in r0-92913-g244609a618b094 . Committed as obvious after a "make html"

Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

On 11/14/22 20:13, Kito Cheng wrote: I would suggest add a sperated case and scan-assembly-not to demonstrate this patch. Agreed.  One way to do this would be to have new tests which have the proper dg-directives for testing this issue and #include the original test. So, something like th

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

On 11/14/22 17:53, Palmer Dabbelt wrote: On Mon, 14 Nov 2022 16:46:37 PST (-0800), Kito Cheng wrote: Hi Christoph: This patch implements expansions for the cmpstrsi and the cmpstrnsi builtins using Zbb instructions (if available). This allows to inline calls to strcmp() and strncmp(). The e

[PATCH] doc: Reword the description of -mrelax-cmpxchg-loop [PR 107676]

Hi, According to PR 107676, the document of -mrelax-cmpxchg-loop is nonsensical. Adjust the wording according to the comments. Bootstrapped on x86_64-pc-linux-gnu, ok for trunk? gcc/ChangeLog: PR target/107676 * doc/invoke.texi: Reword the description of -mrelax-cmpxchg-

Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

On 11/14/22 09:29, jiawei wrote: Skip add insn generate if the adjust size equal to zero. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_epilogue): New if control segement. --- gcc/config/riscv/riscv.cc | 18 ++ 1 file changed

Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

I would suggest add a sperated case and scan-assembly-not to demonstrate this patch. juzhe.zh...@rivai.ai 於 2022年11月15日 週二 10:47 寫道： > I think you'd better change assembler checking of "spill-*.c" cases. > Check they don't have "addi sp,sp,0" redundant instruction. > Let's see whether Kito aggr

Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

I think you'd better change assembler checking of "spill-*.c" cases. Check they don't have "addi sp,sp,0" redundant instruction. Let's see whether Kito aggree with that. juzhe.zh...@rivai.ai From: jiawei Date: 2022-11-15 10:37 To: Kito Cheng CC: gcc-patches; kito.cheng; palmer; juzhe.zhong; chr

Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

> -原始邮件- > 发件人: "Kito Cheng" > 发送时间: 2022-11-15 09:48:26 (星期二) > 收件人: jiawei > 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@rivosinc.com, juzhe.zh...@rivai.ai, christoph.muell...@vrull.eu, philipp.toms...@vrull.eu, wuwei2...@iscas.ac.cn > 主题: Re: [PATCH] RISC-V: Optimal RV

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

On Tue, Nov 15, 2022 at 8:53 AM Palmer Dabbelt wrote: > > On Mon, 14 Nov 2022 16:46:37 PST (-0800), Kito Cheng wrote: > > Hi Christoph: > > > >> This patch implements expansions for the cmpstrsi and the cmpstrnsi > >> builtins using Zbb instructions (if available). > >> This allows to inline calls

Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

Could you provide some testcase? On Tue, Nov 15, 2022 at 12:29 AM jiawei wrote: > > Skip add insn generate if the adjust size equal to zero. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_epilogue): > New if control segement. > > --- > gcc/co

Re: [PATCH] lto: Stream current working directory for first streamed relative filename and adjust relative paths [PR93865]

On Thu, Sep 10, 2020 at 1:39 AM Jakub Jelinek via Gcc-patches wrote: > > If the gcc -c -flto ... commands to compile some or all objects are run in a > different directory (or in different directories) from the directory in > which the gcc -flto link line is invoked, then the .debug_line will be >

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

On Mon, 14 Nov 2022 16:46:37 PST (-0800), Kito Cheng wrote: Hi Christoph: This patch implements expansions for the cmpstrsi and the cmpstrnsi builtins using Zbb instructions (if available). This allows to inline calls to strcmp() and strncmp(). The expansion basically emits a peeled comparison

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

Hi Christoph: > This patch implements expansions for the cmpstrsi and the cmpstrnsi > builtins using Zbb instructions (if available). > This allows to inline calls to strcmp() and strncmp(). > > The expansion basically emits a peeled comparison sequence (i.e. a peeled > comparison loop) which comp

[PATCH v2] c++: Disable -Wignored-qualifiers for template args [PR107492]

On Thu, Nov 03, 2022 at 03:22:12PM -0400, Jason Merrill wrote: > On 11/1/22 13:01, Marek Polacek wrote: > > It seems wrong to issue a -Wignored-qualifiers warning for code like: > > > >static_assert(!is_same_v); > > > > because there the qualifier matters. Likewise in template > > specializa

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

On 11/14/22 14:49, Christoph Müllner wrote: We can take this further, but then the following questions pop up: * how much data processing per loop iteration? I have no idea because I don't have any real data.  Last time I gathered any data on this issue was circa 1988 :-) * what about

Re: [PATCH] ira: Remove duplicate `memset' over `full_costs' from `assign_hard_reg'

On 11/14/22 16:21, Maciej W. Rozycki wrote: Remove duplicate clearing of `full_costs' made in `assign_hard_reg', which has been there since the beginning, i.e. commit 058e97ecf33a ("IRA has been merged into trunk"), . gcc/

Re: [PATCH] c++: Add testcase for DR 2392

On 11/14/22 00:36, Jakub Jelinek wrote: Hi! Working virtually out of Baker Island. The testcase from DR 2392 passes, so I assume we don't need to do anything further for the DR. Tested on x86_64-linux, ok for trunk? OK. 2022-11-13 Jakub Jelinek * g++.dg/DRs/dr2392.C: Add testca

Re: [PATCH] c++: Allow attributes on concepts - DR 2428

On 11/14/22 00:40, Jakub Jelinek wrote: Hi! Working virtually out of Baker Island. The following patch adds parsing of attributes to concept definition, allows deprecated attribute to be specified (some ugliness needed because CONCEPT_DECL is a cp/*.def attribute and so can't be mentioned in c-

Re: [PATCH 2/2] c++: remove i_c_e_p parm from tsubst_copy_and_build

On 11/10/22 09:56, Patrick Palka wrote: AFAICT the only purpose of tsubst_copy_and_build's integral_constant_expression_p boolean parameter is to diagnose certain constructs that aren't allowed to appear in a C++98 integral constant expression context, specifically casts to a non-integral type (d

Re: [PATCH 1/2] c++: remove function_p parm from tsubst_copy_and_build

On 11/10/22 09:56, Patrick Palka wrote: The function_p parameter of tsubst_copy_and_build (added in r69316) is inspected only in its IDENTIFIER_NODE case, where it controls whether we diagnose unqualified name lookup failure for the given identifier. But I think ever since r173965, we never subs

Re: [PATCH] c++: Implement C++23 P2589R1 - - static operator[]

On 11/10/22 21:40, Jakub Jelinek wrote: Hi! As stage1 is very close, here is a patch that implements the static operator[] paper. One thing that doesn't work properly is the same problem as I've filed yesterday for static operator() - PR107624 - that side-effects of the postfix-expression on whi

[PATCH] ira: Remove duplicate `memset' over `full_costs' from `assign_hard_reg'

Remove duplicate clearing of `full_costs' made in `assign_hard_reg', which has been there since the beginning, i.e. commit 058e97ecf33a ("IRA has been merged into trunk"), . gcc/ * ira-color.cc (assign_hard_reg): Remove du

Re: [PATCH] c++: init_priority and SUPPORTS_INIT_PRIORITY [PR107638]

On 11/11/22 08:47, Patrick Palka wrote: The commit r13-3706-gd0a492faa6478c for correcting the result of __has_attribute(init_priority) causes a bootstrap failure on hppa64-hpux because it assumes SUPPORTS_INIT_PRIORITY expands to a simple constant, but on this target SUPPORTS_INIT_PRIORITY is de

gcc-patches@gcc.gnu.org

On 11/11/22 10:22, Marek Polacek wrote: Non-const lvalue references can't bind to a temporary, so the warning should not be emitted if we're initializing something of that type. I'm not disabling the warning when the function itself returns a non-const lvalue reference, that would regress at lea

Re: [PATCH] c++: Add testcase for DR 2604

On 11/14/22 01:43, Jakub Jelinek wrote: Hi! Working virtually out of Baker Island. As the following testcase shows, I think we don't inherit template's attributes into specializations. Tested on x86_64-linux, ok for trunk? OK. 2022-11-13 Jakub Jelinek * g++.dg/DRs/dr2604.C: New

Re: [PATCH] c++: P2448 - Relaxing some constexpr restrictions [PR106649]

On 11/9/22 10:53, Marek Polacek wrote: This patch implements C++23 P2448, which lifts more restrictions on the constexpr keyword. It's effectively going the way of being just a hint (hello, inline!). This gist is relatively simple: in C++23, a constexpr function's return type/parameter type doe

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On Mon, 14 Nov 2022 at 23:47, Palmer Dabbelt wrote: > > [Trying to join the threads here.] > > On Mon, 14 Nov 2022 13:28:23 PST (-0800), philipp.toms...@vrull.eu wrote: > > Jeff, > > > > On Mon, 14 Nov 2022 at 22:23, Jeff Law wrote: > >> > >> > >> On 11/14/22 13:00, Palmer Dabbelt wrote: > >> > O

[committed] wwwdocs: gcc-13: Add release notes for more C23 features

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index 41d07e57..d033628b 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -112,9 +112,41 @@ a work-in-progress. https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm";>N3042,

[pushed] c++: only declare satisfied friends

Tested x86_64-pc-linux-gnu, applying to trunk. -- >8 -- A friend declaration can only have constraints if it is defined. If multiple instantiations of a class template define the same friend function signature, it's an error, but that shouldn't happen if it's constrained to only be declared in o

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

[Trying to join the threads here.] On Mon, 14 Nov 2022 13:28:23 PST (-0800), philipp.toms...@vrull.eu wrote: Jeff, On Mon, 14 Nov 2022 at 22:23, Jeff Law wrote: On 11/14/22 13:00, Palmer Dabbelt wrote: > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: >> >> This se

Re: Revert Sphinx documentation [Was: Issues with Sphinx]

On Mon, 14 Nov 2022, Jonathan Wakely wrote: > I formatted my new region/endregion pragmas on one line because that > seemed to be how it should be done for rSt, e.g. we had: > > ``#pragma GCC push_options`` ``#pragma GCC pop_options`` > > But I think the attached patch is more correct for how we

[committed] ira: Fix `create_insn_allocnos' `outer' parameter documentation

The parameter of `create_insn_allocnos' for any parent expression of `x' has always been called `outer' rather than `parent', just as added by commit d1bb282efbf9 ("Fix for "FAIL: tmpdir-gcc.dg-struct-layout-1/t028 c_compat_x_tst.o compile, (internal compiler error)""),

Re: [PATCH 2/2]AArch64 Perform more late folding of reg moves and shifts which arrive after expand

(Sorry, immediately following up to myself for a second time recently.) Richard Sandiford writes: > Tamar Christina writes: >>> >>> The same thing ought to work for smov, so it would be good to do both. >>> That would also make the split between the original and new patterns more >>> obvious: l

Re: [PATCH] [range-ops] Implement sqrt.

On Sun, 13 Nov 2022, Jakub Jelinek via Gcc-patches wrote: > So, I wonder if we don't need to add a target hook where targets will be > able to provide upper bound on error for floating point functions for > different floating point modes and some way to signal unknown accuracy/can't > be trusted,

Re: [PATCH 2/2]AArch64 Perform more late folding of reg moves and shifts which arrive after expand

Tamar Christina writes: >> >> The same thing ought to work for smov, so it would be good to do both. >> That would also make the split between the original and new patterns more >> obvious: left shift for the old pattern, right shift for the new pattern. >> > > Done, though because umov can do m

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

On Mon, Nov 14, 2022 at 8:28 PM Jeff Law wrote: > > On 11/13/22 16:05, Christoph Muellner wrote: > > From: Christoph Müllner > > > > This patch implements expansions for the cmpstrsi and the cmpstrnsi > > builtins using Zbb instructions (if available). > > This allows to inline calls to strcmp()

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

Jeff, On Mon, 14 Nov 2022 at 22:23, Jeff Law wrote: > > > On 11/14/22 13:00, Palmer Dabbelt wrote: > > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: > >> > >> This series provides support for the Ventana VT1 (a 4-way superscalar > >> rv64gc_zba_zbb_zbc_zbs_zifenci_xven

Re: [PATCH 1/5] c: Set the locus of the function result decl

On Sun, 13 Nov 2022, Bernhard Reutner-Fischer via Gcc-patches wrote: > Bootstrapped and regtested on x86_86-unknown-linux with no regressions. > Ok for trunk? > > Cc: Joseph Myers > --- > gcc/c/ChangeLog: > > * c-decl.cc (start_function): Set the result decl source > location to the

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On 11/14/22 13:00, Palmer Dabbelt wrote: On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: This series provides support for the Ventana VT1 (a 4-way superscalar rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support for the supported instruction fusion

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On Mon, 14 Nov 2022 at 21:58, Palmer Dabbelt wrote: > > On Mon, 14 Nov 2022 12:03:38 PST (-0800), philipp.toms...@vrull.eu wrote: > > On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt wrote: > >> > >> On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: > >> > > >> > This series p

Re: [PATCH 6/7] riscv: Add support for strlen inline expansion

On Mon, Nov 14, 2022 at 7:17 PM Jeff Law wrote: > > On 11/13/22 16:05, Christoph Muellner wrote: > > From: Christoph Müllner > > > > This patch implements the expansion of the strlen builtin > > using Zbb instructions (if available) for aligned strings > > using the following sequence: > > > >

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On Mon, 14 Nov 2022 12:03:38 PST (-0800), philipp.toms...@vrull.eu wrote: On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt wrote: On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: > > This series provides support for the Ventana VT1 (a 4-way superscalar > rv64gc_zba_zbb_zbc

Re: [PATCH v2] c, analyzer: support named constants in analyzer [PR106302]

On Fri, Nov 11, 2022 at 10:23:10PM -0500, David Malcolm wrote: > Changes since v1: ported the doc changes from texinfo to sphinx > > Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. > > Are the C frontend parts OK for trunk? (I can self-approve the > analyzer parts) Sorry for the

[PATCH][committed]middle-end: Fix addsub patch removing return statements

Hi All, My recent patch had return statements in the match.pd expressions which were recently outlawed.. Unfornately I didn't rebase this patch before committing so this broke the build. I've just reflowed the conditions to avoid the returns. Bootstrapped Regtested on aarch64-none-linux-gnu and

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt wrote: > > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: > > > > This series provides support for the Ventana VT1 (a 4-way superscalar > > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support > > for the sup

Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion

On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: This series provides support for the Ventana VT1 (a 4-way superscalar rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support for the supported instruction fusion patterns. This includes the addition of the

Re: [PATCH 7/7] riscv: Add support for str(n)cmp inline expansion

On 11/13/22 16:05, Christoph Muellner wrote: From: Christoph Müllner This patch implements expansions for the cmpstrsi and the cmpstrnsi builtins using Zbb instructions (if available). This allows to inline calls to strcmp() and strncmp(). The expansion basically emits a peeled comparison se

Re: [PATCH v2 2/2] RISC-V: Add instruction fusion (for ventana-vt1)

On 11/14/22 11:55, Philipp Tomsich wrote: On Mon, 14 Nov 2022 at 17:06, Jeff Law wrote: On 11/13/22 13:48, Philipp Tomsich wrote: The Ventana VT1 core supports quad-issue and instruction fusion. This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences together and adds idiom m

Re: [PATCH 3/7] riscv: Enable overlap-by-pieces via tune param

On Mon, Nov 14, 2022 at 8:04 PM Jeff Law wrote: > > On 11/14/22 01:29, Christoph Müllner wrote: > > > > On Mon, Nov 14, 2022 at 8:59 AM Philipp Tomsich > wrote: > >> On Mon, 14 Nov 2022 at 03:48, Vineet Gupta wrote: >> > >> > >> > >> > On 11/13/22 15:05, Christoph Muellner wrote: >> > > >> > >

Re: [PATCH] [PR68097] Try to avoid recursing for floats in tree_*_nonnegative_warnv_p.

On 11/14/22 10:12, Richard Biener wrote: On Sat, Nov 12, 2022 at 7:30 PM Aldy Hernandez wrote: It irks me that a PR named "we should track ranges for floating-point hasn't been closed in this release. This is an attempt to do just that. As mentioned in the PR, even though we track ranges f

Re: [PATCH 1/7] riscv: bitmanip: add orc.b as an unspec

On Mon, 14 Nov 2022 at 17:51, Jeff Law wrote: > > > On 11/13/22 16:05, Christoph Muellner wrote: > > From: Philipp Tomsich > > > > As a basis for optimized string functions (e.g., the by-pieces > > implementations), we need orc.b available. This adds orc.b as an > > unspec, so we can expand to i

Re: [PATCH 5/7] riscv: Use by-pieces to do overlapping accesses in block_move_straight

On 11/14/22 12:01, Christoph Müllner wrote: On Mon, Nov 14, 2022 at 6:16 PM Jeff Law wrote: On 11/13/22 16:05, Christoph Muellner wrote: > From: Christoph Müllner > > The current implementation of riscv_block_move_straight() emits a couple > of load-store pairs wit

Re: [PATCH 3/7] riscv: Enable overlap-by-pieces via tune param

On 11/14/22 01:29, Christoph Müllner wrote: On Mon, Nov 14, 2022 at 8:59 AM Philipp Tomsich wrote: On Mon, 14 Nov 2022 at 03:48, Vineet Gupta wrote: > > > > On 11/13/22 15:05, Christoph Muellner wrote: > > > > +static bool > > +riscv_overlap_op_by_piec

Re: [PATCH 5/7] riscv: Use by-pieces to do overlapping accesses in block_move_straight

On Mon, Nov 14, 2022 at 6:16 PM Jeff Law wrote: > > On 11/13/22 16:05, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The current implementation of riscv_block_move_straight() emits a couple > > of load-store pairs with maximum width (e.g. 8-byte for RV64). > > The remainder is ha

[PATCH][committed]middle-end: Fix can_special_div_by_const doc.

Hi All, This commits the typo fix so it matches the tm.texi file and fix the bootstrap. Committed under the obvious rule. Thanks, Tamar gcc/ChangeLog: * target.def: Fix typo. --- inline copy of patch -- diff --git a/gcc/target.def b/gcc/target.def index f491e2233cf18760631f148dacf18

Re: [PATCH v2 2/2] RISC-V: Add instruction fusion (for ventana-vt1)

On Mon, 14 Nov 2022 at 17:06, Jeff Law wrote: > > > On 11/13/22 13:48, Philipp Tomsich wrote: > > The Ventana VT1 core supports quad-issue and instruction fusion. > > This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences > > together and adds idiom matcheing for the supported fusi

[wwwdocs] cxx-status: Add C++23 papers from the Nov 2022 Kona WG21 plenary

Pushed. commit b97d1aba41d95ae9220fe08a991738a58a716212 Author: Marek Polacek Date: Mon Nov 14 13:49:21 2022 -0500 cxx-status: Add C++23 papers from the Nov 2022 Kona WG21 plenary diff --git a/htdocs/projects/cxx-status.html b/htdocs/projects/cxx-status.html index 8650f3cd..3454cfc9 10064

Re: [PATCH][X86_64] Separate znver4 insn reservations from older znvers

On Mon, 14 Nov 2022, Joshi, Tejas Sanjay wrote: > [Public] > > Hi, Hi. I'm still waiting for feedback on fixes for existing models: https://inbox.sourceware.org/gcc-patches/5ae6fc21-edc6-133-aee2-a41e16eb...@ispras.ru/T/#t did you have a chance to look at those? > PFA the patch which adds znv

Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

Applied to master. Thanks! Philipp. On Mon, 14 Nov 2022 at 16:52, Jeff Law wrote: > > > On 11/13/22 13:48, Philipp Tomsich wrote: > > The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and > > XVentanaCondOps. > > This introduces a placeholder -mcpu=ventana-vt1, so tooling and > >

Re: [PATCH] libstdc++: Enable _GLIBCXX_WEAK_DEFINITION on more platforms

Evening, Similar to the other patch, pinging this before it drifts unreasonably far into S3, and hence into GCC14. Archive: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603931.html Have a great evening :) -- Arsen Arsenović signature.asc Description: PGP signature

Ping: [PATCH] libstdc++: Enable building libstdc++.{a, so} when !HOSTED

Evening, Since S1 is closed now, best to ping this patch before it drifts into GCC14. Archive link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604031.html Have a great evening! -- Arsen Arsenović signature.asc Description: PGP signature

Re: [PATCH 6/7] riscv: Add support for strlen inline expansion

On 11/13/22 16:05, Christoph Muellner wrote: From: Christoph Müllner This patch implements the expansion of the strlen builtin using Zbb instructions (if available) for aligned strings using the following sequence: li a3,-1 addia4,a0,8 .L2: ld a5,0(a0) add

[PATCH] tree-optimization/107485 - fix non-call exception ICE with inlining

Inlining performs a wrong non-call exception fixup for VEC_COND_EXPRs which on the branch fail to properly have the condition split out in the first place. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed to the GCC 10 branch which is the only one this code snippet prevails. PR

[PATCH][committed] aarch64: Add support for +cssc

Hi all, This patch adds codegen for FEAT_CSSC from the 2022 Architecture extensions. It fits various existing optabs in GCC quite well. There are instructions for scalar signed/unsigned min/max, abs, ctz, popcount. We have expanders for these already, so they are wired up to emit single-insn patte

Re: [PATCH] Fix gdb FilteringTypePrinter (again)

Any chance to review this one ? On 06/10/22 19:38, François Dumont wrote: Hi Looks like the previous patch was not enough. When using it in the context of a build without dual abi and versioned namespace I started having failures again. I guess I hadn't rebuild everything properly. This tim

Re: [PATCH] PR 107189 Remove useless _Alloc_node

Gentle reminder. Sorry if I should have committed it as trivial but I cannot do it anymore now that I asked :-) On 12/10/22 22:18, François Dumont wrote: libstdc++: Remove _Alloc_node instance in _Rb_tree [PR107189]     libstdc++-v3/ChangeLog:     PR libstdc++/107189     *

Re: [PATCH v3] c++: parser - Support for target address spaces in C++

On 11/10/22 06:40, Georg-Johann Lay wrote: Am 10.11.22 um 15:08 schrieb Paul Iannetta: On Thu, Nov 03, 2022 at 02:38:39PM +0100, Georg-Johann Lay wrote: [PATCH v3] c++: parser - Support for target address spaces in C++ 2. Will it work with compound literals? =

Re: [PATCH 1/7] riscv: bitmanip: add orc.b as an unspec

On 11/14/22 09:51, Jeff Law wrote: On 11/13/22 16:05, Christoph Muellner wrote: From: Philipp Tomsich As a basis for optimized string functions (e.g., the by-pieces implementations), we need orc.b available.  This adds orc.b as an unspec, so we can expand to it. gcc/ChangeLog: *

Re: [PATCH] libatomic: Add support for LSE and LSE2

Wilco Dijkstra via Gcc-patches writes: > Add support for AArch64 LSE and LSE2 to libatomic. Disable outline atomics, > and use LSE ifuncs for 1-8 byte atomics and LSE2 ifuncs for 16-byte atomics. > On Neoverse V1, 16-byte atomics are ~4x faster due to avoiding locks. > > Note this is safe since w

Re: GCC 13.0.0 Status Report (2022-11-14), Stage 3 in effect now

Hi Martin, Is it allowed to merge libsanitizer from LLVM in stage 3? If not I'd like to cherry pick some commits from LLVM [to fix some stupid errors I've made in LoongArch libasan :(]. On Mon, 2022-11-14 at 13:21 +, Richard Biener via Gcc-patches wrote: > Status > == > > The GCC develo

Re: [PATCH 5/7] riscv: Use by-pieces to do overlapping accesses in block_move_straight

On 11/13/22 16:05, Christoph Muellner wrote: From: Christoph Müllner The current implementation of riscv_block_move_straight() emits a couple of load-store pairs with maximum width (e.g. 8-byte for RV64). The remainder is handed over to move_by_pieces(), which emits code based target settings

Re: [PATCH 4/7] riscv: Move riscv_block_move_loop to separate file

On 11/13/22 16:05, Christoph Muellner wrote: From: Christoph Müllner Let's try to not accumulate too much functionality in one single file as this does not really help maintaining or extending the code. So in order to add more similar functionality like riscv_block_move_loop let's move this f

Re: [PATCH 2/7] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity

On 11/13/22 16:05, Christoph Muellner wrote: From: Christoph Müllner INSNs are usually postfixed by a number representing the argument count. Given the instructions will be used in a later commit, let's make them visible, but add a "riscv_" prefix to avoid conflicts with standard INSNs. gcc/

Re: [PATCH 1/7] riscv: bitmanip: add orc.b as an unspec

On 11/13/22 16:05, Christoph Muellner wrote: From: Philipp Tomsich As a basis for optimized string functions (e.g., the by-pieces implementations), we need orc.b available. This adds orc.b as an unspec, so we can expand to it. gcc/ChangeLog: * config/riscv/bitmanip.md (orcb2): Add

[PATCH] RISC-V: Optimal RVV epilogue logic.

Skip add insn generate if the adjust size equal to zero. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_epilogue): New if control segement. --- gcc/config/riscv/riscv.cc | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) dif

Re: [PATCH 1/2]middle-end: Add new tbranch optab to add support for bit-test-and-branch operations

On 11/14/22 08:56, Tamar Christina wrote: gcc/ChangeLog: * dojump.cc (do_jump): Pass along value. (do_jump_by_parts_greater_rtx): Likewise. (do_jump_by_parts_zero_rtx): Likewise. (do_jump_by_parts_equality_rtx): Likewise. (do_compare_rtx_and_jump): Like

[PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Public] Hi, PFA the patch which adds znver4 instruction reservations separately from older znver versions: * This also models separate div, fdiv and ssediv units accordingly. * Does not blow-up the insn-automata.cc size (it grew from 201502 to 206141 for me.) * The patch successfully builds, b

Re: [PATCH v2 2/2] RISC-V: Add instruction fusion (for ventana-vt1)

On Mon, Nov 14, 2022 at 09:06:10AM -0700, Jeff Law via Gcc-patches wrote: > > On 11/13/22 13:48, Philipp Tomsich wrote: > > The Ventana VT1 core supports quad-issue and instruction fusion. > > This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences > > together and adds idiom matche

Re: [PATCH v2 2/2] RISC-V: Add instruction fusion (for ventana-vt1)

On 11/13/22 13:48, Philipp Tomsich wrote: The Ventana VT1 core supports quad-issue and instruction fusion. This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences together and adds idiom matcheing for the supported fusion cases. gcc/ChangeLog: * config/riscv/riscv.cc (e

Re: [PATCH] libstdc++: Fix python/ not making install directories

On Mon, 14 Nov 2022 at 15:58, Arsen Arsenović wrote: > > > Jonathan Wakely writes: > >> It's the first thing the recipe does: > >> > >> install-data-local: gdb.py > >> @$(mkdir_p) $(DESTDIR)$(toolexeclibdir) > >> > >> That's why I'm suggesting to do the same thing for the debug dir. > > > > Th

RE: [PATCH 2/2]AArch64 Support new tbranch optab.

Hello, Ping and updated patch. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.md (*tb1): Rename to... (*tb1): ... this. (tbranch4): New. gcc/testsuite/ChangeLog: * gcc.targe

Re: [PATCH] libstdc++: Fix python/ not making install directories

Jonathan Wakely writes: >> It's the first thing the recipe does: >> >> install-data-local: gdb.py >> @$(mkdir_p) $(DESTDIR)$(toolexeclibdir) >> >> That's why I'm suggesting to do the same thing for the debug dir. > > This presumably means it has the problems that mkinstalldirs is > supposed t

Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

On Mon, 14 Nov 2022 at 16:52, Jeff Law wrote: > > > On 11/13/22 13:48, Philipp Tomsich wrote: > > The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and > > XVentanaCondOps. > > This introduces a placeholder -mcpu=ventana-vt1, so tooling and > > scripts don't need to change once ful

RE: [PATCH 1/2]middle-end: Add new tbranch optab to add support for bit-test-and-branch operations

> -Original Message- > From: Richard Biener > Sent: Saturday, November 5, 2022 2:23 PM > To: Aldy Hernandez > Cc: Tamar Christina ; Jeff Law > ; gcc-patches@gcc.gnu.org; nd ; > MacLeod, Andrew > Subject: Re: [PATCH 1/2]middle-end: Add new tbranch optab to add support > for bit-test-and-b

Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

On 11/13/22 13:48, Philipp Tomsich wrote: The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and XVentanaCondOps. This introduces a placeholder -mcpu=ventana-vt1, so tooling and scripts don't need to change once full support (pipeline, tuning, etc.) will become public later. gcc

RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.

Hi, > -Original Message- > From: Kyrylo Tkachov > Sent: Monday, November 14, 2022 2:47 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Sandiford > Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU. > > > > > -Original Message- > > From:

Re: [RFC PATCH] ipa-guarded-deref: Add new pass to dereference function pointers

On Mon, Nov 14, 2022 at 2:48 PM Richard Biener wrote: > On Mon, Nov 14, 2022 at 12:46 PM Christoph Müllner > wrote: > > > > > > > > On Mon, Nov 14, 2022 at 11:10 AM Richard Biener < > richard.guent...@gmail.com> wrote: > >> > >> On Mon, Nov 14, 2022 at 10:32 AM Christoph Müllner > >> wrote: > >

[PATCH 2/2] IBM zSystems: Save argument registers to the stack -mpreserve-args

This adds support for preserving the content of parameter registers to the stack and emit CFI for it. This useful for applications which want to implement their own stack unwinding and need access to function arguments. With the -mpreserve-args option GPRs and FPRs are save to the stack slots whic

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