Hi Segher,
On 2019/1/26 AM1:43, Segher Boessenkool wrote:
Hi!
On Wed, Jan 23, 2019 at 03:57:28AM -0600, luo...@linux.vnet.ibm.com wrote:
The 5 new builtins vec_sbox_be, vec_cipher_be, vec_cipherlast_be, vec_ncipher_be
and vec_ncipherlast_be only support vector unsigned char type parameters.
Ad
Hi,
It turns out that the new tests added today actually require POWER8 hardware at
a minimum, since the vec_vsrad interface requires it. (Note that requiring
P8 hardware obviates the need to specify -mvsx, so that is now removed.)
Tested on powerpc64le (P9, P8) and powerpc64 (P7) with correct b
The attached patch removes the assumption introduced earlier today
in my fix for bug 87996 that the valid_constant_size_p argument is
a constant expression. I couldn't come up with a C/C++ test case
where this isn't true but apparently it can happen in Ada which I
inadvertently didn't build. I s
PR lto/88147 reports an assertion failure due to a bogus location_t value
when adding a line to a pre-existing line map, when there's a large
difference between the two line numbers.
For some "large differences", this leads to a location_t value that exceeds
LINE_MAP_MAX_LOCATION, in which case li
On Sun, Feb 10, 2019 at 3:40 AM Svante Signell wrote:
>
> > I've found some problems. Current problem is with the mksysinfo.sh patch.
> > But
> > there are some other things missing. New patches will be submitted tomorrow.
>
> Attached are three additional patches needed to build libgo on GNU/Hur
On Tue, Feb 12, 2019 at 12:15 AM Uros Bizjak wrote:
>
> On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu wrote:
> >
> > Emulate MMX ashr3/3 with SSE. Only SSE register
> > source operand is allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (mmx_ashr3): Changed to define_expand.
>
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i3
On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu wrote:
>
> Emulate MMX ashr3/3 with SSE. Only SSE register
> source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_ashr3): Changed to define_expand.
> Disallow TARGET_MMX_WITH_SSE.
> (mmx_3): Likewise.
>
On Mon, Feb 11, 2019 at 01:43:36PM -0500, Jason Merrill wrote:
> On 2/7/19 6:02 PM, Marek Polacek wrote:
> > Since r268321 we can call digest_init even in a template, when the compound
> > literal isn't instantiation-dependent.
>
> Right. And since digest_init modifies the CONSTRUCTOR in place, t
Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33 ++
When we're instantiating a generic lambda, its enclosing context will
have already been instantiated, so we need to look for that as well.
Tested x86_64-pc-linux-gnu, applying to trunk.
* pt.c (enclosing_instantiation_of): Also check
instantiated_lambda_fn_p for the template conte
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
gcc/config/i38
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (UNSPEC_CVTPI2PS): New.
(sse_cvtpi2ps): Renamed to ...
(*mmx_cvtpi2ps): This. Disab
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.
Since we now emulate MMX intrinsics with SSE in 64-bit mode, we can
enable SSSE3 __m64 tests even when AVX is enabled.
PR target/89021
* gcc.target/i386/ssse3-pabsb.c: Also enable __m64 check in
64-bit mode.
* gcc.target/i386/ssse3-pabsd.c: Likewise.
* gcc.t
PR target/89021
* config/i386/i386.c (ix86_expand_vector_init_duplicate): Set
mmx_ok to true if TARGET_MMX_WITH_SSE is true.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
(ix86_expand_vector_init_general
In 64-bit, we support 8-byte vectorizer with SSE. Also xfail x86-64
targets for gcc.dg/tree-ssa/pr84512.c.
gcc/
PR target/89028
* config/i386/i386.c (ix86_autovectorize_vector_sizes): Enable
8-byte vectorizer for TARGET_MMX_WITH_SSE.
gcc/testsuite/
PR target/890
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md (*vec_
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/c
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --gi
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/conf
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_an
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i3
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/con
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ...
(ssse3_pshufbv8qi3_mmx): This.
(ssse3_pshufbv8
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 22 ++---
Emulate MMX movntq with SSE2 movntidi. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Renamed to ...
(*sse_movntq): This. Require TARGET_MMX and disallow
TARGET_MMX_WITH_SSE.
(sse_movntq): New. Emulate MMX
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 21 +
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 22 +
Emulate MMX maskmovq with SSE2 maskmovdqu in 64-bit mode by zero-extending
source and mask operands to 128 bits. Handle unmapped bits 64:127 at
memory address by adjusting source and mask operands together with memory
address.
PR target/89021
* config/i386/xmmintrin.h: Emulate MMX
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
(umaxmin:v8qi3
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split a
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 del
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Changed to define_expand.
Disallow TARGET_MMX_WITH_SSE.
(mmx_3): Likewise.
(ashr3): New.
(*ashr3): Likewise.
(3): Li
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/mmx.
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
---
gcc/config/i386/mmx.md | 27 ---
1 file c
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
gcc/c
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 21 +--
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
* config/i386/i38
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
gcc/config/i386/mmx.md | 26 +++---
1 file
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386.c (ix86_set_reg_reg_cost): Also support
VALID_MMX_WITH_SSE_REG_MODE.
(ix86_vector_mode_supported_p): Likewi
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h (ix86_move_vec
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE \
(TARGET_64BIT && TARGET_SSE2)
#define TARGET_MMX_WITH_SSE_P(x) \
(TARGET_64BIT_P (x) && TARGET_SSE2_P (x))
;; Define ins
The attached patch moves the check for this F2018 obsolescent feature
to a better place where the warning is only emitted when the COMMON is
declared. No warning should be emitted when such a legacy module is
simply used.
Regtested on x86_64-pc-linux-gnu.
OK for trunk?
Thanks,
Harald
2019-02-1
On Mon, 2019-02-11 at 10:27 -0800, Ian Lance Taylor wrote:
> On Mon, Feb 11, 2019 at 3:10 AM Svante Signell
> wrote:
> > On Sun, 2019-02-10 at 22:08 -0800, Ian Lance Taylor wrote:
> > > On Sun, Feb 10, 2019 at 3:41 AM Svante Signell
> > > wrote:
> > > > On Sat, 2019-02-09 at 23:57 +0100, Svante S
On Mon, Feb 11, 2019 at 4:48 PM Olivier Hainque wrote:
>
> Hi Wilco,
>
> > On 8 Feb 2019, at 22:35, Wilco Dijkstra wrote:
>
> > So I think we need to push much harder on getting rid of obsolete stuff and
> > avoid people encountering these nasty issues.
>
> Numbers I just received indicate that w
On Mon, Feb 11, 2019 at 5:35 PM Wilco Dijkstra wrote:
>
> The GCC optimizer can generate symbols with non-zero offset from simple
> if-statements. Bit zero is used for the Arm/Thumb state bit, so relocations
> with offsets fail if it changes bit zero and the relocation forces bit zero
> to true.
On 2/11/19 1:23 PM, Jakub Jelinek wrote:
On Mon, Feb 11, 2019 at 12:20:42PM -0700, Martin Sebor wrote:
--- gcc/c-family/c-attribs.c(revision 268774)
+++ gcc/c-family/c-attribs.c(working copy)
@@ -4032,8 +4032,12 @@ validate_attribute (location_t atloc, tree oper, t
if (TYPE_P (ope
On Mon, 11 Feb 2019, Wilco Dijkstra wrote:
> > With Gold linker this is handled correctly. So it looks to me like a
> > bug in BFD linker, where it ignores any addend (not just +1/-1) when
> > resolving a relocation against a Thumb function.
>
> If the Gold linker doesn't fail that means Gold has
On Mon, Feb 11, 2019 at 12:20:42PM -0700, Martin Sebor wrote:
> --- gcc/c-family/c-attribs.c (revision 268774)
> +++ gcc/c-family/c-attribs.c (working copy)
> @@ -4032,8 +4032,12 @@ validate_attribute (location_t atloc, tree oper, t
>
>if (TYPE_P (oper))
> tmpdecl = build_decl (atloc,
On 2/8/19 6:18 PM, Jakub Jelinek wrote:
Hi!
Non-type template arguments are constant-expression in the grammar and thus
manifestly constant-evaluated.
For e.g. class templates, convert_nontype_argument is called with
tf_warning_or_error and so while we called in the below spots
maybe_constant_va
On 2/11/19 2:21 PM, Marek Polacek wrote:
On Fri, Feb 08, 2019 at 05:37:00PM -0500, Jason Merrill wrote:
On 2/8/19 12:21 PM, Marek Polacek wrote:
r256999 removed early bailout for pointer-to-member-function types, so we
now try to tsubst each element of a pointer-to-member-function CONSTRUCTOR.
On Mon, Feb 11, 2019 at 8:08 PM H.J. Lu wrote:
>
> On Sun, Feb 10, 2019 at 2:48 AM Uros Bizjak wrote:
> >
> > On 2/10/19, H.J. Lu wrote:
> > > Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
> > >
> > > PR target/89021
> > > * config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation.
>
OK.
On 2/11/19 2:27 PM, Marek Polacek wrote:
This I don't like.
Obvious, but ok?
2019-02-11 Marek Polacek
* typeck2.c (digest_init_r): Remove commented code.
--- gcc/cp/typeck2.c
+++ gcc/cp/typeck2.c
@@ -1099,7 +1099,6 @@ digest_init_r (tree type, tree init, int nested, int
flags
Hi Alexander,
> Just to be sure the issue is analyzed properly: if it's certain that this
> usage
> is not allowed, shouldn't the linker produce a diagnostic instead of silently
> concealing the issue?
The ABI doesn't require this but yes a linker could report a warning if the
addend of a functi
On Mon, Feb 11, 2019 at 7:09 PM H.J. Lu wrote:
>
> On Sun, Feb 10, 2019 at 3:16 AM Uros Bizjak wrote:
> >
> > On 2/10/19, H.J. Lu wrote:
> > > Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
> > >
> > > PR target/89021
> > > * config/i386/mmx.md (mmx_pshufw
On Mon, Feb 11, 2019 at 12:20:42PM -0700, Martin Sebor wrote:
> This is a repost of a patch for PR 88383 updated to also fix the just
> reported PR 89288 (the original patch only partially handles this case).
> The review of the first patch was derailed by questions about the design
> of the built-
This I don't like.
Obvious, but ok?
2019-02-11 Marek Polacek
* typeck2.c (digest_init_r): Remove commented code.
--- gcc/cp/typeck2.c
+++ gcc/cp/typeck2.c
@@ -1099,7 +1099,6 @@ digest_init_r (tree type, tree init, int nested, int
flags,
tree typ1 = TYPE_MAIN_VARIANT (TREE_T
On Fri, Feb 08, 2019 at 05:37:00PM -0500, Jason Merrill wrote:
> On 2/8/19 12:21 PM, Marek Polacek wrote:
> > r256999 removed early bailout for pointer-to-member-function types, so we
> > now try to tsubst each element of a pointer-to-member-function CONSTRUCTOR.
> >
> > That's fine but the proble
This is a repost of a patch for PR 88383 updated to also fix the just
reported PR 89288 (the original patch only partially handles this case).
The review of the first patch was derailed by questions about the design
of the built-in so the fix for the ICE was never approved. I think
the ICEs shoul
On Sun, Feb 10, 2019 at 2:48 AM Uros Bizjak wrote:
>
> On 2/10/19, H.J. Lu wrote:
> > Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
> >
> > PR target/89021
> > * config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation.
> > (sse_cvttps2pi): Likewise.
>
> It looks to me that this
On Thu, 2019-02-07 at 18:13 +, Wilco Dijkstra wrote:
> External Email
>
> Hi Steve,
>
> > > After special cases you could do something like t = mask2 +
> > > (HWI_1U << shift);
> > > return t == (t & -t) to check for a valid bfi.
> >
> > I am not sure I follow this logic and my attempts to u
On 2/7/19 6:02 PM, Marek Polacek wrote:
Since r268321 we can call digest_init even in a template, when the compound
literal isn't instantiation-dependent.
Right. And since digest_init modifies the CONSTRUCTOR in place, that
means the template trees are digested rather than the original parse
Svante Signell, le lun. 11 févr. 2019 12:10:21 +0100, a ecrit:
> WCONTINUED is not defined, I assume that WIFCONTINUED is not supported.
>
> From waitpid(2):
> WCONTINUED (since Linux 2.6.10)
>also return if a stopped child has been resumed by delivery of SIGCONT.
>
> @Samuel: more info?
git
On Mon, Feb 11, 2019 at 3:10 AM Svante Signell wrote:
>
> On Sun, 2019-02-10 at 22:08 -0800, Ian Lance Taylor wrote:
> > On Sun, Feb 10, 2019 at 3:41 AM Svante Signell
> > wrote:
> > > On Sat, 2019-02-09 at 23:57 +0100, Svante Signell wrote:
> > > > On Sat, 2019-02-09 at 14:40 -0800, Ian Lance Ta
Ping: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00224.html
(This patch also handles bug 88835.)
On 2/4/19 8:58 PM, Martin Sebor wrote:
The attached patch relaxes -Wformat-overflow=2 to avoid warning about
individual directives that might (but need not) exceed the 4095 byte
limit, and about
Tamar Christina writes:
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index
> 5df5a8b78439e69705e62845a4d1f86166a01894..59f03e688e58c1aab37629555c7b3f19e5075935
> 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -3414,6 +3414,14
Fix test errors on targets which do not support pthreads.
Committed as obvious.
ChangeLog:
2019-02-11 Wilco Dijkstra
PR tree-optimization/86637
* gcc.c-torture/compile/pr86637-2.c: Test pthread and graphite target.
---
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr86637-2
On Mon, 11 Feb 2019, Wilco Dijkstra wrote:
> The GCC optimizer can generate symbols with non-zero offset from simple
> if-statements. Bit zero is used for the Arm/Thumb state bit, so relocations
> with offsets fail if it changes bit zero and the relocation forces bit zero
> to true. The fix is to
On Sun, Feb 10, 2019 at 3:16 AM Uros Bizjak wrote:
>
> On 2/10/19, H.J. Lu wrote:
> > Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (mmx_pshufw_1): Add SSE emulation.
> > (*vec_dupv4hi): Likewise.
> >
My patch for 86943 on the branch removed this code, which led to a location
change on one of the diagnostics in constexpr-lambda8.C. Removing this bit
wasn't the point of the patch, so let's put it back.
Applying to 8 branch.
* pt.c (tsubst_copy_and_build): Do still clear expr location
Bootstrapped and regtested on s390x-redhat-linux.
The previous attempt to fix PR89233 [1] went into wrong direction of
dealing with symptoms rather than the root cause. Since the approach
here is completely different, I'm not sending it as v2.
The following insn:
(insn (set (reg:DI %r2)
The GCC optimizer can generate symbols with non-zero offset from simple
if-statements. Bit zero is used for the Arm/Thumb state bit, so relocations
with offsets fail if it changes bit zero and the relocation forces bit zero
to true. The fix is to disable offsets on function pointer symbols.
ARM
Hello Ramana,
> Olivier, while you are here could you also document the choices made by
> the vxworks port in terms of the ABI and how it differs from EABI ? It
> would certainly help with patch review.
Thanks for your feedback as well.
Yes, I'll add a comment and macro defs to the VxWorks
heade
Hi Wilco,
> On 8 Feb 2019, at 22:35, Wilco Dijkstra wrote:
> So I think we need to push much harder on getting rid of obsolete stuff and
> avoid people encountering these nasty issues.
Numbers I just received indicate that we can legitimately head
in this direction for VxWorks as well (move tow
> I noticed the comments in the test don't correspond to what it's
> designed to exercise: namely that the call to hot_function() is
> inlined and the call to cold_function() is not, rather than
> the other way around.
>
> Attached is a patch that adjusts the comments. Honza, please let
> me know
I noticed the comments in the test don't correspond to what it's
designed to exercise: namely that the call to hot_function() is
inlined and the call to cold_function() is not, rather than
the other way around.
Attached is a patch that adjusts the comments. Honza, please let
me know if this look
On Mon, Feb 11, 2019 at 02:16:27PM +, Дилян Палаузов wrote:
> Hello Segher,
>
> my question was how do you propose to proceed, so that a
> no-reminders-for-patches-are-necessary-state is reached.
>
> There is no relation with having infinite time or dealing with high-cost
> low-profit patch
On Mon, Feb 11, 2019 at 04:56:45PM +0100, Uros Bizjak wrote:
> > Let's first define what MODE_XI means in standard_sse_constant_opcode
> > as well as in all these mov patterns for with and without AVX512VL.
> > Without
> > a clear definition, we can't get out of this mess.
>
> INT_MODE (OI, 32)
On 2/11/19 10:01 AM, Segher Boessenkool wrote:
> Hi Bill,
>
> On Mon, Feb 11, 2019 at 07:36:11AM -0600, Bill Schmidt wrote:
>> 2019-02-11 Bill Schmidt
>>
>> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Shift-right
>> and shift-left vector built-ins need to include a TRUNC_MO
On 11/02/19 15:17, Tamar Christina wrote:
Hi all,
After the register allocator changes of r268705 we need to update a few tests
with new output.
In all cases the compiler is now generating the expected code, since the tests
are all float16 testcases using a hard-floar abi, we expect that actu
In Mon, Feb 11, 2019 at 7:56 AM Uros Bizjak wrote:
>
> On Mon, Feb 11, 2019 at 3:32 PM H.J. Lu wrote:
> >
> > On Mon, Feb 11, 2019 at 5:51 AM Uros Bizjak wrote:
> > >
> > > On Mon, Feb 11, 2019 at 2:29 PM H.J. Lu wrote:
> > >
> > > > > No. As said, please correctly set mode to XImode in mode at
Hi Bill,
On Mon, Feb 11, 2019 at 07:36:11AM -0600, Bill Schmidt wrote:
> 2019-02-11 Bill Schmidt
>
> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Shift-right
> and shift-left vector built-ins need to include a TRUNC_MOD_EXPR
> for correct semantics.
>
> [gcc/testsu
On Mon, Feb 11, 2019 at 3:32 PM H.J. Lu wrote:
>
> On Mon, Feb 11, 2019 at 5:51 AM Uros Bizjak wrote:
> >
> > On Mon, Feb 11, 2019 at 2:29 PM H.J. Lu wrote:
> >
> > > > No. As said, please correctly set mode to XImode in mode attribute
> > > > calculation.
> > >
> > > There is
> > >
> > > swit
> -Original Message-
> From: James Greenhalgh
> Sent: 06 February 2019 17:42
> To: Alejandro Martinez Vicente
> Cc: GCC Patches ; nd ; Richard
> Sandiford ; Richard Biener
>
> Subject: Re: [Aarch64][SVE] Vectorise sum-of-absolute-differences
>
> On Mon, Feb 04, 2019 at 07:34:05AM -0600,
Hi all,
After the register allocator changes of r268705 we need to update a few tests
with new output.
In all cases the compiler is now generating the expected code, since the tests
are all float16 testcases using a hard-floar abi, we expect that actual fp16
instructions are used rather than usin
Hi All,
On AArch64 aarch64_classify_address has a case for when it's non-strict
that will allow it to accept any byte offset from a reg when validating
an address in a given addressing mode.
This because reload would later make the address valid. SVE however requires
the address always be valid,
On 2/11/19 8:11 AM, Segher Boessenkool wrote:
> On Mon, Feb 11, 2019 at 07:17:16AM -0600, Bill Schmidt wrote:
>> At -O0 (if I hand-inline everything myself to avoid errors), we scalarize
>> the modulo/masking operation into a rldicl for each doubleword. I really
>> don't see any reason to change t
On 10/02/19 09:42, Christophe Lyon wrote:
>
> Both this simple patch or the previous fix all the ICEs I reported, thanks.
>
> Of course, the scan-assembler failures remain to be fixed.
>
In the testcase I failed to account for targets that don't support arm
mode or
targets that do not support
On Mon, Feb 11, 2019 at 5:51 AM Uros Bizjak wrote:
>
> On Mon, Feb 11, 2019 at 2:29 PM H.J. Lu wrote:
>
> > > No. As said, please correctly set mode to XImode in mode attribute
> > > calculation.
> >
> > There is
> >
> > switch (get_attr_type (insn))
> > {
> > case TYPE_SSELOG1:
> >
Hi Wilco,
Thanks for your feedback.
> On 8 Feb 2019, at 22:35, Wilco Dijkstra wrote:
>
> Hi Olivier,
>
>> Sorry, I had -mapcs-frame in mind.
>
> That's identical to -mapcs, and equally deprecated. It was superceded 2
> decades
> ago. -mpcs-frame bugs have been reported multiple times, includ
Hello Segher,
my question was how do you propose to proceed, so that a
no-reminders-for-patches-are-necessary-state is reached.
There is no relation with having infinite time or dealing with high-cost
low-profit patches.
Previously I raised the quesion, whether automating the process for sendi
On Mon, Feb 11, 2019 at 07:17:16AM -0600, Bill Schmidt wrote:
> At -O0 (if I hand-inline everything myself to avoid errors), we scalarize
> the modulo/masking operation into a rldicl for each doubleword. I really
> don't see any reason to change the code.
So what does this look like at expand (at
On Mon, Feb 11, 2019 at 12:44:31PM +, Дилян Палаузов wrote:
> -- at https://www.gnu.org/software/gcc/contribute.html is written “If you do
> not receive a response to a patch that you
> have submitted within two weeks or so, it may be a good idea to chase it by
> sending a follow-up email to
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