Re: Late-breaking jit features (was Re: [PATCH][gcc] libgccjit: introduce gcc_jit_context_add_driver_option)

On February 1, 2019 10:11:12 PM GMT+01:00, David Malcolm wrote: >On Mon, 2019-01-21 at 08:40 +, Andrea Corallo wrote: >> Hi all, >> Second version of the patch addressing David's comment about all-non- >> failing-tests.h >> >> Adds gcc_jit_context_add_driver_option to the libgccjit ABI and a

[C++ PATCH] PR c++/88761 - ICE with reference capture of constant.

Here, we capture nf, then the use of the proxy decays to a constant during semantic processing of +nf. Since we saw some decay from proxy to constant, we walk through the lambda body to see which proxies are still used, but we weren't walking into subtrees of DECL_EXPR at all, so we missed the use

Re: [PATCH 00/46] Implement MMX intrinsics with SSE

On Fri, Feb 1, 2019 at 4:50 PM Andi Kleen wrote: > > "H.J. Lu" writes: > > > To support it, we disable > > MMX by default in 64-bit mode so that MMX registers won't be available > > Wouldn't that break inline assembler that references MMX register clobbers? Yes. You need to use -mmmx explicitly

Re: [PATCH 00/46] Implement MMX intrinsics with SSE

"H.J. Lu" writes: > To support it, we disable > MMX by default in 64-bit mode so that MMX registers won't be available Wouldn't that break inline assembler that references MMX register clobbers? -Andi

[committed] Fix omp declare simd ICE (PR middle-end/87887)

Hi! We can't create a vector type with aggregate elements. In the past we used to reject BLKmode aggregates, but accepted (and ICEd on) [QHSD]Imode aggregates. On the other side, as the FIXME says, we should accept any argument type if it is uniform (linear should be only integers or pointers or

libgo patch committed: Add Hurd netpoll and semaphore support

This patch by Svante Signell adds Hurd netpoll and semaphore support to the runtime package. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/gofronte

Re: [PATCH] Handle timeout warnings in dg-extract-results

On Jan 23, 2019, at 5:16 AM, Christophe Lyon wrote: > What do people think about this? Seems reasonable.

Re: libgo patch committed: Hurd configury

And this patch adds the new expected file, libgo/runtime/getncpu-hurd.c. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/gofrontend/MERGE (revisi

Re: [PATCH] Fix Fortran handling of PARAMETERs in BLOCK which is not the first statement in function (PR fortran/83246, PR fortran/89084)

On Fri, Feb 01, 2019 at 11:36:27PM +0100, Jakub Jelinek wrote: > > As mentioned in the PR, the following testcases FAIL, because a VAR_DECL > for a PARAMETER inside of a BLOCK is not added to the BIND_EXPR vars and > thus the middle-end doesn't consider it defined. > > The problem is in the follo

Re: [PATCH] Move stack protector epilogue before loading return hard reg(s) from pseudo(s) (PR rtl-optimization/87485)

> So, can we e.g. keep emitting the epilogue where it is now for > naked_return_label != NULL_RTX and move it otherwise? > For __builtin_return the setter and use of the hard register won't be > adjacent in any case. See my comment in the audit trail of the PR; I'd suspend it and go to bed. ;-) -

libgo patch committed: Hurd configury

This libgo patch by Svante Signell adds Hurd configury support, and also sysinfo/sigtab support. On Hurd systems it expects a file that will be added in a later patch. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE ===

Re: [PATCH] Move stack protector epilogue before loading return hard reg(s) from pseudo(s) (PR rtl-optimization/87485)

On Fri, Feb 01, 2019 at 11:37:06PM +0100, Eric Botcazou wrote: > > As discussed in the PR and suggested by Uros, scheduler has code to keep a > > use of hard register next to the assignment that sets that hard register > > from a pseudo, which is desirable so that RA can deal with it properly. > >

[omp] Move NE_EXPR handling to omp_adjust_for_condition

Hi, even after the two previous HSA fixes, there is still one remining libgomp failure in the testsuite when run on an HSA-enabled APU. The problem is that grid calculation does not work with NE_EXPR conditions in omp loop constructs which is now permitted in OpenMP 5. The patch below fixes it b

Re: [PATCH] Move stack protector epilogue before loading return hard reg(s) from pseudo(s) (PR rtl-optimization/87485)

> As discussed in the PR and suggested by Uros, scheduler has code to keep a > use of hard register next to the assignment that sets that hard register > from a pseudo, which is desirable so that RA can deal with it properly. > Unfortunately, with -fstack-protector* we stick the stack protect epilo

[PATCH] Fix Fortran handling of PARAMETERs in BLOCK which is not the first statement in function (PR fortran/83246, PR fortran/89084)

Hi! As mentioned in the PR, the following testcases FAIL, because a VAR_DECL for a PARAMETER inside of a BLOCK is not added to the BIND_EXPR vars and thus the middle-end doesn't consider it defined. The problem is in the following test, which passes for all the PR67885 tests, but doesn't really t

[PATCH] Move stack protector epilogue before loading return hard reg(s) from pseudo(s) (PR rtl-optimization/87485)

Hi! As discussed in the PR and suggested by Uros, scheduler has code to keep a use of hard register next to the assignment that sets that hard register from a pseudo, which is desirable so that RA can deal with it properly. Unfortunately, with -fstack-protector* we stick the stack protect epilogue

Re: libgo patch committed: Add hurd build tags

And this patch by adds more hurd build tags, this time to test files. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/gofrontend/MERGE (revision

libgo patch committed: Add hurd build tags

This libgo patch bySvante Signell adds hurd build tags. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/gofrontend/MERGE (revision 268458) +++ gc

libgo patch committed: Use __atomic intrinsics instead of __sync

This patch changes libgo to use the __atomic intrinsics instead of the older __sync intrinsics. libgo already used some __atomic calls; this replaces all the __sync calls. GCC has supported the __atomic intrinsics since 4.7. They are better than the __sync intrinsics in that they specify a memor

Re: [PATCH] [og8] Allow optional arguments to be used in the use_device OpenACC clause

I have retested all the failing cases and they now pass with the attached patch. I will commit this to openacc-gcc-8-branch now as the fix is obvious. Kwok On 01/02/2019 6:02 pm, Kwok Cheung Yeung wrote: There is an error in the logic here: --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -8938,18

[PATCH 11/46] i386: Emulate MMX ashr3/3 with SSE

Emulate MMX ashr3/3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (ashr3): New. (3): Likewise. --- gcc/config/i386/mmx.md | 34 ++ 1 file changed, 34 insertions(+) diff --git a/gcc/config/i386/

[PATCH 16/46] i386: Emulate MMX pshufw with SSE

Emulate MMX pshufw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pshufw_1): Check TARGET_MMX_WITH_SSE for SSE emulation. (*vec_dupv4hi): Add SSE emulation. --- gcc/config/i386/mmx.md | 25 +++--

[PATCH 41/46] i386: Add tests for MMX intrinsic emulations with SSE

Test MMX intrinsics with -msse2 -mno-mmx in 64-bit mode. PR target/89021 * gcc.target/i386/mmx-vals.h: New file. * gcc.target/i386/sse2-mmx-2.c: Likewise. * gcc.target/i386/sse2-mmx-3.c: Likewise. * gcc.target/i386/sse2-mmx-4.c: Likewise. * gcc.targe

[PATCH 46/46] i386: Implement V2SF comparisons with SSE

In 64-bit mode, implement V2SF comparisons with SEE. Only SSE register source operand is allowed. gcc/ PR target/89028 * config/i386/sse.md (V_128_64): New mode iterator. (VF_128_64): Likewise. (sseintvecmode): Add V2SF. (sseintvecmodelower): Likewise.

[PATCH 40/46] i386: Don't enable MMX in 64-bit mode by default

In 64-bit mode, don't enable MMX by default and allow SSE/SSE2/SSSE3 to emulate MMX intrinsics when MMX is disabled. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" no longer ICEs in 64-bit mode since MMX intrinsics are supported now when MMX is disabled. gcc/ PR target/89021

[PATCH 42/46] i386: Also enable SSSE3 __m64 tests without MMX

Since we now emulate MMX intrinsics with SSE when MMX is disabled, we can enable SSSE3 __m64 tests without MMX even when AVX is enabled. PR target/89021 * gcc.target/i386/ssse3-pabsb.c: Also enable __m64 check when MMX is disabled. * gcc.target/i386/ssse3-pabsd.c: L

[PATCH 38/46] i386: Allow MMXMODE moves without MMX

In 64-bit mode, allow MMXMODE moves with SSE when MMX is disabled. PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Check TARGET_MMX_INSNS instead of TARGET_MMX. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.

[PATCH 43/46] i386: Enable 8-byte vectorizer for TARGET_MMX_WITH_SSE

In 64-bit, we support 8-byte vectorizer with SSE when MMX is disabled. Also xfail x86-64 targets for gcc.dg/tree-ssa/pr84512.c. gcc/ PR target/89028 * config/i386/i386.c (ix86_autovectorize_vector_sizes): Enable 8-byte vectorizer for TARGET_MMX_WITH_SSE. gcc/testsuite/

[PATCH 39/46] i386: Allow MMX vector expanders with SSE

In 64-bit mode, allow MMX vector expanders with SSE when MMX is disabled. PR target/89021 * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set mmx_ok to true if TARGET_MMX_WITH_SSE is true. (ix86_expand_vector_init_one_nonzero): Likewise. (ix86_expa

[PATCH 37/46] i386: Emulate MMX abs2 with SSE

Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i3

[PATCH 44/46] i386: Implement V2SF add/sub/mul with SEE

In 64-bit mode, implement V2SF add/sub/mul with SEE. Only SSE register source operand is allowed. gcc/ PR target/89028 * config/i386/i386.md (comm): Handle mult. * config/i386/mmx.md (plusminusmult): New. (plusminusmult_insn): Likewse. (plusminusmult_mnemo

[PATCH 45/46] i386: Implement V2SF <-> V2SI conversions with SEE

In 64-bit mode, implement V2SF <-> V2SI conversions with SEE. Only SSE register source operand is allowed. gcc/ PR target/89028 * config/i386/sse.md (floatv2siv2sf2): New. (fix_truncv2sfv2si2): Likewise. gcc/testsuite/ PR target/89028 * gcc.target/i386/p

[PATCH 36/46] i386: Emulate MMX ssse3_palignrdi with SSE

Emulate MMX version of palignrq with SSE version by concatenating 2 64-bit MMX operands into a single 128-bit SSE operand, followed by SSE psrldq. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_palignrdi): Changed to define_insn_an

[PATCH 34/46] i386: Emulate MMX pshufb with SSE version

Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ... (ssse3_pshufbv8qi3_mmx): This. (ssse3_pshufbv8

[PATCH 32/46] i386: Emulate MMX ssse3_pmaddubsw with SSE

Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation. --- gcc/config/i386/sse.md | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/confi

[PATCH 28/46] i386: Emulate MMX movntq with SSE2 movntidi

Emulate MMX movntq with SSE2 movntidi. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Renamed to ... (*sse_movntq): This. (sse_movntq): New. Emulate MMX movntq with SSE2 movntidi. --- gcc/config/i386/mmx.md | 16 ++

[PATCH 25/46] i386: Emulate MMX mmx_uavgv8qi3 with SSE

Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (*mmx_uavgv8qi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i38

[PATCH 29/46] i386: Emulate MMX umulv1siv1di3 with SSE2

Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (*sse2_umulv1siv1di3): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/gcc/

[PATCH 33/46] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/

[PATCH 35/46] i386: Emulate MMX ssse3_psign3 with SSE

Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_psign3): Add SSE emulation. --- gcc/config/i386/sse.md | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386

[PATCH 30/46] i386: Emulate MMX ssse3_phwv4hi3 with SSE

Emulate MMX ssse3_phwv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phwv4hi3): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i386/sse.m

[PATCH 31/46] i386: Emulate MMX ssse3_phdv2si3 with SSE

Emulate MMX ssse3_phdv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phdv2si3): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i386/sse.m

[PATCH 27/46] i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/mm

[PATCH 21/46] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE

Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (smaxmin:v4hi3): New. (umaxmin:v8qi3): Likewise. (smaxmin:*mmx_v4hi3): Add SSE emulation. (umaxmin:*mmx_v8qi3): Likewise. ---

[PATCH 26/46] i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/config/i

[PATCH 22/46] i386: Emulate MMX mmx_pmovmskb with SSE

Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i

[PATCH 23/46] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE

Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (*mmx_umulv4hi3_highpart): Add SSE emulation. --- gcc/config/i386/mmx.md | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --

[PATCH 19/46] i386: Emulate MMX mmx_pextrw with SSE

Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/mmx.md b

[PATCH 24/46] i386: Emulate MMX maskmovq with SSE2 maskmovdqu

Emulate MMX maskmovq with SSE2 maskmovdqu by zeroing out the upper 64 bits of the mask operand. A warning is issued since invalid memory access may happen when bits 64:127 at memory location are unmapped: xmmintrin.h:1168:3: note: Emulate MMX maskmovq with SSE2 maskmovdqu may result in invalid m

[PATCH 17/46] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE

Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE. PR target/89021 * config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation. (sse_cvttps2pi): Likewise. --- gcc/config/i386/sse.md | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/gcc/conf

[PATCH 20/46] i386: Emulate MMX mmx_pinsrw with SSE

Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 27 +++ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/gcc/conf

[PATCH 18/46] i386: Emulate MMX sse_cvtpi2ps with SSE

Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (UNSPEC_CVTPI2PS): New. (sse_cvtpi2ps): Renamed to ... (*mmx_cvtpi2ps): This.

[PATCH 15/46] i386: Emulate MMX vec_dupv2si with SSE

Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (*vec_dupv2si): Changed to define_insn_and_split to support SSE emulation. * config/i386/sse.md (*vec_dupv4si): Renamed to ... (vec_dupv4si):

[PATCH 14/46] i386: Emulate MMX mmx_eq/mmx_gt3 with SSE

Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_eq3): Check TARGET_MMX_INSNS instead of TARGET_MMX. (*mmx_eq3): Check TARGET_MMX_INSNS instead of TARGET_MMX. Add SSE support.

[PATCH 12/46] i386: Emulate MMX 3 with SSE

Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:3): New. (any_logic:*mmx_3): Check TARGET_MMX_INSNS instead of TARGET_MMX. Add SSE support. --- gcc/config/i386/mmx.md | 26 +++---

[PATCH 10/46] i386: Emulate MMX mmx_pmaddwd with SSE

Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Check TARGET_MMX_INSNS instead of TARGET_MMX. (*mmx_pmaddwd): Check TARGET_MMX_INSNS instead of TARGET_MMX. Add SSE support. ---

[PATCH 13/46] i386: Emulate MMX mmx_andnot3 with SSE

Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_andnot3): Check TARGET_MMX_INSNS instead of TARGET_MMX. Add SSE support. --- gcc/config/i386/mmx.md | 18 +++--- 1 file changed, 11 insert

[PATCH 09/46] i386: Emulate MMX smulv4hi3_highpart with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Check TARGET_MMX_INSNS instead of TARGET_MMX. (*mmx_smulv4hi3_highpart): Check TARGET_MMX_INSNS instead of TARGET_MMX.

[PATCH 08/46] i386: Emulate MMX mulv4hi3 with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mulv4hi3): New. (*mmx_mulv4hi3): Check TARGET_MMX_INSNS instead of TARGET_MMX. Add SSE support. --- gcc/config/i386/mmx.md | 25 ++

[PATCH 05/46] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2

Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/constraints.md (Yx): Any SSE register if MMX is disabled in 64-bit mo

[PATCH 03/46] i386: Allow 64-bit vector modes in SSE registers

In 64-bit mode, we can use SSE2 to support 64-bit vectors. PR target/89021 * config/i386/i386.h (VALID_SSE_REG_MODE): Allow 64-bit vector modes for TARGET_MMX_WITH_SSE. (VALID_SSE2_REG_MODE): Likewise. --- gcc/config/i386/i386.h | 12 ++-- 1 file changed, 1

[PATCH 00/46] Implement MMX intrinsics with SSE

On x86-64, since __m64 is returned and passed in XMM registers, we can implement MMX intrinsics with SSE instructions. To support it, we disable MMX by default in 64-bit mode so that MMX registers won't be available with x86-64. Most of MMX instructions have equivalent SSE versions and results of

[PATCH 07/46] i386: Emulate MMX plusminus/sat_plusminus with SSE

Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (3): New. (*mmx_3): Changed to define_insn_and_split to support SSE emulation. (*mmx_3): Likewise. (mmx_3): Check TARGET_

[PATCH 02/46] libitm: Support _ITM_TYPE_M64 with SSE2 in 64-bit mode

In 64-bit mode when MMX is disabled, we can use SSE2 emulate MMX intrinsics. PR target/89021 * libitm.h (_ITM_TYPE_M64): Also enabled with SSE2 in 64-bit mode. --- libitm/libitm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libitm/libitm.h b/libitm/libitm.h

[PATCH 06/46] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX

Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX, move bits 64:127 to bits 0:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/i386-protos.h (ix86_split_mmx_punpck): New prototype. * config/i386/i38

[PATCH 01/46] i386: Add TARGET_MMX_INSNS and TARGET_MMX_WITH_SSE

In 64-bit mode when MMX is disabled, SSE2 can be used to emulate MMX instructions. PR target/89021 * config/i386/i386.h (TARGET_MMX_INSNS): New. (TARGET_MMX_INSNS_P): Likewise. (TARGET_MMX_WITH_SSE): Likewise. (TARGET_MMX_WITH_SSE_P): Likewise. --- gcc/conf

[PATCH 04/46] i386: Allow UNSPECV_EMMS with SSE2 in 64-bit mode

In 64-bit mode, also support __builtin_ia32_emms with SSE2. PR target/89021 * config/i386/mmx.md (UNSPECV_EMMS): Replace TARGET_MMX with TARGET_MMX_INSNS. --- gcc/config/i386/mmx.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/i386/mmx.md

Late-breaking jit features (was Re: [PATCH][gcc] libgccjit: introduce gcc_jit_context_add_driver_option)

On Mon, 2019-01-21 at 08:40 +, Andrea Corallo wrote: > Hi all, > Second version of the patch addressing David's comment about all-non- > failing-tests.h > > Adds gcc_jit_context_add_driver_option to the libgccjit ABI and a > testcase for it. > > Using this interface is now possible to pass op

[PATCH, rs6000] Correct dg directives on recently added vec-extract tests

Overnight regression testing revealed a portability problem with several recently installed tests. The tests were observed to fail on a power7 test platform. The tests, which are intended to execute, are compiled with -mcpu=power8. Thus, they require power 8 hardware. I have regression tes

[C++ Patch] PR 88986 ("[7/8/9 Regression] ICE: tree check: expected tree that contains 'decl minimal' structure, have 'error_mark' in member_vec_binary_search, at cp/name-lookup.c:1136")

Hi, I think that this ICE on invalid (and valid, for c++17+) can be in fact avoided by accepting in make_typename_type a TYPE_PACK_EXPANSION as context, thus by not triggering the "‘T ...’ is not a class" error. Not sure if a better fix would be something more general. Note, anyway, that we a

Re: Move -Wmaybe-uninitialized to -Wextra

On Fri, 1 Feb 2019, Jeff Law wrote: On 2/1/19 7:01 AM, Marek Polacek wrote: On Fri, Feb 01, 2019 at 07:19:25AM -0600, Segher Boessenkool wrote: Hi Marc, On Fri, Feb 01, 2019 at 12:32:45PM +0100, Marc Glisse wrote: -Wmaybe-uninitialized generates false positives, we can tweak the compiler to

Re: C++ PATCH for c++/88325 - ICE with invalid out-of-line template member definition

On Fri, Feb 01, 2019 at 12:02:44PM -0500, Jason Merrill wrote: > On 2/1/19 11:26 AM, Marek Polacek wrote: > > On Wed, Jan 30, 2019 at 01:39:11PM -0500, Jason Merrill wrote: > > > On 1/28/19 9:46 PM, Marek Polacek wrote: > > > > This patch fixes an ICE-on-invalid (becase out-of-line constructors >

Re: [og8] OpenACC 'kernels' construct changes: splitting of the construct into several regions

Hi! On Fri, 01 Feb 2019 00:59:30 +0100, I wrote: > From c7713be32fc5eace2b1e9c20447da849d23f6076 Mon Sep 17 00:00:00 2001 > From: =?UTF-8?q?Gerg=C3=B6=20Barany?= > Date: Wed, 23 Jan 2019 22:11:11 -0800 > Subject: [PATCH 6/9] Adjust parallelism of loops in gang-single parts of > OpenACC kernels r

Re: [Patch, fortran] PR88393 - [7/8/9 Regression] [OOP] Segfault with type-bound assignment

On Fri, Feb 01, 2019 at 06:15:21PM +, Paul Richard Thomas wrote: > I will commit this patch as 'obvious' tomorrow. > > Cheers > > Paul > > 2019-02-01 Paul Thomas > > PR fortran/88393 > * trans-expr.c (gfc_conv_procedure_call): For derived entities, > passed in parentheses to

Re: Move -Wmaybe-uninitialized to -Wextra

On 2/1/19 7:01 AM, Marek Polacek wrote: > On Fri, Feb 01, 2019 at 07:19:25AM -0600, Segher Boessenkool wrote: >> Hi Marc, >> >> On Fri, Feb 01, 2019 at 12:32:45PM +0100, Marc Glisse wrote: >>> -Wmaybe-uninitialized generates false positives, we can tweak the compiler >>> to reduce them, but there

[PATCH] [8/9 Regression] i386: Add pass_remove_partial_avx_dependency

On Mon, Jan 28, 2019 at 9:08 AM H.J. Lu wrote: > > On Tue, Jan 22, 2019 at 5:28 AM H.J. Lu wrote: > > > > On Tue, Jan 22, 2019 at 4:08 AM Richard Biener > > wrote: > > > > > > On Mon, Jan 21, 2019 at 10:27 PM H.J. Lu wrote: > > > > > > > > On Mon, Jan 21, 2019 at 10:54 AM Jeff Law wrote: > > >

Re: [Patch, fortran] PR88393 - [7/8/9 Regression] [OOP] Segfault with type-bound assignment

On Fri, Feb 01, 2019 at 06:15:21PM +, Paul Richard Thomas wrote: > 2019-02-01 Paul Thomas > > PR fortran/88393 > * trans-expr.c (gfc_conv_procedure_call): For derived entities, > passed in parentheses to class formals, invert the order of > copying allocatable components to

Re: [PATCH] Add simplification rule tanh (x) * cosh (x) -> sinh (x)

On 1/30/19 7:10 AM, Bárbara de Castro Fernandes wrote: > This patch simplifies the function tanh (x) * cosh (x) -> sinh (x). > This rule is derived from the relationship between hyperbolic > functions. > > I ran the tests and gfortran.dg/pr79966.f90 failed, but this failure > is unrelated to the p

[Patch, fortran] PR88393 - [7/8/9 Regression] [OOP] Segfault with type-bound assignment

I will commit this patch as 'obvious' tomorrow. Cheers Paul 2019-02-01 Paul Thomas PR fortran/88393 * trans-expr.c (gfc_conv_procedure_call): For derived entities, passed in parentheses to class formals, invert the order of copying allocatable components to taking taking the

Re: [PATCH] [og8] Allow optional arguments to be used in the use_device OpenACC clause

There is an error in the logic here: --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -8938,18 +8938,51 @@ lower_omp_target (gimple_stmt_iterator *gsi_p, omp_context *ctx) tkind = GOMP_MAP_FIRSTPRIVATE_INT; type = TREE_TYPE (ovar); if (TREE_CODE (type) == ARRAY_T

Re: C++ PATCH for c++/88325 - ICE with invalid out-of-line template member definition

On 2/1/19 11:26 AM, Marek Polacek wrote: On Wed, Jan 30, 2019 at 01:39:11PM -0500, Jason Merrill wrote: On 1/28/19 9:46 PM, Marek Polacek wrote: This patch fixes an ICE-on-invalid (becase out-of-line constructors can't have template arguments and also because function templates can't be partial

Re: C++ PATCH for c++/88325 - ICE with invalid out-of-line template member definition

On Wed, Jan 30, 2019 at 01:39:11PM -0500, Jason Merrill wrote: > On 1/28/19 9:46 PM, Marek Polacek wrote: > > This patch fixes an ICE-on-invalid (becase out-of-line constructors can't > > have > > template arguments and also because function templates can't be partially > > specialized) in C++2a:

Re: [PATCH] [og8] Allow optional arguments to be used in the use_device OpenACC clause

Hi Kwok! On Thu, 31 Jan 2019 18:30:35 +, Kwok Cheung Yeung wrote: > This patch allows for the use of Fortran optional arguments in the > use_device clause of a host_data directive. > > I will push this into openacc-gcc-8-branch later today. Per my testing, it unfortunately also introduces

Re: [Patch, fortran] PR88980 - [9 regression] segfault on allocatable string member assignment

On Fri, Feb 01, 2019 at 01:10:21PM +, Paul Richard Thomas wrote: > This patch is rather simpler than it looks. > > The segfault was occurring because r264724 changed the array reference > for cases like these to use pointer arithmetic to obtain the element. > Unfortunately, in the case, the sp

Re: Move -Wmaybe-uninitialized to -Wextra

On Fri, Feb 01, 2019 at 09:01:53AM -0500, Marek Polacek wrote: > On Fri, Feb 01, 2019 at 07:19:25AM -0600, Segher Boessenkool wrote: > > > Some people tend to consider that > > > if a warning is not part of -Wall, it might as well not exist. Obviously > > > I > > > disagree with that. > > > > I

Re: Go patch committed: Support alias to pointer type as method receiver

On Wed, Jan 30, 2019 at 7:57 AM Ian Lance Taylor wrote: > > This patch by Ben Shi to the Go frontend fixes it to support an > aliases to a pointer type as a method receiver. This fixes > https://golang.org/issue/28252. Bootstrapped and ran Go testsuite on > x86_64-pc-linux-gnu. Committed to mai

Re: [PATCH] Another -fdebug-type-section fix

On 2/1/19 7:29 AM, Richard Biener wrote: This fixes another case where we end up with duplicate stub DIEs and thus build_abbrev_table trying to adjust a DW_AT_signature ref to a local DIE. This happens when we have two unworthy DIEs from different type units rooted in stub DIEs themselves. Her

Re: [PATCH] print correct array sizes in errors (PR 87996)

On 1/31/19 5:49 PM, Martin Sebor wrote: On 1/30/19 3:15 PM, Jason Merrill wrote: On 1/29/19 7:15 PM, Martin Sebor wrote: +  /* Try to convert the original SIZE to a ssizetype.  */ +  if (orig_size != error_mark_node +  && !TYPE_UNSIGNED (TREE_TYPE (orig_size))) +    { + 

Re: [libphobos] Work around lack of dlpi_tls_modid before Solaris 11.5

Hi Johannes, > I'd recommend not using such a workaround: > > This means getTLSRange will always return an empty range, but the GC uses > this to scan TLS memory. This means a GC collection can delete objects > which are still pointed to from TLS. This leads to hard to debug errors, > and if I rem

Re: [PATCH, GCC] PR target/86487: fix the way 'uses_hard_regs_p' handles paradoxical subregs

On 11/01/2019 22:54, Jeff Law wrote: On 1/8/19 8:21 AM, Andre Vieira (lists) wrote: On 07/01/2019 22:50, Jeff Law wrote: On 1/7/19 7:42 AM, Andre Vieira (lists) wrote: Hi, This patch fixes the way 'uses_hard_regs_p' handles paradoxical subregs.   The function is supposed to detect whethe

Re: Move -Wmaybe-uninitialized to -Wextra

On Fri, Feb 01, 2019 at 07:19:25AM -0600, Segher Boessenkool wrote: > Hi Marc, > > On Fri, Feb 01, 2019 at 12:32:45PM +0100, Marc Glisse wrote: > > -Wmaybe-uninitialized generates false positives, we can tweak the compiler > > to reduce them, but there will always be some, that's in the nature of

Re: Provide __start_minfo/__stop_minfo for linkers that don't (PR d/87864)

Hi Johannes, > Looks good to me, although ultimately Iain has to decide of course. fine, thanks. However, if we cannot find an acceptable solution for the lack of dlpi_tls_modid, the patch isn't of much use: * Solaris 11.5 will have all of dlpi_tls_modid and section bracketing. * Solaris 11.4

Re: Fix inconsistent operator delete usages

On 31/01/19 22:29 +0100, François Dumont wrote:     I was writing a test which needed to override the std::nothrow versions of the operator new and delete to control get_temporary_buffer behavior and noticed that it is inconsistent with release_temporary_buffer in terms of new/delete operators.

Re: Move -Wmaybe-uninitialized to -Wextra

Hi Marc, On Fri, Feb 01, 2019 at 12:32:45PM +0100, Marc Glisse wrote: > -Wmaybe-uninitialized generates false positives, we can tweak the compiler > to reduce them, but there will always be some, that's in the nature of > this warning. That is true for *every* warning; if not, it should be an e

[Patch, fortran] PR88980 - [9 regression] segfault on allocatable string member assignment

This patch is rather simpler than it looks. The segfault was occurring because r264724 changed the array reference for cases like these to use pointer arithmetic to obtain the element. Unfortunately, in the case, the span field of the descriptor was not being set during the allocation of the compo

[PATCH] Another -fdebug-type-section fix

This fixes another case where we end up with duplicate stub DIEs and thus build_abbrev_table trying to adjust a DW_AT_signature ref to a local DIE. This happens when we have two unworthy DIEs from different type units rooted in stub DIEs themselves. Here copy_ancestor_tree records the stubs as

[PATCH] Fix PR88597

The following fixes the compile-time explosion for the PR88597 testcase. The fix isn't really "complete" but as usual I'd like to see testcases for other cases. I've queued a more complete fix for GCC 10. The issue is exponential work done by SCEV instantiation which eventually hits "cached" b

Move -Wmaybe-uninitialized to -Wextra

Hello, first, I expect this to be controversial, so feel free to complain. The description of -Wall says "This enables all the warnings about constructions that some users consider questionable, and that are easy to avoid (or modify to prevent the warning), even in conjunction with macros." And

Re: [PATCH][wwwdocs][Arm] Mention the fixed configurations for Cortex-R7 and Cortex-R8

On Fri, 1 Feb 2019, Andre Vieira (lists) wrote: > This patch adds the documentation to the FPU configuration fixes for > Cortex-R7 and Cortex-R8 to changes.html for GCC9. See > https://gcc.gnu.org/ml/gcc-patches/2018-11/msg02183.html Looks good to me. (And I'm happy to see all those improvement

[PATCH][wwwdocs][Arm] Mention the fixed configurations for Cortex-R7 and Cortex-R8

Hi, This patch adds the documentation to the FPU configuration fixes for Cortex-R7 and Cortex-R8 to changes.html for GCC9. See https://gcc.gnu.org/ml/gcc-patches/2018-11/msg02183.html I have validated the html using the W3C validator. Is it OK? Cheers, Andre ? .changes.html.swp ? patch cvs d

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