[PATCH 10/46] i386: Emulate MMX mmx_pmaddwd with SSE

[H.J. Lu]

Emulate MMX pmaddwd with SSE.  Only SSE register source operand is
allowed.

        PR target/89021
        * config/i386/mmx.md (mmx_pmaddwd): Check TARGET_MMX_INSNS
        instead of TARGET_MMX.
        (*mmx_pmaddwd): Check TARGET_MMX_INSNS instead of TARGET_MMX.
        Add SSE support.
---
 gcc/config/i386/mmx.md | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 5ba8b46fc73..fe199b84935 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -850,20 +850,20 @@
            (sign_extend:V2SI
              (vec_select:V2HI (match_dup 2)
                (parallel [(const_int 1) (const_int 3)]))))))]
-  "TARGET_MMX"
+  "TARGET_MMX_INSNS"
   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 
 (define_insn "*mmx_pmaddwd"
-  [(set (match_operand:V2SI 0 "register_operand" "=y")
+  [(set (match_operand:V2SI 0 "register_operand" "=y,Yx,Yy")
         (plus:V2SI
          (mult:V2SI
            (sign_extend:V2SI
              (vec_select:V2HI
-               (match_operand:V4HI 1 "nonimmediate_operand" "%0")
+               (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yy")
                (parallel [(const_int 0) (const_int 2)])))
            (sign_extend:V2SI
              (vec_select:V2HI
-               (match_operand:V4HI 2 "nonimmediate_operand" "ym")
+               (match_operand:V4HI 2 "nonimmediate_operand" "ym,Yx,Yy")
                (parallel [(const_int 0) (const_int 2)]))))
          (mult:V2SI
            (sign_extend:V2SI
@@ -872,10 +872,14 @@
            (sign_extend:V2SI
              (vec_select:V2HI (match_dup 2)
                (parallel [(const_int 1) (const_int 3)]))))))]
-  "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
-  "pmaddwd\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  "TARGET_MMX_INSNS && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+  "@
+   pmaddwd\t{%2, %0|%0, %2}
+   pmaddwd\t{%2, %0|%0, %2}
+   vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "*,noavx,avx")
+   (set_attr "type" "mmxmul,sseiadd,sseiadd")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_pmulhrwv4hi3"
   [(set (match_operand:V4HI 0 "register_operand")
-- 
2.20.1