IS_UNKNOWN_LOCATION is very misleading. This patch removes this macro
from input.h. For sites when checking LOCUS is intended, we explicit
use LOCATION_LOCUS and compare it to UNKNOWN_LOCATION.
Bootstrapped and passed all gcc regression tests.
Ok for trunk?
Thanks,
Dehao
gcc/ChangeLog:
2012-09
Hi, I'm Bethanie. I don't know you.
I found ur account right here, was impressed with it and now write you.
My ex boyfriend and I decided to let us part friends about two weeks ago.
So, I decided to find something new and maybe find it on this site. I did not
use to meet on sites but u really i
This patch to the Go frontend gives a better error message for a switch
on a non-comparable type. Bootstrapped and ran Go testsuite on
x86_64-unknown-linux-gnu. Committed to mainline and 4.7 branch.
Ian
diff -r 74d2d7d217d8 -r f47f5449a663 go/statements.cc
--- a/go/statements.cc Sat Sep 22 00:1
Hi Tom,
On 09/25/2012 10:53 PM, Tom Tromey wrote:
"Magnus" == Magnus Fromreide writes:
Magnus> How does it display the types of the variables us, s and ss in the
Magnus> following code:
It does what you'd expect.
Magnus> I would expect it to say std::basic_string,
Magnus> std::string and std
On Sep 25, 2012, Jakub Jelinek wrote:
> (the other alternative would be to use mode in the hash function etc.,
> but if usually the same pseudo has the same mode everywhere, then the above
> should be good enough).
AFAIK each pseudo is referenced everywhere using the same RTX; if so, it
follows
On 8/15/12, Richard Henderson wrote:
> On 2012-08-15 07:29, Richard Guenther wrote:
> > + typedef typename Element::Element_t Element_t;
>
> Can we use something less ugly than Element_t?
> Such as
>
> typedef typename Element::T T;
>
> ? Given that this name is scoped anyway...
I've been fi
Hi,
This patch (fixed by Richard, I just helped testing) fixes a bug in
the hash function which leads to too many collisions and a 3x compile
time overhead for tramp3d. After applying the patch, the compile time
of tramp3d returns to normal (the same as no block-location patch).
Bootstrapped and
On Mon, Sep 24, 2012 at 2:42 PM, Rong Xu wrote:
> Hi,
>
> This is for google branches only.
> It fix the lino number checksum mismatch during LIPO-use build.
>
> Tested with SPEC and google internal banchmarks.
>
> Thanks,
>
> -Rong
>
> 2012-09-24 Rong Xu
>
> * gcc/coverage.c (coverage_
> "Magnus" == Magnus Fromreide writes:
Magnus> How does it display the types of the variables us, s and ss in the
Magnus> following code:
It does what you'd expect.
Magnus> I would expect it to say std::basic_string,
Magnus> std::string and std::basic_string, but I thought a test
Magnus> ca
On Tue, Sep 25, 2012 at 2:28 PM, Segher Boessenkool
wrote:
> How's this?
>
>
> Segher
>
>
> 2012-09-25 Segher Boessenkool
>
> gcc/testsuite/
> * gcc.target/powerpc/ppc-ne0-1.c: New.
Okay.
Thanks, David
On Tue, Sep 25, 2012 at 9:12 PM, Matthew Gretton-Dann
wrote:
>> No, I mean using the onlyjump_p predicate.
>
> Again sorry for the delay. Attached is an updated patch using the onlyjump_p
> predicate as suggested by Steven.
+ if (onlyjump_p (BB_END (pred->src)))
Eh, don't you want (!onlyju
On Wednesday 05 September 2012 17:40:23 Steven Bosscher wrote:
> On Wed, Sep 5, 2012 at 3:18 PM, Matthew Gretton-Dann
>
> wrote:
> > On 5 September 2012 13:45, Richard Earnshaw wrote:
> >> On 05/09/12 13:02, Steven Bosscher wrote:
> >>> On Wed, Sep 5, 2012 at 1:42 PM, Matthew Gretton-Dann wrote:
How's this?
Segher
2012-09-25 Segher Boessenkool
gcc/testsuite/
* gcc.target/powerpc/ppc-ne0-1.c: New.
---
gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c | 33 ++
1 files changed, 33 insertions(+), 0 deletions(-)
create mode 100644 gcc/testsuite/gc
On 10/09/12 16:28, Tejas Belagod wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_shift_truncation_mask): Define.
(TARGET_SHIFT_TRUNCATION_MASK): Define.
* config/aarch64/aarch64.h (SHIFT_COUNT_TRUNCATED): Conditionalize on
TARGET_SIMD.
Committed to aarch64-branch
On 10/09/12 16:22, Tejas Belagod wrote:
2012-09-10 Tejas Belagod
gcc/
* config/aarch64/arm_neon.h (vrshrn_high_n_s16, vrshrn_high_n_s32,
vrshrn_high_n_s64, vrshrn_high_n_u16, vrshrn_high_n_u32,
vrshrn_high_n_u64, vshrn_high_n_s16, vshrn_high_n_s32, vshrn_high_n_s32,
On 10/09/12 16:20, Tejas Belagod wrote:
2012-09-10 Tejas Belagod
gcc/
* config/aarch64/arm_neon.h (vmovq_n_f64): Add.
Committed to aarch64-branch and aarch64-4.7-branch.
/Marcus
On 10/09/12 16:18, Tejas Belagod wrote:
2012-09-10 Tejas Belagod
gcc/
* config/aarch64/arm_neon.h (vfmaq_lane_f64): Fix prototype and
assembler template accordingly.
Committed to aarch64-branch and aarch64-4.7-branch.
/Marcus
OK.
Jason
On 10/09/12 16:14, Tejas Belagod wrote:
2012-09-10 Tejas Belagod
gcc/
* config/aarch64/aarch64-protos.h (aarch64_simd_imm_scalar_p):
Declare.
* config/aarch64/aarch64.c (aarch64_simd_imm_scalar_p): New.
* config/aarch64/aarch64.md (*movdi_aarch64): Add alternative
On Tue, 25 Sep 2012, Richard Sandiford wrote:
> >> According to my sources the R4650 has a 4-cycle MULT latency (MAD is 3-4
> >> cycles on that processor). An MTHI/MTLO pair will take 2 cycles;
> >> obviously the resulting larger code may adversely affect cache performance
> >> in some scenar
On 10/09/12 16:11, Tejas Belagod wrote:
2012-09-10 Tejas Belagod
gcc/
* config/aarch64/aarch64-simd.md (aarch64_cm): Tighten
predicate for operand 2 of the compare pattern to accept register
or zero.
* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New.
On 10/09/12 16:05, Tejas Belagod wrote:
2012-09-10 Tejas Belagod
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Split Q-reg
vector value move contained in general registers.
Committed to aarch64-branch and aarch64-4.7-branch
/Marcus
On 10/09/12 16:02, Tejas Belagod wrote:
Hi,
This patch expands an Advanced SIMD intrinsic's operand into a constant operand
only if the predicate allows it.
Regression-tested on aarch64-none-elf. OK for aarch64-branch?
Thanks,
Tejas Belagod
ARM.
Changelog
2012-09-10 Tejas Belagod
gcc/
I've committed this patch to aarch64-branch and backported to
aarch64-4.7-branch.
/Marcus
On 10 Sep 2012, at 15:54, Tejas Belagod wrote:
Hi,
The attached patch implements register list support, standard patterns for
struct vector(strided) load-store support and their associated Advanced SIM
A few arm targets were removed from config.gcc, and picochip is only
available with --enable-obsolete. This patch brings config-list.mk
up-to-date in these respects.
2012-09-24 Joern Rennecke
* contrib-list.mk (LIST): Remove arm-freebsd6, arm-linux,
arm-ecos-elf, arm-rtems, ar
On 2012-09-20 22:33 , Ian Lance Taylor wrote:
gcc/:
2012-09-17 Ian Lance Taylor
* diagnostic.c: Include "demangle.h" and "backtrace.h".
(bt_stop): New static array.
(bt_callback, bt_err_callback): New static functions.
(diagnostic_action_after_output): Ca
On Tue, Sep 25, 2012 at 05:59:28PM +0200, Paolo Bonzini wrote:
> Il 25/09/2012 13:19, Jakub Jelinek ha scritto:
> Yes, thanks. Would it make sense to leave -Og in?
Maybe once it matures more. E.g. the scheduler isn't currently
tweaked for -Og (should either not schedule at all, or only
within gr
Hi Ramana,
Here is obvious fix for PR49423, I just added pool range for
arm_zero_extendqisi2, arm_zero_extendqisi2_v6, arm_zero_extendhisi2,
arm_zero_extendhisi2_v6 patterns.
thanks, Dinar.
PR49423.patch
Description: Binary data
Applied the following patches:
PR64641:
http://gcc.gnu.org/viewcvs?view=revision&revision=191714
PR target/54641
* config/avr/t-avr: Use ALL_COMPILERFLAGS instead of ALL_CFLAGS
for sources compiled with COMPILER.
PR54701:
http://gcc.gnu.org/viewcvs?view=revision&revision
On Tue, Sep 25, 2012 at 03:40:10PM +0200, Segher Boessenkool wrote:
> >This is okay, but can you also add a target testcase to check that the
> >correct assembly instructions are generated so that we can try to
> >ensure this does not regress again?
>
> This won't regress in this way again, becaus
Il 25/09/2012 13:19, Jakub Jelinek ha scritto:
> Hi!
>
> On Thu, Sep 13, 2012 at 06:24:14PM +0200, Paolo Bonzini wrote:
>> Il 13/09/2012 17:57, Jakub Jelinek ha scritto:
>>> Can we get this change in? The current state is terribly annoying.
>
> Yes, please go ahead.
>>> Here it is, bo
> I guess I just have to wait for approval by the right maintainer now?
Right, GCC's bureaucracy is no legend. :-)
I've CCed Richard, who approved the __builtin_bswap16 stuff back in April.
--
Eric Botcazou
I am testing the following patch to fix a typo(?) in the hash
function for location ad-hoc data. The current hash function
causes 1000 collisions for each search when building tramp3d.
Bootstrap and regtest running on x86_64-unknown-linux-gnu.
Richard.
2012-09-25 Richard Guenther
P
On 25 September 2012 13:32, Segher Boessenkool
wrote:
>>> Christophe, it looks like the zero-extend in the unsigned case is not
>>> needed on any target? Assuming the shifts are at least SImode, of
>>> course (I'm too lazy to check, sorry).
>>
>>
>> It's also present when compiling:
>> unsigned s
On Tue, 25 Sep 2012, Richard Guenther wrote:
>
> This fixes PR54702 and LTO bootstrap (well, at least I now survive
> stage2 cc1 build). We shouldn't enter builtins into the symtab
> asm-name hash, too much code seems to be confused by that (at least
> we should at most insert builtins with a se
This patch adds support for #pragma GCC warning and #pragma GCC error.
These pragmas can be used from preprocessor macros, unlike the existing
#warning and #error directives. Library authors can use these pragmas
to add deprecation warnings to macros they define.
Bootstrapped and tested on x8
Hi all,
This patch corrects what seemed to be a typo in expand_mov_immediate
in aarch64.c, where we had || instead of an && in our original code.
if (offset != const0_rtx
&& (targetm.cannot_force_const_mem (mode, imm)
|| (can_create_pseudo_p ( // <- should have been &&
A
This is okay, but can you also add a target testcase to check that the
correct assembly instructions are generated so that we can try to
ensure this does not regress again?
This won't regress in this way again, because now the pattern is a
single RTL op. But yes, target tests for this kind of t
On Tue, Sep 25, 2012 at 12:44 AM, Segher Boessenkool
wrote:
> The current patterns will never match. Fix that. Also, merge the
> SI and DI variants of each. Also, remove an unnecessary earlyclobber.
> And add a pattern for what combine considers the canonical form of
> one of these patterns.
>
On 09/25/2012 06:47 AM, Paolo Carlini wrote:
if I understand correctly, in C++11 mode we should simply accept what we
used to accept only with -fpermissive.
Let's also mention -std=c++11 as an alternative to -fpermissive in the
note. OK with that change.
Jason
> Ok. Having dug a bit deeper I think the main problem is that you're
> working against yourself by not handling this pattern right from the
> beginning. You have split the address incorrectly to begin and are
> now trying to recover after the fact.
>
> The following patch seems to do the trick
This fixes PR54702 and LTO bootstrap (well, at least I now survive
stage2 cc1 build). We shouldn't enter builtins into the symtab
asm-name hash, too much code seems to be confused by that (at least
we should at most insert builtins with a set assembler name).
Smells somewhat LTO-ish, but well.
On Tue, 2012-09-25 at 09:14 +0200, Richard Guenther wrote:
> On Mon, 24 Sep 2012, William J. Schmidt wrote:
>
> > In cases where pointers and ints are cast back and forth, SLSR can be
> > tricked into introducing a multiply where one of the operands is of
> > pointer type. Don't do that!
> >
>
On Sun, Sep 23, 2012 at 07:59:37AM -0300, Alexandre Oliva wrote:
> This patch introduces a global mode of dead_debug tracking for use in
> fast DCE. If a debug use reaches the top of a basic block before
> finding its death point, the pending and subsequent uses of the pseudo
> in debug insns will
Jason Merrill writes:
> On 09/20/2012 10:01 AM, Dodji Seketeli wrote:
>> This is because in cplus_decl_attributes, save_template_attributes
>> makes so that the 'unused' attribute is applied to its appertaining
>> entity only at instantiation time. But then at parsing time
>> maybe_warn_unused_l
On Tue, Sep 25, 2012 at 1:23 PM, Jakub Jelinek wrote:
> Hi!
>
> This patch fixes two spots where signed 1-bit precision isn't handled
> properly in VRP. With that type, build_int_cst (TREE_TYPE (min), 1)
> will overflow and thus adding it to something or subtracting leads to
> ICEs or bad code.
Christophe, it looks like the zero-extend in the unsigned case is not
needed on any target? Assuming the shifts are at least SImode, of
course (I'm too lazy to check, sorry).
It's also present when compiling:
unsigned short swapu16(unsigned short x) {
return __builtin_bswap16(x);
}
so it'
On Tue, Sep 25, 2012 at 1:19 PM, Jakub Jelinek wrote:
> Hi!
>
> On Thu, Sep 13, 2012 at 06:24:14PM +0200, Paolo Bonzini wrote:
>> Il 13/09/2012 17:57, Jakub Jelinek ha scritto:
>> >>> > > Can we get this change in? The current state is terribly annoying.
>> >> >
>> >> > Yes, please go ahead.
>> >
Hi!
This patch fixes two spots where signed 1-bit precision isn't handled
properly in VRP. With that type, build_int_cst (TREE_TYPE (min), 1)
will overflow and thus adding it to something or subtracting leads to
ICEs or bad code. In the first spot min is different from max, which
for 1-bit preci
The following fixes the TREE_ADDRESSABLE issue during LTO bootstrap.
We fail to merge all symbols because 'first' may no longer be 'first'.
Committed as obvious. LTO bootstrap is still broken for me:
/tmp/ccXpATTw.ltrans19.ltrans.o: In function `is_ctor_or_dtor.17240':
ccXpATTw.ltrans19.o:(.tex
Hi!
On Thu, Sep 13, 2012 at 06:24:14PM +0200, Paolo Bonzini wrote:
> Il 13/09/2012 17:57, Jakub Jelinek ha scritto:
> >>> > > Can we get this change in? The current state is terribly annoying.
> >> >
> >> > Yes, please go ahead.
> > Here it is, bootstrapped/regtested on x86_64-linux and i686-lin
On Mon, Sep 24, 2012 at 6:10 PM, H.J. Lu wrote:
> On Mon, Sep 24, 2012 at 8:50 AM, Martin Jambor wrote:
>> Hi,
>>
>> On Tue, Sep 18, 2012 at 03:35:45PM +0200, Jan Hubicka wrote:
>>> Hi,
>>> this patch reorganize lto-symtab to work across symtab's symbol table
>>> instead
>>> of building its own.
Hi,
if I understand correctly, in C++11 mode we should simply accept what we
used to accept only with -fpermissive.
Tested x86_64-linux.
Thanks,
Paolo.
//
/cp
2012-09-25 Paolo Carlini
PR c++/54526
* parser.c (cp_parser_template_id): In C++11 mode simpl
On 25 September 2012 07:00, Segher Boessenkool
wrote:
> Christophe, it looks like the zero-extend in the unsigned case is not
> needed on any target? Assuming the shifts are at least SImode, of
> course (I'm too lazy to check, sorry).
>
It's also present when compiling:
unsigned short swapu16(un
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the German team of translators. The file is available at:
http://translationproject.org/latest/gcc/de.po
(This file, 'gcc-4.7.2.de.po', has just
Oleg Endo wrote:
> This patch does some further improvements to the utilization of rotate
> insns on SH. Tested on rev 191657 with
> make -k check RUNTESTFLAGS="--target_board=sh-sim
> \{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
> and no new failures.
>
> OK?
OK.
> (BTW, com
Richard Sandiford writes:
> "Maciej W. Rozycki" writes:
>> On Mon, 24 Sep 2012, Richard Sandiford wrote:
>>
>>> > From the context I am assuming none of this matters for the 74K (and
>>> > presumably the 24KE/34K) and a MULT $0, $0 is indeed faster, but overall
>>> > isn't it something that sh
Hello,
This patch does some further improvements to the utilization of rotate
insns on SH. Tested on rev 191657 with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
and no new failures.
OK?
(BTW, comparing test summaries of rev. 1
"Maciej W. Rozycki" writes:
> On Mon, 24 Sep 2012, Richard Sandiford wrote:
>
>> > From the context I am assuming none of this matters for the 74K (and
>> > presumably the 24KE/34K) and a MULT $0, $0 is indeed faster, but overall
>> > isn't it something that should be decided based on instructi
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: Wednesday, September 05, 2012 6:09 AM
> To: Bin Cheng
> Cc: Ramana Radhakrishnan; 'Eric Botcazou'; gcc-patches@gcc.gnu.org
> Subject: Re: Ping: [PATCH GCC/ARM] Fix problem that hardreg_cprop
> opport
PR target/51274
Also:
PR target/53087
On Mon, Sep 24, 2012 at 10:23 PM, Hans-Peter Nilsson wrote:
> On Fri, 21 Sep 2012, Dehao Chen wrote:
>> This patch moves location_adhoc_data into GC, and also rebuild the
>> hash table when reading in the PCH. After the patch, PCH can work as
>> expected.
>>
>> Bootstrapped and passed gcc regressi
Hello!
Attached patch fixes the combine deficiency, where combine is not able
to recognize combination of:
Trying 6 -> 8:
Failed to match this instruction:
(set (reg:QI 66)
(mem/j:QI (plus:SI (subreg:SI (plus:DI (reg/v:DI 62 [ position ])
(const_int 1 [0x1])) 0)
On Mon, 24 Sep 2012, William J. Schmidt wrote:
> In cases where pointers and ints are cast back and forth, SLSR can be
> tricked into introducing a multiply where one of the operands is of
> pointer type. Don't do that!
>
> Verified that the reduced test case in the PR is fixed with a
> cross-co
On 22 September 2012 06:42, wrote:
> On 20 Sep 2012, at 08:51, "Zhenqiang Chen" wrote:
>
>> Hi,
>>
>> PR 50970 is a general c++ front-end issue for targets which define
>> TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta, although the
>> reporter had issues only on ARM.
>>
>> Root cause:
Hello!
2012-09-25 Uros Bizjak
* gcc.target/i386/pr50725.c: Change 'long' to 'long long'.
Tested on x86_64-pc-linux-gnu, committed to mainline SVN.
Uros.
Index: gcc.target/i386/pr50725.c
===
--- gcc.target/i386/pr50725.c
66 matches
Mail list logo
