[gcc r15-170] config-ml.in: Fix multi-os-dir search

https://gcc.gnu.org/g:70d30dd656957f518b8169a125f6b17f53da8237 commit r15-170-g70d30dd656957f518b8169a125f6b17f53da8237 Author: YunQiang Su Date: Sun May 5 23:12:37 2024 +0800 config-ml.in: Fix multi-os-dir search When building multilib libraries, CC/CXX etc are set with an option

[gcc r15-171] expmed: TRUNCATE value1 if needed in store_bit_field_using_insv

https://gcc.gnu.org/g:7d5d2b879ae7636ca118fb4f3a08b22705cdeacb commit r15-171-g7d5d2b879ae7636ca118fb4f3a08b22705cdeacb Author: YunQiang Su Date: Mon Apr 29 00:33:44 2024 +0800 expmed: TRUNCATE value1 if needed in store_bit_field_using_insv PR target/113179. In `store_bit

[gcc r15-339] MIPS: Support constraint 'w' for MSA instruction

https://gcc.gnu.org/g:9ba01240864ac446052d97692e2199539b7c76d8 commit r15-339-g9ba01240864ac446052d97692e2199539b7c76d8 Author: YunQiang Su Date: Wed May 8 19:04:33 2024 +0800 MIPS: Support constraint 'w' for MSA instruction Support syntax like: asm volatile ("fmadd.d

[gcc r15-393] Revert "MIPS: Support constraint 'w' for MSA instruction"

https://gcc.gnu.org/g:0c6dd4b0973738ce43e76b468a002ab5eb58aaf4 commit r15-393-g0c6dd4b0973738ce43e76b468a002ab5eb58aaf4 Author: YunQiang Su Date: Mon May 13 14:15:38 2024 +0800 Revert "MIPS: Support constraint 'w' for MSA instruction" This reverts commit 9ba01240864ac446052d97692e

[gcc r15-659] MIPS: Remove -m(no-)lra option

https://gcc.gnu.org/g:d3b4ba120ce3b743838c3545a24554989955722a commit r15-659-gd3b4ba120ce3b743838c3545a24554989955722a Author: YunQiang Su Date: Thu May 16 02:30:50 2024 +0800 MIPS: Remove -m(no-)lra option PR target/113955 The `-mlra` option was introduced in 2014 for MIPS,

[gcc r15-3205] MIPS: Include missing mips16.S in libgcc/lib1funcs.S

https://gcc.gnu.org/g:9522fc8bb7812f2ad50eb038e0938bfd958e730f commit r15-3205-g9522fc8bb7812f2ad50eb038e0938bfd958e730f Author: YunQiang Su Date: Fri Aug 23 23:46:16 2024 +0800 MIPS: Include missing mips16.S in libgcc/lib1funcs.S mips16.S was missing since commit 29b74545531f

[gcc r14-10613] MIPS: Include missing mips16.S in libgcc/lib1funcs.S

https://gcc.gnu.org/g:75892d97979f397a66730b97e8279941169e0316 commit r14-10613-g75892d97979f397a66730b97e8279941169e0316 Author: YunQiang Su Date: Fri Aug 23 23:46:16 2024 +0800 MIPS: Include missing mips16.S in libgcc/lib1funcs.S mips16.S was missing since commit 29b74545531

[gcc r15-3388] MIPS: Support vector reduc for MSA

https://gcc.gnu.org/g:f4f72f9b6bcdec8b2ba20a58a241c8d9d631480c commit r15-3388-gf4f72f9b6bcdec8b2ba20a58a241c8d9d631480c Author: YunQiang Su Date: Mon Aug 26 08:45:36 2024 +0800 MIPS: Support vector reduc for MSA We have SHF.fmt and HADD_S/U.fmt with MSA, which can be used for

[gcc r15-3475] RISC-V: Lookup reversely in riscv_select_multilib_by_abi

https://gcc.gnu.org/g:3162abfb5098934e6ed9d4307a86a84d28823612 commit r15-3475-g3162abfb5098934e6ed9d4307a86a84d28823612 Author: YunQiang Su Date: Thu Sep 5 15:14:43 2024 +0800 RISC-V: Lookup reversely in riscv_select_multilib_by_abi When use --print-multi-os-dir or -print-multi-d

[gcc r15-3501] RISC-V: Fix out of index in riscv_select_multilib_by_abi

https://gcc.gnu.org/g:ead5f587dad3206e45db7ac31f5c34c1530ae529 commit r15-3501-gead5f587dad3206e45db7ac31f5c34c1530ae529 Author: YunQiang Su Date: Thu Sep 5 19:55:20 2024 +0800 RISC-V: Fix out of index in riscv_select_multilib_by_abi commit b5c2aae48723c9098a8a3dab1409b30fd87bbf56

[gcc r15-3605] Git ignores .vscode

https://gcc.gnu.org/g:477f7e2808d38c3192894e0109e1f185ad86d3d7 commit r15-3605-g477f7e2808d38c3192894e0109e1f185ad86d3d7 Author: YunQiang Su Date: Fri Sep 6 11:09:13 2024 +0800 Git ignores .vscode ChangeLog * .gitignore: Add .vscode. Diff: --- .gitignore | 1 + 1 fil

[gcc r15-1605] MIPS: Implement vcond_mask optabs for MSA

https://gcc.gnu.org/g:17b368b4b4524ce9d11bf79ce7f58d6825156ce0 commit r15-1605-g17b368b4b4524ce9d11bf79ce7f58d6825156ce0 Author: YunQiang Su Date: Thu Jun 20 01:20:36 2024 +0800 MIPS: Implement vcond_mask optabs for MSA Currently, we have `mips_expand_vec_cond_expr`, which calcula

[gcc r15-1604] MIPS: Output $0 for conditional trap if !ISA_HAS_COND_TRAPI

https://gcc.gnu.org/g:0b456434fe0f1d64291b7c6b3596c836c9519f85 commit r15-1604-g0b456434fe0f1d64291b7c6b3596c836c9519f85 Author: YunQiang Su Date: Wed Jun 19 23:48:26 2024 +0800 MIPS: Output $0 for conditional trap if !ISA_HAS_COND_TRAPI MIPSr6 removes condition trap instructions

[gcc r15-1849] MIPS/testsuite: Fix umips-save-restore-1.c

https://gcc.gnu.org/g:f1437b96029d78e72bd987997f5303e29ebbb9f0 commit r15-1849-gf1437b96029d78e72bd987997f5303e29ebbb9f0 Author: YunQiang Su Date: Fri Jun 28 16:11:35 2024 +0800 MIPS/testsuite: Fix umips-save-restore-1.c With some recent optimization, -O1/-O2/-O3 can archive almos

[gcc r15-1850] MIPS/testsuite: Add -mfpxx to call-clobbered-1.c

https://gcc.gnu.org/g:e08ed5f1c98ea8de086f5c2d1e373aec6e195735 commit r15-1850-ge08ed5f1c98ea8de086f5c2d1e373aec6e195735 Author: YunQiang Su Date: Fri Jun 28 10:08:38 2024 +0800 MIPS/testsuite: Add -mfpxx to call-clobbered-1.c The scan-assembler-times rules only fit for -mfp32 and

[gcc r15-1851] Testsuite/MIPS: Fix msa.c: test7_v2f64, test7_v4f32, test43_v2i64

https://gcc.gnu.org/g:33dfd6798aa3e5f8be58c8810f9814d57485fe12 commit r15-1851-g33dfd6798aa3e5f8be58c8810f9814d57485fe12 Author: YunQiang Su Date: Thu Jun 27 18:05:30 2024 +0800 Testsuite/MIPS: Fix msa.c: test7_v2f64, test7_v4f32, test43_v2i64 BNEGI.W/D are used for test7_v2f64 an

[gcc r15-1852] MIPS: Support more cases with alien mode of SHF.DF

https://gcc.gnu.org/g:320c2ed4d2b4b007bab5ebf0078e6c730ad25d3e commit r15-1852-g320c2ed4d2b4b007bab5ebf0078e6c730ad25d3e Author: YunQiang Su Date: Thu Jun 27 18:28:27 2024 +0800 MIPS: Support more cases with alien mode of SHF.DF Currently, we support the cases that strictly fit fo

[gcc r15-1995] RISC-V: NO_WARNING preferred else value for RVV

https://gcc.gnu.org/g:c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd commit r15-1995-gc6f38e5e6d900b8ed6a4f5c126d3197946cad4dd Author: YunQiang Su Date: Thu Jul 11 20:43:54 2024 +0800 RISC-V: NO_WARNING preferred else value for RVV PR target/115840. In riscv_preferred_else_valu

[gcc r14-10411] RISC-V: NO_WARNING preferred else value for RVV

https://gcc.gnu.org/g:cff270707f107aff207f4afa73092a2d0731b032 commit r14-10411-gcff270707f107aff207f4afa73092a2d0731b032 Author: YunQiang Su Date: Thu Jul 11 20:43:54 2024 +0800 RISC-V: NO_WARNING preferred else value for RVV PR target/115840. In riscv_preferred_else_val

[gcc r14-9488] MIPS: Add -m(no-)strict-align option

https://gcc.gnu.org/g:acc38ff59976e972ba4b1e39f7653813a05de588 commit r14-9488-gacc38ff59976e972ba4b1e39f7653813a05de588 Author: YunQiang Su Date: Fri Mar 15 14:33:58 2024 +0800 MIPS: Add -m(no-)strict-align option We support options -m(no-)unaligned-access 2 years ago, while

[gcc r14-9496] Regenerate opt.urls

https://gcc.gnu.org/g:b5e1f0696110fbf5c73426ede70562edc6f54481 commit r14-9496-gb5e1f0696110fbf5c73426ede70562edc6f54481 Author: YunQiang Su Date: Fri Mar 15 21:22:40 2024 +0800 Regenerate opt.urls Fixes: acc38ff59976 ("MIPS: Add -m(no-)strict-align option") gcc/ChangeLog

[gcc r14-9661] MIPS: Predefine __mips_strict_alignment if STRICT_ALIGNMENT

https://gcc.gnu.org/g:bb819067b3037dbc847aef6c46b8dc6cd5b50962 commit r14-9661-gbb819067b3037dbc847aef6c46b8dc6cd5b50962 Author: YunQiang Su Date: Wed Mar 20 16:25:04 2024 +0800 MIPS: Predefine __mips_strict_alignment if STRICT_ALIGNMENT Arm32 predefines __ARM_FEATURE_UNALIGNED if

[gcc r15-43] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6

https://gcc.gnu.org/g:11c13111ac64a035d6c4ea6c118eff4ece7a9d9b commit r15-43-g11c13111ac64a035d6c4ea6c118eff4ece7a9d9b Author: Jie Mei Date: Sun Apr 28 16:57:31 2024 +0800 MIPS: Add MIN/MAX.fmt instructions support for MIPS R6 This patch adds the smin/smax RTL mode for the min

[gcc r15-910] MIPS/testsuite: Fix bseli.b fail in msa-builtins.c

https://gcc.gnu.org/g:9a92e5e56a7f2b19928b8cb7634f59d9c7b2b582 commit r15-910-g9a92e5e56a7f2b19928b8cb7634f59d9c7b2b582 Author: YunQiang Su Date: Tue May 28 23:44:49 2024 +0800 MIPS/testsuite: Fix bseli.b fail in msa-builtins.c commit 05daf617ea22e1d818295ed2d037456937e23530 A

[gcc r15-911] MIPS16: Mark $2/$3 as clobbered if GP is used

https://gcc.gnu.org/g:915440eed21de367cb41857afb5273aff5bcb737 commit r15-911-g915440eed21de367cb41857afb5273aff5bcb737 Author: YunQiang Su Date: Wed May 29 02:28:25 2024 +0800 MIPS16: Mark $2/$3 as clobbered if GP is used PR Target/84790. The gp init sequence li

[gcc r14-10260] MIPS16: Mark $2/$3 as clobbered if GP is used

https://gcc.gnu.org/g:201cfa725587d13867b4dc25955434ebe90aff7b commit r14-10260-g201cfa725587d13867b4dc25955434ebe90aff7b Author: YunQiang Su Date: Wed May 29 02:28:25 2024 +0800 MIPS16: Mark $2/$3 as clobbered if GP is used PR Target/84790. The gp init sequence li

[gcc r12-10480] MIPS16: Mark $2/$3 as clobbered if GP is used

https://gcc.gnu.org/g:e26f16424f6279662efb210bc87c77148e956fed commit r12-10480-ge26f16424f6279662efb210bc87c77148e956fed Author: YunQiang Su Date: Wed May 29 02:28:25 2024 +0800 MIPS16: Mark $2/$3 as clobbered if GP is used PR Target/84790. The gp init sequence li

[gcc r13-8809] MIPS16: Mark $2/$3 as clobbered if GP is used

https://gcc.gnu.org/g:3be8fa7b19d218ca5812d71801e3e83ee2260ea0 commit r13-8809-g3be8fa7b19d218ca5812d71801e3e83ee2260ea0 Author: YunQiang Su Date: Wed May 29 02:28:25 2024 +0800 MIPS16: Mark $2/$3 as clobbered if GP is used PR Target/84790. The gp init sequence li

[gcc r11-11457] MIPS16: Mark $2/$3 as clobbered if GP is used

https://gcc.gnu.org/g:1bc4a777b21ae36b116e1842b7c482340ec929ef commit r11-11457-g1bc4a777b21ae36b116e1842b7c482340ec929ef Author: YunQiang Su Date: Wed May 29 02:28:25 2024 +0800 MIPS16: Mark $2/$3 as clobbered if GP is used PR Target/84790. The gp init sequence li

[gcc r15-1051] MIPS: Need COSTS_N_INSNS in mips_insn_cost

https://gcc.gnu.org/g:edd90d6d298f006e2c2e6c710ab97cd5ad733cb5 commit r15-1051-gedd90d6d298f006e2c2e6c710ab97cd5ad733cb5 Author: YunQiang Su Date: Thu Jun 6 12:28:31 2024 +0800 MIPS: Need COSTS_N_INSNS in mips_insn_cost In mips_insn_cost, COSTS_N_INSNS is missing when we return th

[gcc r15-1127] MIPS/testsuite: add -mno-branch-likely to r10k-cache-barrier-13.c

https://gcc.gnu.org/g:8e2eb6039d183b7c571da9eb83b933021c5b29be commit r15-1127-g8e2eb6039d183b7c571da9eb83b933021c5b29be Author: YunQiang Su Date: Sat Jun 8 16:05:13 2024 +0800 MIPS/testsuite: add -mno-branch-likely to r10k-cache-barrier-13.c In mips.cc(mips_reorg_process_insns),

[gcc r15-1230] MIPS: Use signaling fcmp instructions for LT/LE/LTGT

https://gcc.gnu.org/g:e3e5fd0c24c9b82d824da27bf8455bb3654e8eff commit r15-1230-ge3e5fd0c24c9b82d824da27bf8455bb3654e8eff Author: YunQiang Su Date: Sat Jun 8 11:31:19 2024 +0800 MIPS: Use signaling fcmp instructions for LT/LE/LTGT LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/c

[gcc r15-1231] MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5

https://gcc.gnu.org/g:f10896c8e5fe34e51ea61aaa4d4aaedb4677ff13 commit r15-1231-gf10896c8e5fe34e51ea61aaa4d4aaedb4677ff13 Author: YunQiang Su Date: Mon Jun 10 14:31:12 2024 +0800 MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5 Currently, the default tune val

[gcc r15-1436] build: Fix missing variable quotes

https://gcc.gnu.org/g:c6a9ab8c920f297c4efd289182aef9fbc73f5906 commit r15-1436-gc6a9ab8c920f297c4efd289182aef9fbc73f5906 Author: Collin Funk Date: Thu Jun 13 17:53:55 2024 -0700 build: Fix missing variable quotes When dlopen and pthread_create are in libc the variable is set t

[gcc r15-1446] Build: Fix typo ac_cv_search_pthread_crate

https://gcc.gnu.org/g:8088374a868aacab4dff208ec3e3fde790a1d9a3 commit r15-1446-g8088374a868aacab4dff208ec3e3fde790a1d9a3 Author: YunQiang Su Date: Wed Jun 19 22:30:22 2024 +0800 Build: Fix typo ac_cv_search_pthread_crate The correct variable name is ac_cv_search_pthread_crea

[gcc r15-1458] Revert "Build: Fix typo ac_cv_search_pthread_crate"

https://gcc.gnu.org/g:a334189739e13f8de1f9af99f8d16970435cebc4 commit r15-1458-ga334189739e13f8de1f9af99f8d16970435cebc4 Author: YunQiang Su Date: Thu Jun 20 07:02:33 2024 +0800 Revert "Build: Fix typo ac_cv_search_pthread_crate" This reverts commit 8088374a868aacab4dff208ec3e3fde

[gcc r15-1459] Revert "build: Fix missing variable quotes"

https://gcc.gnu.org/g:6d6587bc37f2039225e4fba9acaf7b26e600e3d3 commit r15-1459-g6d6587bc37f2039225e4fba9acaf7b26e600e3d3 Author: YunQiang Su Date: Thu Jun 20 07:02:47 2024 +0800 Revert "build: Fix missing variable quotes" This reverts commit c6a9ab8c920f297c4efd289182aef9fbc73f590

[gcc r15-1466] build: Fix missing variable quotes and typo

https://gcc.gnu.org/g:bea447a2982f3094aa3423b5045cea929f4f4700 commit r15-1466-gbea447a2982f3094aa3423b5045cea929f4f4700 Author: Collin Funk Date: Wed Jun 19 16:36:50 2024 -0700 build: Fix missing variable quotes and typo When dlopen and pthread_create are in libc the variable is

[gcc r15-1505] MIPS: Set condmove cost to SET(REG, REG)

https://gcc.gnu.org/g:7b67ec4b50ae523a1e1be410644abb627daa9590 commit r15-1505-g7b67ec4b50ae523a1e1be410644abb627daa9590 Author: YunQiang Su Date: Tue Jun 18 17:03:51 2024 +0800 MIPS: Set condmove cost to SET(REG, REG) On most uarch, the cost condmove is same as other noraml integ

[gcc r15-1506] Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel

https://gcc.gnu.org/g:573f11ec34eeb6a6c3bd3d7619738f927236727b commit r15-1506-g573f11ec34eeb6a6c3bd3d7619738f927236727b Author: YunQiang Su Date: Thu Jun 20 10:37:39 2024 +0800 Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel We check gcc_cv_as_m

[gcc r14-10336] Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel

https://gcc.gnu.org/g:a16f47f5f34d08b13ee58ea362027c6a479eb82f commit r14-10336-ga16f47f5f34d08b13ee58ea362027c6a479eb82f Author: YunQiang Su Date: Thu Jun 20 10:37:39 2024 +0800 Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel We check gcc_cv_as_

[gcc r15-7468] config.gcc: Support mips*64*-linux-muslabi64 as ABI64 by default

https://gcc.gnu.org/g:0399e3e54a2c891116d6b43683c7fdce689304c5 commit r15-7468-g0399e3e54a2c891116d6b43683c7fdce689304c5 Author: YunQiang Su Date: Mon Sep 23 00:55:29 2024 +0800 config.gcc: Support mips*64*-linux-muslabi64 as ABI64 by default LLVM introduced this triple support.

[gcc r15-7467] MIPS: Add some floating point instructions support for MIPSr6

https://gcc.gnu.org/g:86b9abc829316f94d455a2309f212031af36ba68 commit r15-7467-g86b9abc829316f94d455a2309f212031af36ba68 Author: Jie Mei Date: Fri Sep 20 10:42:48 2024 +0800 MIPS: Add some floating point instructions support for MIPSr6 This patch adds some of the float point instr