[gcc(refs/users/meissner/heads/work176)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

https://gcc.gnu.org/g:9bb7924857212ebaed7d46832d148c50461412e6 commit 9bb7924857212ebaed7d46832d148c50461412e6 Author: Michael Meissner Date: Mon Aug 19 13:41:01 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full

[gcc(refs/users/meissner/heads/work176)] RFC2656-Support load/store vector with right length.

https://gcc.gnu.org/g:56a9db5160a34db170f68370c1f0848f2969742f commit 56a9db5160a34db170f68370c1f0848f2969742f Author: Michael Meissner Date: Mon Aug 19 13:42:46 2024 -0400 RFC2656-Support load/store vector with right length. This patch adds support for new instructions that may b

[gcc(refs/users/meissner/heads/work176)] RFC2686-Add paddis support.

https://gcc.gnu.org/g:0db29e6841be33457118d7888dde0f258c5c360b commit 0db29e6841be33457118d7888dde0f258c5c360b Author: Michael Meissner Date: Mon Aug 19 13:44:27 2024 -0400 RFC2686-Add paddis support. 2024-08-19 Michael Meissner gcc/ * config/rs6000/co

[gcc(refs/users/meissner/heads/work176)] RFC2655-Add saturating subtract built-ins.

https://gcc.gnu.org/g:251349263ff84a4c5c5b6a712e8c106402405101 commit 251349263ff84a4c5c5b6a712e8c106402405101 Author: Michael Meissner Date: Mon Aug 19 13:43:33 2024 -0400 RFC2655-Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in functi

[gcc(refs/users/meissner/heads/work176)] RFC2677-Add xvrlw support.

https://gcc.gnu.org/g:11f9bbc963f9096f58f1e57fd3a61476333df2c3 commit 11f9bbc963f9096f58f1e57fd3a61476333df2c3 Author: Michael Meissner Date: Mon Aug 19 13:45:28 2024 -0400 RFC2677-Add xvrlw support. 2024-08-19 Michael Meissner gcc/ * config/rs6000/alt

[gcc(refs/users/meissner/heads/work176)] Revert changes

https://gcc.gnu.org/g:5f249111a45818b00063a4674c46041805269bf5 commit 5f249111a45818b00063a4674c46041805269bf5 Author: Michael Meissner Date: Mon Aug 19 13:51:17 2024 -0400 Revert changes Diff: --- gcc/config/rs6000/altivec.md | 14 - gcc/config/rs6000/constraints.

[gcc(refs/users/meissner/heads/work176-dmf)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:aa3552fcdfe7f9c6103229a5c1a194d4ed625474 commit aa3552fcdfe7f9c6103229a5c1a194d4ed625474 Author: Michael Meissner Date: Mon Aug 19 13:51:56 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC di

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-Add wD constraint.

https://gcc.gnu.org/g:631c2bebb7aad48deba16a5e0d4f02c08f8e56bc commit 631c2bebb7aad48deba16a5e0d4f02c08f8e56bc Author: Michael Meissner Date: Mon Aug 19 13:52:23 2024 -0400 RFC2653-Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:621467db4c48a51fa4b26b560f31e32cb5882525 commit 621467db4c48a51fa4b26b560f31e32cb5882525 Author: Michael Meissner Date: Mon Aug 19 13:53:00 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work176-dmf)] xRFC2653-Add dense math test for new instruction names.

https://gcc.gnu.org/g:ce4973acae8715305b2e8e6bec1bd73eccd1a971 commit ce4973acae8715305b2e8e6bec1bd73eccd1a971 Author: Michael Meissner Date: Mon Aug 19 13:54:59 2024 -0400 xRFC2653-Add dense math test for new instruction names. 2024-08-19 Michael Meissner gcc/testsui

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

https://gcc.gnu.org/g:d5e1fc8ad02bfd5b133b328cbb8d8e51bd247f6b commit d5e1fc8ad02bfd5b133b328cbb8d8e51bd247f6b Author: Michael Meissner Date: Mon Aug 19 13:54:13 2024 -0400 RFC2653-PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruc

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers

https://gcc.gnu.org/g:b9841440d225bf35f9903212cef11b6679c963cc commit b9841440d225bf35f9903212cef11b6679c963cc Author: Michael Meissner Date: Mon Aug 19 13:57:32 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers This patch is a prelimianry patch to add the full 1

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2656-Support load/store vector with right length

https://gcc.gnu.org/g:5a59d920eb3dbcad808d1ed496cb279de9adfa2f commit 5a59d920eb3dbcad808d1ed496cb279de9adfa2f Author: Michael Meissner Date: Mon Aug 19 13:59:03 2024 -0400 RFC2656-Support load/store vector with right length This patch adds support for new instructions that may be

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2655-Add saturating subtract built-ins

https://gcc.gnu.org/g:5777392dbf05d4fe6ad82405b4cf81055b8bc12f commit 5777392dbf05d4fe6ad82405b4cf81055b8bc12f Author: Michael Meissner Date: Mon Aug 19 13:59:27 2024 -0400 RFC2655-Add saturating subtract built-ins This patch adds support for a saturating subtract built-in functio

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2677-Add xvrlw support

https://gcc.gnu.org/g:bb360cc7fdb5b20190372b0628b03e25390c0f96 commit bb360cc7fdb5b20190372b0628b03e25390c0f96 Author: Michael Meissner Date: Mon Aug 19 14:00:19 2024 -0400 RFC2677-Add xvrlw support 2024-08-19 Michael Meissner gcc/ * config/rs6000/alti

[gcc(refs/users/meissner/heads/work176-dmf)] RFC2686-Add paddis support

https://gcc.gnu.org/g:c827e64576d202661c6224ff540659ced605297e commit c827e64576d202661c6224ff540659ced605297e Author: Michael Meissner Date: Mon Aug 19 13:59:50 2024 -0400 RFC2686-Add paddis support 2024-08-19 Michael Meissner gcc/ * config/rs6000/con

[gcc/meissner/heads/work176] Merge commit 'refs/users/meissner/heads/work176' of git+ssh

The branch 'meissner/heads/work176' was updated to point to: 248fc70e14e... Merge commit 'refs/users/meissner/heads/work176' of git+ssh It previously pointed to: 5f249111a45... Revert changes Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --

[gcc(refs/users/meissner/heads/work176-bugs)] Add better support for shifting vectors with 64-bit elements

https://gcc.gnu.org/g:b79d939912a9826b29603037848503ca56ed2ea8 commit b79d939912a9826b29603037848503ca56ed2ea8 Author: Michael Meissner Date: Mon Aug 19 14:09:32 2024 -0400 Add better support for shifting vectors with 64-bit elements This patch fixes PR target/89213 to allow bette

[gcc(refs/users/meissner/heads/work176-bugs)] Optimize splat of a V2DF/V2DI extract with constant element

https://gcc.gnu.org/g:d4e863527f6453d567400381cb3df53fa3c03f22 commit d4e863527f6453d567400381cb3df53fa3c03f22 Author: Michael Meissner Date: Mon Aug 19 14:10:44 2024 -0400 Optimize splat of a V2DF/V2DI extract with constant element We had optimizations for splat of a vector extra

[gcc(refs/users/meissner/heads/work176-bugs)] Update ChagneLog.bugs

https://gcc.gnu.org/g:74a68d9476981f47d53073131b05cfdd28c28a64 commit 74a68d9476981f47d53073131b05cfdd28c28a64 Author: Michael Meissner Date: Mon Aug 19 14:12:25 2024 -0400 Update ChagneLog.bugs Diff: --- gcc/ChangeLog.bugs | 94 +- 1 f

[gcc(refs/users/meissner/heads/work176-tar)] Remove SPR alternatives for move insns.

https://gcc.gnu.org/g:1eaca9796aaad6e085323f03fd523d087ee659db commit 1eaca9796aaad6e085323f03fd523d087ee659db Author: Michael Meissner Date: Mon Aug 19 14:17:13 2024 -0400 Remove SPR alternatives for move insns. 2024-08-19 Michael Meissner * config/rs6000/rs60

[gcc(refs/users/meissner/heads/work176-tar)] Add support for the TAR register.

https://gcc.gnu.org/g:987957c82206af4bf69175c7438fe9d3de5a3cc0 commit 987957c82206af4bf69175c7438fe9d3de5a3cc0 Author: Michael Meissner Date: Mon Aug 19 14:16:09 2024 -0400 Add support for the TAR register. 2024-08-19 Michael Meissner gcc/ * config/rs6

[gcc(refs/users/meissner/heads/work176-tar)] Update ChangeLog.*

https://gcc.gnu.org/g:15ff7216870b8c3689c848ab8d42d67598c6337d commit 15ff7216870b8c3689c848ab8d42d67598c6337d Author: Michael Meissner Date: Mon Aug 19 14:19:19 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 83 ++- 1 file

[gcc(refs/users/meissner/heads/work176-vpair)] Add support for vector pair unary and binary operations.

https://gcc.gnu.org/g:843b0025117e9a3c3a3bb57b5dc05c149b94575e commit 843b0025117e9a3c3a3bb57b5dc05c149b94575e Author: Michael Meissner Date: Mon Aug 19 14:21:35 2024 -0400 Add support for vector pair unary and binary operations. 2024-08-19 Michael Meissner gcc/

[gcc(refs/users/meissner/heads/work176-vpair)] Add support for vector pair fma operations.

https://gcc.gnu.org/g:64af04ceb49a577e8c263db5e1ac31fb0b8c18b7 commit 64af04ceb49a577e8c263db5e1ac31fb0b8c18b7 Author: Michael Meissner Date: Mon Aug 19 14:22:38 2024 -0400 Add support for vector pair fma operations. 2024-08-19 Michael Meissner gcc/ *

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair init and splat.

https://gcc.gnu.org/g:19677035f937f71409fdf6cc52999ab1e7e0c25f commit 19677035f937f71409fdf6cc52999ab1e7e0c25f Author: Michael Meissner Date: Mon Aug 19 14:23:29 2024 -0400 Add vector pair init and splat. 2024-08-19 Michael Meissner gcc/ * config/rs600

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair optimizations.

https://gcc.gnu.org/g:a2ecfd5d0a177a8c3cb187fafdb807e98a4b58a8 commit a2ecfd5d0a177a8c3cb187fafdb807e98a4b58a8 Author: Michael Meissner Date: Mon Aug 19 14:24:38 2024 -0400 Add vector pair optimizations. 2024-08-19 Michael Meissner gcc/ * config/rs6000

[gcc(refs/users/meissner/heads/work176-vpair)] Update ChangeLog.*

https://gcc.gnu.org/g:83e3e4b42b551cbf6e544a2d1fb4bf63f8d95d0c commit 83e3e4b42b551cbf6e544a2d1fb4bf63f8d95d0c Author: Michael Meissner Date: Mon Aug 19 14:27:08 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.vpair | 127 +++- 1 file

[gcc(refs/users/meissner/heads/work176-libs)] Do not build IEEE 128-bit libgfortran support if VSX is not available.

https://gcc.gnu.org/g:5a17794170f2ae8a3e81f3d4c7e62e5f6abbeeaa commit 5a17794170f2ae8a3e81f3d4c7e62e5f6abbeeaa Author: Michael Meissner Date: Mon Aug 19 14:32:54 2024 -0400 Do not build IEEE 128-bit libgfortran support if VSX is not available. If you build a little endian compiler

[gcc(refs/users/meissner/heads/work176-libs)] Do not add -mvsx when building libgcc float128 support.

https://gcc.gnu.org/g:18edb686452a6217166adc336a42eec1619e5cf0 commit 18edb686452a6217166adc336a42eec1619e5cf0 Author: Michael Meissner Date: Mon Aug 19 14:38:05 2024 -0400 Do not add -mvsx when building libgcc float128 support. Currently, we add -mvsx when building the float128 s

[gcc(refs/users/meissner/heads/work176-libs)] Do not add -mvsx when testing the float128 support.

https://gcc.gnu.org/g:a10b0df9be3c909e5adc0d13fe2f4c89e465a8e6 commit a10b0df9be3c909e5adc0d13fe2f4c89e465a8e6 Author: Michael Meissner Date: Mon Aug 19 14:42:27 2024 -0400 Do not add -mvsx when testing the float128 support. Currently, we add -mvsx when building the float128 suppo

[gcc(refs/users/meissner/heads/work176-libs)] Update ChangeLog.*

https://gcc.gnu.org/g:6a2d250899a3691fe55dddf3cf671d49de2d88bd commit 6a2d250899a3691fe55dddf3cf671d49de2d88bd Author: Michael Meissner Date: Mon Aug 19 14:44:50 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.libs | 210 - 1 file

[gcc(refs/users/meissner/heads/work176-vpair)] Revert changes

https://gcc.gnu.org/g:0b7aaee1ce5fa2f2f5f2239450eb128dd6d2b2e5 commit 0b7aaee1ce5fa2f2f5f2239450eb128dd6d2b2e5 Author: Michael Meissner Date: Tue Aug 20 12:46:42 2024 -0400 Revert changes Diff: --- gcc/config/rs6000/rs6000-builtins.def | 10 - gcc/config/rs6000/vector-pair.m

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair init and splat.

https://gcc.gnu.org/g:901c7f0836effdb24831f04ec4a5884f33fd76ba commit 901c7f0836effdb24831f04ec4a5884f33fd76ba Author: Michael Meissner Date: Tue Aug 20 12:52:34 2024 -0400 Add vector pair init and splat. 2024-08-20 Michael Meissner gcc/ * config/rs600

[gcc(refs/users/meissner/heads/work176-vpair)] Revert changes

https://gcc.gnu.org/g:528b36dade23b80f8021a0701d238ad971ff033c commit 528b36dade23b80f8021a0701d238ad971ff033c Author: Michael Meissner Date: Tue Aug 20 12:54:57 2024 -0400 Revert changes Diff: --- gcc/config/rs6000/rs6000-builtins.def | 10 gcc/config/rs6000/vector-pair.md |

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair init and splat.

https://gcc.gnu.org/g:7d99722e8df0aade817f19f657dfd7e739108ab6 commit 7d99722e8df0aade817f19f657dfd7e739108ab6 Author: Michael Meissner Date: Tue Aug 20 12:57:02 2024 -0400 Add vector pair init and splat. 2024-08-20 Michael Meissner gcc/ * config/rs600

[gcc(refs/users/meissner/heads/work176-vpair)] Add vector pair optimizations.

https://gcc.gnu.org/g:7e2134dab92d9032a849772f09b2b7935a8f4e62 commit 7e2134dab92d9032a849772f09b2b7935a8f4e62 Author: Michael Meissner Date: Tue Aug 20 12:57:41 2024 -0400 Add vector pair optimizations. 2024-08-20 Michael Meissner gcc/ * config/rs6000

[gcc] Created branch 'meissner/heads/work177' in namespace 'refs/users'

The branch 'meissner/heads/work177' was created in namespace 'refs/users' pointing to: f9642ffe7814... Explicitly document that the "counted_by" attribute is only

[gcc/meissner/heads/work177] (2 commits) split-path: Improve ifcvt heurstic for split path [PR112402

The branch 'meissner/heads/work177' was updated to point to: b2b20b277988... split-path: Improve ifcvt heurstic for split path [PR112402 It previously pointed to: f9642ffe7814... Explicitly document that the "counted_by" attribute is only Diff: Summary of changes (added commits): ---

[gcc(refs/users/meissner/heads/work177)] Add ChangeLog.meissner and REVISION.

https://gcc.gnu.org/g:53168176652d415fb8c77ff7f0fc3c4b8ef4c066 commit 53168176652d415fb8c77ff7f0fc3c4b8ef4c066 Author: Michael Meissner Date: Tue Sep 3 19:39:29 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-09-03 Michael Meissner gcc/ * REVISION

[gcc] Created branch 'meissner/heads/work177-dmf' in namespace 'refs/users'

The branch 'meissner/heads/work177-dmf' was created in namespace 'refs/users' pointing to: 53168176652d... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work177-dmf)] Add ChangeLog.dmf and update REVISION.

https://gcc.gnu.org/g:b0d36040031e957f032d34c560c9050d0362c9a3 commit b0d36040031e957f032d34c560c9050d0362c9a3 Author: Michael Meissner Date: Tue Sep 3 19:40:35 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-09-03 Michael Meissner gcc/ * Change

[gcc] Created branch 'meissner/heads/work177-vpair' in namespace 'refs/users'

The branch 'meissner/heads/work177-vpair' was created in namespace 'refs/users' pointing to: 53168176652d... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work177-vpair)] Add ChangeLog.vpair and update REVISION.

https://gcc.gnu.org/g:a1297ab8acc18f2c4a5da6eb0ea59616e4a31532 commit a1297ab8acc18f2c4a5da6eb0ea59616e4a31532 Author: Michael Meissner Date: Tue Sep 3 19:41:27 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chan

[gcc] Created branch 'meissner/heads/work177-tar' in namespace 'refs/users'

The branch 'meissner/heads/work177-tar' was created in namespace 'refs/users' pointing to: 53168176652d... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work177-tar)] Add ChangeLog.tar and update REVISION.

https://gcc.gnu.org/g:e3af2c7a011e462a0934e9f022c96227629d3cf1 commit e3af2c7a011e462a0934e9f022c96227629d3cf1 Author: Michael Meissner Date: Tue Sep 3 19:42:20 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-09-03 Michael Meissner gcc/ * Change

[gcc] Created branch 'meissner/heads/work177-bugs' in namespace 'refs/users'

The branch 'meissner/heads/work177-bugs' was created in namespace 'refs/users' pointing to: 53168176652d... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work177-bugs)] Add ChangeLog.bugs and update REVISION.

https://gcc.gnu.org/g:e9eff3979fbb53d0959cac044f9918f4840a3a04 commit e9eff3979fbb53d0959cac044f9918f4840a3a04 Author: Michael Meissner Date: Tue Sep 3 19:43:16 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chang

[gcc] Created branch 'meissner/heads/work177-libs' in namespace 'refs/users'

The branch 'meissner/heads/work177-libs' was created in namespace 'refs/users' pointing to: 53168176652d... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work177-libs)] Add ChangeLog.libs and update REVISION.

https://gcc.gnu.org/g:752eeaaf40595de40bdd75cf16ba325c0403 commit 752eeaaf40595de40bdd75cf16ba325c0403 Author: Michael Meissner Date: Tue Sep 3 19:44:40 2024 -0400 Add ChangeLog.libs and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chang

[gcc] Created branch 'meissner/heads/work177-test' in namespace 'refs/users'

The branch 'meissner/heads/work177-test' was created in namespace 'refs/users' pointing to: 53168176652d... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work177-test)] Add ChangeLog.test and update REVISION.

https://gcc.gnu.org/g:9977091c89facf09ce829bfd41a3437c28e328cb commit 9977091c89facf09ce829bfd41a3437c28e328cb Author: Michael Meissner Date: Tue Sep 3 19:45:32 2024 -0400 Add ChangeLog.test and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chang

[gcc] Created branch 'meissner/heads/work177-orig' in namespace 'refs/users'

The branch 'meissner/heads/work177-orig' was created in namespace 'refs/users' pointing to: b2b20b277988... split-path: Improve ifcvt heurstic for split path [PR112402

[gcc(refs/users/meissner/heads/work177-orig)] Add REVISION.

https://gcc.gnu.org/g:f43015cda20994222e0660dace5f4196c0abd3ab commit f43015cda20994222e0660dace5f4196c0abd3ab Author: Michael Meissner Date: Tue Sep 3 19:46:34 2024 -0400 Add REVISION. 2024-09-03 Michael Meissner gcc/ * REVISION: New file for branch.

[gcc(refs/users/meissner/heads/work177)] Add rs6000 architecture masks.

https://gcc.gnu.org/g:505f1a5cb7932ff0d22d0316481be278a986f257 commit 505f1a5cb7932ff0d22d0316481be278a986f257 Author: Michael Meissner Date: Tue Sep 3 19:53:25 2024 -0400 Add rs6000 architecture masks. This patch begins the journey to move architecture bits that are not user ISA

[gcc(refs/users/meissner/heads/work177)] Use architecture flags for defining _ARCH_PWR macros.

https://gcc.gnu.org/g:559e865070211ec4a193a5565f1b23edca37f438 commit 559e865070211ec4a193a5565f1b23edca37f438 Author: Michael Meissner Date: Tue Sep 3 19:53:55 2024 -0400 Use architecture flags for defining _ARCH_PWR macros. For the newer architectures, this patch changes GCC to

[gcc(refs/users/meissner/heads/work177)] Do not allow -mvsx to boost processor to power7.

https://gcc.gnu.org/g:75c6f74df51de2751c3da377b15da0d1c821d244 commit 75c6f74df51de2751c3da377b15da0d1c821d244 Author: Michael Meissner Date: Tue Sep 3 19:55:32 2024 -0400 Do not allow -mvsx to boost processor to power7. This patch restructures the code so that -mvsx for example w

[gcc(refs/users/meissner/heads/work177)] Change TARGET_POPCNTB to TARGET_POWER5

https://gcc.gnu.org/g:9e092b36f68d63b236f8693e0d9f445a81ab370b commit 9e092b36f68d63b236f8693e0d9f445a81ab370b Author: Michael Meissner Date: Tue Sep 3 19:57:43 2024 -0400 Change TARGET_POPCNTB to TARGET_POWER5 As part of the architecture flags patches, this patch changes the use

[gcc(refs/users/meissner/heads/work177)] Change TARGET_FPRND to TARGET_POWER5X

https://gcc.gnu.org/g:c3fd033dca28a0617f0ce7e64f4a9b90c15f133e commit c3fd033dca28a0617f0ce7e64f4a9b90c15f133e Author: Michael Meissner Date: Tue Sep 3 19:58:59 2024 -0400 Change TARGET_FPRND to TARGET_POWER5X As part of the architecture flags patches, this patch changes the use o

[gcc(refs/users/meissner/heads/work177)] Change TARGET_CMPB to TARGET_POWER6

https://gcc.gnu.org/g:924e0f641636c09990f2d5094f9585ae5818bf16 commit 924e0f641636c09990f2d5094f9585ae5818bf16 Author: Michael Meissner Date: Tue Sep 3 21:53:25 2024 -0400 Change TARGET_CMPB to TARGET_POWER6 As part of the architecture flags patches, this patch changes the use of

[gcc(refs/users/meissner/heads/work177)] Change TARGET_POPCNTD to TARGET_POWER7

https://gcc.gnu.org/g:59231f09ecfa595b602bcb96ce8d9ea73b57e934 commit 59231f09ecfa595b602bcb96ce8d9ea73b57e934 Author: Michael Meissner Date: Tue Sep 3 21:54:04 2024 -0400 Change TARGET_POPCNTD to TARGET_POWER7 As part of the architecture flags patches, this patch changes the use

[gcc(refs/users/meissner/heads/work177)] Change TARGET_MODULO to TARGET_POWER9

https://gcc.gnu.org/g:33a2cf2f215c286088c33bc49f4426e1c354be5d commit 33a2cf2f215c286088c33bc49f4426e1c354be5d Author: Michael Meissner Date: Tue Sep 3 21:55:50 2024 -0400 Change TARGET_MODULO to TARGET_POWER9 As part of the architecture flags patches, this patch changes the use o

[gcc(refs/users/meissner/heads/work177)] Update tests to work with architecture flags changes.

https://gcc.gnu.org/g:62ff64e4d799235646100d85b4428267fa3844c3 commit 62ff64e4d799235646100d85b4428267fa3844c3 Author: Michael Meissner Date: Tue Sep 3 21:57:11 2024 -0400 Update tests to work with architecture flags changes. Two tests used -mvsx to raise the processor level to at

[gcc(refs/users/meissner/heads/work177)] Add support for -mcpu=future

https://gcc.gnu.org/g:bb83c503c32a453704994cb802985119d3199ff0 commit bb83c503c32a453704994cb802985119d3199ff0 Author: Michael Meissner Date: Tue Sep 3 21:59:12 2024 -0400 Add support for -mcpu=future This patch adds the support that can be used in developing GCC support for f

[gcc(refs/users/meissner/heads/work177)] Add -mcpu=future tuning support.

https://gcc.gnu.org/g:6671caf766c5022dc409d9be4a5dc81526cbf1ed commit 6671caf766c5022dc409d9be4a5dc81526cbf1ed Author: Michael Meissner Date: Tue Sep 3 22:00:24 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power

[gcc(refs/users/meissner/heads/work177)] Update ChangeLog.*

https://gcc.gnu.org/g:c6a092f33bc8540eb5fdf8fd60f7ea84b5e3a934 commit c6a092f33bc8540eb5fdf8fd60f7ea84b5e3a934 Author: Michael Meissner Date: Tue Sep 3 22:04:07 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 449 - 1 file

[gcc/meissner/heads/work177-bugs] (14 commits) Merge commit 'refs/users/meissner/heads/work177-bugs' of gi

The branch 'meissner/heads/work177-bugs' was updated to point to: 3b714bd343c2... Merge commit 'refs/users/meissner/heads/work177-bugs' of gi It previously pointed to: e9eff3979fbb... Add ChangeLog.bugs and update REVISION. Diff: Summary of changes (added commits): --

[gcc(refs/users/meissner/heads/work177-bugs)] Add ChangeLog.bugs and update REVISION.

https://gcc.gnu.org/g:47ea6bac4fcd2fd42929756717369c8838096435 commit 47ea6bac4fcd2fd42929756717369c8838096435 Author: Michael Meissner Date: Tue Sep 3 19:43:16 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chang

[gcc(refs/users/meissner/heads/work177-bugs)] Merge commit 'refs/users/meissner/heads/work177-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

https://gcc.gnu.org/g:3b714bd343c212924f0371e2eedc3530c85ab5c0 commit 3b714bd343c212924f0371e2eedc3530c85ab5c0 Merge: 47ea6bac4fcd e9eff3979fbb Author: Michael Meissner Date: Tue Sep 3 22:04:52 2024 -0400 Merge commit 'refs/users/meissner/heads/work177-bugs' of git+ssh://gcc.gnu.org/git/g

[gcc/meissner/heads/work177-dmf] (14 commits) Merge commit 'refs/users/meissner/heads/work177-dmf' of git

The branch 'meissner/heads/work177-dmf' was updated to point to: e26fe0258375... Merge commit 'refs/users/meissner/heads/work177-dmf' of git It previously pointed to: b0d36040031e... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits):

[gcc(refs/users/meissner/heads/work177-dmf)] Add ChangeLog.dmf and update REVISION.

https://gcc.gnu.org/g:ac3382f8526f4d0ffeeca8edc11149832c52d815 commit ac3382f8526f4d0ffeeca8edc11149832c52d815 Author: Michael Meissner Date: Tue Sep 3 19:40:35 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-09-03 Michael Meissner gcc/ * Change

[gcc(refs/users/meissner/heads/work177-dmf)] Merge commit 'refs/users/meissner/heads/work177-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17

https://gcc.gnu.org/g:e26fe0258375de420238bf66f9ddf2f2cfea57ce commit e26fe0258375de420238bf66f9ddf2f2cfea57ce Merge: ac3382f8526f b0d36040031e Author: Michael Meissner Date: Tue Sep 3 22:06:34 2024 -0400 Merge commit 'refs/users/meissner/heads/work177-dmf' of git+ssh://gcc.gnu.org/git/gc

[gcc/meissner/heads/work177-libs] (14 commits) Merge commit 'refs/users/meissner/heads/work177-libs' of gi

The branch 'meissner/heads/work177-libs' was updated to point to: fd9c9e45d5d5... Merge commit 'refs/users/meissner/heads/work177-libs' of gi It previously pointed to: 752eeaaf... Add ChangeLog.libs and update REVISION. Diff: Summary of changes (added commits): --

[gcc(refs/users/meissner/heads/work177-libs)] Add ChangeLog.libs and update REVISION.

https://gcc.gnu.org/g:cd87d132d47469a00a6ffa5863ce57226541c74b commit cd87d132d47469a00a6ffa5863ce57226541c74b Author: Michael Meissner Date: Tue Sep 3 19:44:40 2024 -0400 Add ChangeLog.libs and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chang

[gcc(refs/users/meissner/heads/work177-libs)] Merge commit 'refs/users/meissner/heads/work177-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

https://gcc.gnu.org/g:fd9c9e45d5d5cef02e3f3ddc7669ae8028d0acd4 commit fd9c9e45d5d5cef02e3f3ddc7669ae8028d0acd4 Merge: cd87d132d474 752eeaaf Author: Michael Meissner Date: Tue Sep 3 22:08:20 2024 -0400 Merge commit 'refs/users/meissner/heads/work177-libs' of git+ssh://gcc.gnu.org/git/g

[gcc/meissner/heads/work177-tar] (14 commits) Merge commit 'refs/users/meissner/heads/work177-tar' of git

The branch 'meissner/heads/work177-tar' was updated to point to: e75a605eca9d... Merge commit 'refs/users/meissner/heads/work177-tar' of git It previously pointed to: e3af2c7a011e... Add ChangeLog.tar and update REVISION. Diff: Summary of changes (added commits):

[gcc(refs/users/meissner/heads/work177-tar)] Add ChangeLog.tar and update REVISION.

https://gcc.gnu.org/g:6a6c43f8cfe5e3a926be48f9739592522de9457b commit 6a6c43f8cfe5e3a926be48f9739592522de9457b Author: Michael Meissner Date: Tue Sep 3 19:42:20 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-09-03 Michael Meissner gcc/ * Change

[gcc(refs/users/meissner/heads/work177-tar)] Merge commit 'refs/users/meissner/heads/work177-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17

https://gcc.gnu.org/g:e75a605eca9d86b15f0dc7f58e392012cf86b79a commit e75a605eca9d86b15f0dc7f58e392012cf86b79a Merge: 6a6c43f8cfe5 e3af2c7a011e Author: Michael Meissner Date: Tue Sep 3 22:10:04 2024 -0400 Merge commit 'refs/users/meissner/heads/work177-tar' of git+ssh://gcc.gnu.org/git/gc

[gcc/meissner/heads/work177-test] (14 commits) Merge commit 'refs/users/meissner/heads/work177-test' of gi

The branch 'meissner/heads/work177-test' was updated to point to: 35b6e0965ca6... Merge commit 'refs/users/meissner/heads/work177-test' of gi It previously pointed to: 9977091c89fa... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --

[gcc(refs/users/meissner/heads/work177-test)] Add ChangeLog.test and update REVISION.

https://gcc.gnu.org/g:d8fca012866fa40cc793677326e4f3ca64a56f04 commit d8fca012866fa40cc793677326e4f3ca64a56f04 Author: Michael Meissner Date: Tue Sep 3 19:45:32 2024 -0400 Add ChangeLog.test and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chang

[gcc(refs/users/meissner/heads/work177-test)] Merge commit 'refs/users/meissner/heads/work177-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

https://gcc.gnu.org/g:35b6e0965ca6db155b4281a59b70c7fabde99ead commit 35b6e0965ca6db155b4281a59b70c7fabde99ead Merge: d8fca012866f 9977091c89fa Author: Michael Meissner Date: Tue Sep 3 22:11:56 2024 -0400 Merge commit 'refs/users/meissner/heads/work177-test' of git+ssh://gcc.gnu.org/git/g

[gcc/meissner/heads/work177-vpair] (14 commits) Merge commit 'refs/users/meissner/heads/work177-vpair' of g

The branch 'meissner/heads/work177-vpair' was updated to point to: 4e3f839435e3... Merge commit 'refs/users/meissner/heads/work177-vpair' of g It previously pointed to: a1297ab8acc1... Add ChangeLog.vpair and update REVISION. Diff: Summary of changes (added commits):

[gcc(refs/users/meissner/heads/work177-vpair)] Add ChangeLog.vpair and update REVISION.

https://gcc.gnu.org/g:2ded4c8845ab4597540d3b4740fb9a8bad156c9e commit 2ded4c8845ab4597540d3b4740fb9a8bad156c9e Author: Michael Meissner Date: Tue Sep 3 19:41:27 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-09-03 Michael Meissner gcc/ * Chan

[gcc(refs/users/meissner/heads/work177-vpair)] Merge commit 'refs/users/meissner/heads/work177-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

https://gcc.gnu.org/g:4e3f839435e31f04e7c1c7334b81352645da4ec8 commit 4e3f839435e31f04e7c1c7334b81352645da4ec8 Merge: 2ded4c8845ab a1297ab8acc1 Author: Michael Meissner Date: Tue Sep 3 22:14:19 2024 -0400 Merge commit 'refs/users/meissner/heads/work177-vpair' of git+ssh://gcc.gnu.org/git/

[gcc(refs/users/meissner/heads/work177-bugs)] Add better support for shifting vectors with 64-bit elements

https://gcc.gnu.org/g:2e236aa017bc9c3d1a4fc065c7051c3a45e2f71c commit 2e236aa017bc9c3d1a4fc065c7051c3a45e2f71c Author: Michael Meissner Date: Tue Sep 3 22:17:54 2024 -0400 Add better support for shifting vectors with 64-bit elements This patch fixes PR target/89213 to allow better

[gcc(refs/users/meissner/heads/work177-bugs)] Optimize splat of a V2DF/V2DI extract with constant element

https://gcc.gnu.org/g:8dc69fbc17ba58eac4d758f412ec2014c41b9bbc commit 8dc69fbc17ba58eac4d758f412ec2014c41b9bbc Author: Michael Meissner Date: Tue Sep 3 22:18:49 2024 -0400 Optimize splat of a V2DF/V2DI extract with constant element We had optimizations for splat of a vector extrac

[gcc(refs/users/meissner/heads/work177-bugs)] Update ChangeLog.*

https://gcc.gnu.org/g:4257b13aa62b5307dceaa686ac15088f367fa608 commit 4257b13aa62b5307dceaa686ac15088f367fa608 Author: Michael Meissner Date: Tue Sep 3 22:20:30 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 94 +- 1 file

[gcc(refs/users/meissner/heads/work177-tar)] Add support for the TAR register.

https://gcc.gnu.org/g:5c2283f478e908718024e5b3b53dc8c4db3a8fe9 commit 5c2283f478e908718024e5b3b53dc8c4db3a8fe9 Author: Michael Meissner Date: Wed Sep 4 11:36:25 2024 -0400 Add support for the TAR register. 2024-09-04 Michael Meissner gcc/ * config/rs60

[gcc(refs/users/meissner/heads/work177-tar)] Remove SPR alternatives for move insns.

https://gcc.gnu.org/g:a719aa37a9ddcea20ef9da9c2097ee48465da758 commit a719aa37a9ddcea20ef9da9c2097ee48465da758 Author: Michael Meissner Date: Wed Sep 4 11:38:07 2024 -0400 Remove SPR alternatives for move insns. 2024-09-04 Michael Meissner * config/rs6000/rs600

[gcc(refs/users/meissner/heads/work177-tar)] Update ChangeLog.*

https://gcc.gnu.org/g:ca08fa1266ef9d4678a9ee5b094a06c4f753bda9 commit ca08fa1266ef9d4678a9ee5b094a06c4f753bda9 Author: Michael Meissner Date: Wed Sep 4 11:40:35 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 83 ++- 1 file

[gcc(refs/users/meissner/heads/work177-libs)] Do not build IEEE 128-bit libgfortran support if VSX is not available.

https://gcc.gnu.org/g:b766e0eb3bd24ca74f54cddc957db0b3ba84187e commit b766e0eb3bd24ca74f54cddc957db0b3ba84187e Author: Michael Meissner Date: Wed Sep 4 11:29:29 2024 -0400 Do not build IEEE 128-bit libgfortran support if VSX is not available. If you build a little endian compiler

[gcc(refs/users/meissner/heads/work177-libs)] Do not build IEEE 128-bit libstdc++ support if VSX is not available.

https://gcc.gnu.org/g:61b479aadbe46f39409f8f3996e3192adf60b66d commit 61b479aadbe46f39409f8f3996e3192adf60b66d Author: Michael Meissner Date: Wed Sep 4 11:30:57 2024 -0400 Do not build IEEE 128-bit libstdc++ support if VSX is not available. If you build a little endian compiler an

[gcc(refs/users/meissner/heads/work177-libs)] Do not build IEEE 128-bit libstdc++ support if VSX is not available.

https://gcc.gnu.org/g:3696abc890a0e9acbd4e93c688d0e238c011ee76 commit 3696abc890a0e9acbd4e93c688d0e238c011ee76 Author: Michael Meissner Date: Wed Sep 4 11:31:56 2024 -0400 Do not build IEEE 128-bit libstdc++ support if VSX is not available. If you build a little endian compiler an

[gcc(refs/users/meissner/heads/work177-libs)] Do not add -mvsx when testing the float128 support.

https://gcc.gnu.org/g:db95aceee0bf62edcb1fa34e5c61279fa09ed158 commit db95aceee0bf62edcb1fa34e5c61279fa09ed158 Author: Michael Meissner Date: Wed Sep 4 11:33:00 2024 -0400 Do not add -mvsx when testing the float128 support. Currently, we add -mvsx when building the float128 suppor

[gcc(refs/users/meissner/heads/work177-libs)] Update ChangeLog.*

https://gcc.gnu.org/g:fde55641b666e342f2de9889b930fb8bbec4d691 commit fde55641b666e342f2de9889b930fb8bbec4d691 Author: Michael Meissner Date: Wed Sep 4 11:44:02 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.libs | 210 - 1 file

[gcc(refs/users/meissner/heads/work177-dmf)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:9713c43be031a884541dc63e6c6efae74f7da3ce commit 9713c43be031a884541dc63e6c6efae74f7da3ce Author: Michael Meissner Date: Wed Sep 4 11:48:12 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC did

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-Add wD constraint.

https://gcc.gnu.org/g:76f0343e31fc5da729986de72551d8622aafd728 commit 76f0343e31fc5da729986de72551d8622aafd728 Author: Michael Meissner Date: Wed Sep 4 11:49:07 2024 -0400 RFC2653-Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:0ad27476f30202855d64376550757839733f533c commit 0ad27476f30202855d64376550757839733f533c Author: Michael Meissner Date: Wed Sep 4 11:50:40 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

https://gcc.gnu.org/g:e0b9b958eef1fa1bb51267d4971bb0416fbe commit e0b9b958eef1fa1bb51267d4971bb0416fbe Author: Michael Meissner Date: Wed Sep 4 11:51:51 2024 -0400 RFC2653-PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruct

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

https://gcc.gnu.org/g:62146c78439db4835ad918255a08e57f41de47ce commit 62146c78439db4835ad918255a08e57f41de47ce Author: Michael Meissner Date: Wed Sep 4 11:53:39 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full 1

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