[gcc r15-337] i386: Fix some intrinsics without alignment requirements.

https://gcc.gnu.org/g:5967696c0f6300da4387fea5d102be5bc9f23233 commit r15-337-g5967696c0f6300da4387fea5d102be5bc9f23233 Author: Hu, Lin1 Date: Fri Jan 19 15:22:10 2024 +0800 i386: Fix some intrinsics without alignment requirements. gcc/ChangeLog: PR target/84508

[gcc r15-3474] testsuite: Fix xorsign.c, vect-double-2.c fails with -march=x86-64-v2

https://gcc.gnu.org/g:811204f52a111af24ba4b00df9e947a44c4c1161 commit r15-3474-g811204f52a111af24ba4b00df9e947a44c4c1161 Author: Hu, Lin1 Date: Thu Sep 5 14:51:42 2024 +0800 testsuite: Fix xorsign.c, vect-double-2.c fails with -march=x86-64-v2 These testcases raise fails with -mar

[gcc r15-1677] vect: generate suitable convert insn for int -> int, float -> float and int <-> float.

https://gcc.gnu.org/g:c320a7efcd35ba6c6be70dc9b2fe562a9673e363 commit r15-1677-gc320a7efcd35ba6c6be70dc9b2fe562a9673e363 Author: Hu, Lin1 Date: Thu Feb 1 15:15:01 2024 +0800 vect: generate suitable convert insn for int -> int, float -> float and int <-> float. gcc/ChangeLog:

[gcc r15-1678] vect: Support v4hi -> v4qi.

https://gcc.gnu.org/g:e5f8a39941f6f0f25dac88bd71fd368fb284a10f commit r15-1678-ge5f8a39941f6f0f25dac88bd71fd368fb284a10f Author: Hu, Lin1 Date: Wed Feb 28 18:11:55 2024 +0800 vect: Support v4hi -> v4qi. gcc/ChangeLog: PR target/107432 * config/i386/mmx

[gcc r15-1679] vect: support direct conversion under x86-64-v3.

https://gcc.gnu.org/g:4385dc97b0d28e54541eb2418d6e68fc672441d7 commit r15-1679-g4385dc97b0d28e54541eb2418d6e68fc672441d7 Author: Hu, Lin1 Date: Wed Mar 6 19:58:48 2024 +0800 vect: support direct conversion under x86-64-v3. gcc/ChangeLog: PR target/107432

[gcc r15-1680] i386: Refactor vcvttps2qq/vcvtqq2ps patterns.

https://gcc.gnu.org/g:94495247341bc05b77536271fe3dd789dad62624 commit r15-1680-g94495247341bc05b77536271fe3dd789dad62624 Author: Hu, Lin1 Date: Tue Jun 25 18:25:59 2024 +0800 i386: Refactor vcvttps2qq/vcvtqq2ps patterns. Refactor vcvttps2qq/vcvtqq2ps patterns for remove redundant

[gcc r15-1830] vect: Fix ICE caused by missing check for TREE_CODE == SSA_NAME

https://gcc.gnu.org/g:d1eeafe40f263acdb5eb1b57f777e064a11ced2b commit r15-1830-gd1eeafe40f263acdb5eb1b57f777e064a11ced2b Author: Hu, Lin1 Date: Wed Jul 3 10:07:02 2024 +0800 vect: Fix ICE caused by missing check for TREE_CODE == SSA_NAME Need to check if the tree's code is SSA_NAM

[gcc r15-1853] i386: Refactor ssedoublemode

https://gcc.gnu.org/g:319d3956b16b1270f27e9cbf749e881c4ff7dfb4 commit r15-1853-g319d3956b16b1270f27e9cbf749e881c4ff7dfb4 Author: Hu, Lin1 Date: Thu Jul 4 11:18:46 2024 +0800 i386: Refactor ssedoublemode ssedoublemode's double should mean double type, like SI -> DI. And we need

[gcc r15-2052] i386: extend trunc{128}2{16,32,64}'s scope.

https://gcc.gnu.org/g:a902e35396d68f10bd27477153fafa4f5ac9c319 commit r15-2052-ga902e35396d68f10bd27477153fafa4f5ac9c319 Author: Hu, Lin1 Date: Thu Jul 11 15:03:22 2024 +0800 i386: extend trunc{128}2{16,32,64}'s scope. Based on actual usage, trunc{128}2{16,32,64} use some instruct

[gcc r15-974] i386: Optimize EQ/NE comparison between avx512 kmask and -1.

https://gcc.gnu.org/g:bf7745f887c765e06f2e75508f263debb60aeb2e commit r15-974-gbf7745f887c765e06f2e75508f263debb60aeb2e Author: Hu, Lin1 Date: Thu May 9 09:29:07 2024 +0800 i386: Optimize EQ/NE comparison between avx512 kmask and -1. Acheive EQ/NE comparison between avx512 kmask a

[gcc r15-1370] i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.

https://gcc.gnu.org/g:b5d3ad256afdfd891d37d8fdb126d599f150e78b commit r15-1370-gb5d3ad256afdfd891d37d8fdb126d599f150e78b Author: Hu, Lin1 Date: Wed Jun 12 16:25:34 2024 +0800 i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX. gcc/ChangeLog:

[gcc r15-1389] i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx

https://gcc.gnu.org/g:7c6f79eea9febce3b21c5783bac9b0a36e08f003 commit r15-1389-g7c6f79eea9febce3b21c5783bac9b0a36e08f003 Author: Hu, Lin1 Date: Wed Mar 20 16:01:45 2024 +0800 i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx gcc/ChangeLog:

[gcc r15-4245] i386: Fix some patterns's mem attribute.

https://gcc.gnu.org/g:9f2f108a8a68c7b7b2de5350439a8ab8e17a54da commit r15-4245-g9f2f108a8a68c7b7b2de5350439a8ab8e17a54da Author: Hu, Lin1 Date: Wed Oct 9 10:20:05 2024 +0800 i386: Fix some patterns's mem attribute. Hi, all This is another patch to modify some pattern's ty

[gcc r15-4952] i386: Handling exception input of __builtin_ia32_prefetch. [PR117416]

https://gcc.gnu.org/g:ea46a216d48597b220ae69e79f6513c763f953be commit r15-4952-gea46a216d48597b220ae69e79f6513c763f953be Author: Hu, Lin1 Date: Mon Nov 4 14:52:56 2024 +0800 i386: Handling exception input of __builtin_ia32_prefetch. [PR117416] op1 should be between 0 and 2. Add an

[gcc r15-4973] i386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions.

https://gcc.gnu.org/g:8ac694ae67e24a798dce368587bed4c40b90fbc0 commit r15-4973-g8ac694ae67e24a798dce368587bed4c40b90fbc0 Author: Hu, Lin1 Date: Tue Nov 5 15:49:57 2024 +0800 i386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions. gcc/ChangeLog: PR target/

[gcc r15-5184] i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418]

https://gcc.gnu.org/g:2272cd2508f1854c880082f792de15e76ec09a99 commit r15-5184-g2272cd2508f1854c880082f792de15e76ec09a99 Author: Hu, Lin1 Date: Wed Nov 6 15:42:13 2024 +0800 i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418] -maddress-mo

[gcc r13-9183] i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418]

https://gcc.gnu.org/g:4758f8d410e961b09c8be619d6d0a71d5e7e4aa5 commit r13-9183-g4758f8d410e961b09c8be619d6d0a71d5e7e4aa5 Author: Hu, Lin1 Date: Wed Nov 6 15:42:13 2024 +0800 i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418] -maddress-mo

[gcc r12-10813] i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418]

https://gcc.gnu.org/g:e41fdca8a290c4d72b1972af8cdfd1dd60af31df commit r12-10813-ge41fdca8a290c4d72b1972af8cdfd1dd60af31df Author: Hu, Lin1 Date: Wed Nov 6 15:42:13 2024 +0800 i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418] -maddress-m

[gcc r15-3704] i386: Add ssemov2, sseicvt2 for some load instructions that use memory on operand2

https://gcc.gnu.org/g:1cf1bf7899985df31e1ebccb5d6f1ca762991dcf commit r15-3704-g1cf1bf7899985df31e1ebccb5d6f1ca762991dcf Author: Hu, Lin1 Date: Wed Sep 11 10:10:40 2024 +0800 i386: Add ssemov2, sseicvt2 for some load instructions that use memory on operand2 The memory attr of som

[gcc r14-10895] i386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions.

https://gcc.gnu.org/g:05fd99e3d5e9f00e4e23596ed15a3cec2aaba128 commit r14-10895-g05fd99e3d5e9f00e4e23596ed15a3cec2aaba128 Author: Hu, Lin1 Date: Tue Nov 5 15:49:57 2024 +0800 i386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions. gcc/ChangeLog: PR target

[gcc r14-10896] i386: Modify regexp of pr117304-1.c

https://gcc.gnu.org/g:6a0e143a6449bcc250af13642263f671f756500b commit r14-10896-g6a0e143a6449bcc250af13642263f671f756500b Author: Hu, Lin1 Date: Thu Nov 7 10:13:15 2024 +0800 i386: Modify regexp of pr117304-1.c Since the test doesn't care if the hint is correct, modify the reg

[gcc r15-5006] i386: Modify regexp of pr117304-1.c

https://gcc.gnu.org/g:4473cf8409f4db19ad91bd784e32dc54eccf02a3 commit r15-5006-g4473cf8409f4db19ad91bd784e32dc54eccf02a3 Author: Hu, Lin1 Date: Thu Nov 7 10:13:15 2024 +0800 i386: Modify regexp of pr117304-1.c Since the test doesn't care if the hint is correct, modify the rege

[gcc r14-10937] i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418]

https://gcc.gnu.org/g:8b4bb54e6c45411845ec559c49f594a6239c3969 commit r14-10937-g8b4bb54e6c45411845ec559c49f594a6239c3969 Author: Hu, Lin1 Date: Wed Nov 6 15:42:13 2024 +0800 i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418] -maddress-m

[gcc r15-8876] i386: Fix AVX10.2 sat cvt intrinsic.

https://gcc.gnu.org/g:90ab42f92b876b74056db297557e8c3d51cdd773 commit r15-8876-g90ab42f92b876b74056db297557e8c3d51cdd773 Author: Hu, Lin1 Date: Tue Mar 25 09:24:59 2025 +0800 i386: Fix AVX10.2 sat cvt intrinsic. The patch aims to modify the missed fixed for vcvttph2iubs's testcase

[gcc r15-8457] i386: Update Suffix for AVX10.2 SAT CVT Intrinsics

https://gcc.gnu.org/g:82bbc9da2c7a24a38916158eaff767cc82a7b6bf commit r15-8457-g82bbc9da2c7a24a38916158eaff767cc82a7b6bf Author: Hu, Lin1 Date: Tue Mar 18 10:03:22 2025 +0800 i386: Update Suffix for AVX10.2 SAT CVT Intrinsics The intrinsic names for *[i|u]bs instructions in AVX10.

[gcc r15-8463] i386: Fix AVX10.2 SAT CVT testcases.

https://gcc.gnu.org/g:8d236c53c679ca920092ce9200785fcccd97d971 commit r15-8463-g8d236c53c679ca920092ce9200785fcccd97d971 Author: Hu, Lin1 Date: Thu Mar 20 11:55:49 2025 +0800 i386: Fix AVX10.2 SAT CVT testcases. Init res_ref2 for rounding control intrinsics. gcc/testsuite

[gcc r15-9117] i386: Add attr_isa for vaes patterns to sync with attr gpr16. [pr119473]

https://gcc.gnu.org/g:e5cfa7f797b79613e5483786484567b9ca72db06 commit r15-9117-ge5cfa7f797b79613e5483786484567b9ca72db06 Author: Hu, Lin1 Date: Wed Mar 26 16:15:52 2025 +0800 i386: Add attr_isa for vaes patterns to sync with attr gpr16. [pr119473] For vaes patterns with jm constra

[gcc r15-8458] i386: Add AVX10.2 SAT CVT Intrinsics without Rounding Control

https://gcc.gnu.org/g:e35327242317282a4ff5e2d933719828a0285e81 commit r15-8458-ge35327242317282a4ff5e2d933719828a0285e81 Author: Hu, Lin1 Date: Thu Mar 13 16:36:15 2025 +0800 i386: Add AVX10.2 SAT CVT Intrinsics without Rounding Control gcc/ChangeLog: * config/i38

[gcc r15-8915] i386: Add "s_" as Saturation for AVX10.2 Converting Intrinsics.

https://gcc.gnu.org/g:330df57938fe609a49c5cb047be443475cb9a3c3 commit r15-8915-g330df57938fe609a49c5cb047be443475cb9a3c3 Author: Hu, Lin1 Date: Fri Mar 21 10:43:10 2025 +0800 i386: Add "s_" as Saturation for AVX10.2 Converting Intrinsics. This patch aims to add "s_" after 'cvt' re

[gcc r15-8964] i386: Set attr "addr" as "gpr16" for constraint "jm". [PR 119425]

https://gcc.gnu.org/g:271745bafafbf3316d01ceb6430d67b894129a4c commit r15-8964-g271745bafafbf3316d01ceb6430d67b894129a4c Author: Hu, Lin1 Date: Mon Mar 24 15:36:13 2025 +0800 i386: Set attr "addr" as "gpr16" for constraint "jm". [PR 119425] "jm" should with "gpr16", otherwise mayb

[gcc r15-8459] i386: Fix AVX10.2 SAT CVT testcases.

https://gcc.gnu.org/g:2e7a92a68aab3aaee8872c1a59e1391e07517b05 commit r15-8459-g2e7a92a68aab3aaee8872c1a59e1391e07517b05 Author: Hu, Lin1 Date: Fri Mar 14 11:16:14 2025 +0800 i386: Fix AVX10.2 SAT CVT testcases. Add missing testcases. gcc/testsuite/ChangeLog:

[gcc r16-1125] i386: Fix vmovvdup's mem attribute

https://gcc.gnu.org/g:24cbcc49277a0ac40fc2d82831f6db5e8d6d890d commit r16-1125-g24cbcc49277a0ac40fc2d82831f6db5e8d6d890d Author: Hu, Lin1 Date: Tue May 27 19:09:04 2025 +0800 i386: Fix vmovvdup's mem attribute Some vmovvdup pattern's type attribute is sselog1 and then mem attribut

[gcc r16-1093] i386: Add more forms peephole2 for adc/sbb

https://gcc.gnu.org/g:31b887bcc898787a228672d417ec0b33a15b2fb2 commit r16-1093-g31b887bcc898787a228672d417ec0b33a15b2fb2 Author: Hu, Lin1 Date: Wed Feb 19 15:51:40 2025 +0800 i386: Add more forms peephole2 for adc/sbb Enable -mapxf will change some patterns about adc/sbb.

[gcc r16-1094] i386: Add more peephole2 for APX NDD

https://gcc.gnu.org/g:102b21f9ce7d7a30cdee7c729a152e95c96107ac commit r16-1094-g102b21f9ce7d7a30cdee7c729a152e95c96107ac Author: Hu, Lin1 Date: Mon Mar 10 16:52:22 2025 +0800 i386: Add more peephole2 for APX NDD The patch aims to optimize movb(%rdi), %al