https://gcc.gnu.org/g:8ac694ae67e24a798dce368587bed4c40b90fbc0
commit r15-4973-g8ac694ae67e24a798dce368587bed4c40b90fbc0
Author: Hu, Lin1 <lin1...@intel.com>
Date: Tue Nov 5 15:49:57 2024 +0800
i386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions.
gcc/ChangeLog:
PR target/117304
* config/i386/i386-builtin.def: Add OPTION_MASK_ISA2_EVEX512 for
some
AVX512 512-bits instructions.
gcc/testsuite/ChangeLog:
PR target/117304
* gcc.target/i386/pr117304-1.c: New test.
Diff:
---
gcc/config/i386/i386-builtin.def | 10 +++++-----
gcc/testsuite/gcc.target/i386/pr117304-1.c | 28 ++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index c484e6dc29e4..26c23780b1c6 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3357,11 +3357,11 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0,
CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_
BDESC (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, 0,
CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64",
IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_sse2_cvtss2sd_round,
"__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int)
V2DF_FTYPE_V2DF_V4SF_INT)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_sse2_cvtss2sd_mask_round,
"__builtin_ia32_cvtss2sd_mask_round", IX86_BUILTIN_CVTSS2SD_MASK_ROUND,
UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_V2DF_UQI_INT)
-BDESC (OPTION_MASK_ISA_AVX512F, 0,
CODE_FOR_unspec_fix_truncv8dfv8si2_mask_round,
"__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int)
V8SI_FTYPE_V8DF_V8SI_QI_INT)
-BDESC (OPTION_MASK_ISA_AVX512F, 0,
CODE_FOR_unspec_fixuns_truncv8dfv8si2_mask_round,
"__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int)
V8SI_FTYPE_V8DF_V8SI_QI_INT)
-BDESC (OPTION_MASK_ISA_AVX512F, 0,
CODE_FOR_unspec_fix_truncv16sfv16si2_mask_round,
"__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int)
V16SI_FTYPE_V16SF_V16SI_HI_INT)
-BDESC (OPTION_MASK_ISA_AVX512F, 0,
CODE_FOR_unspec_fixuns_truncv16sfv16si2_mask_round,
"__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int)
V16SI_FTYPE_V16SF_V16SI_HI_INT)
-BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_floatunsv16siv16sf2_mask_round,
"__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int)
V16SF_FTYPE_V16SI_V16SF_HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_EVEX512,
CODE_FOR_unspec_fix_truncv8dfv8si2_mask_round,
"__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int)
V8SI_FTYPE_V8DF_V8SI_QI_INT)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_EVEX512,
CODE_FOR_unspec_fixuns_truncv8dfv8si2_mask_round,
"__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int)
V8SI_FTYPE_V8DF_V8SI_QI_INT)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_EVEX512,
CODE_FOR_unspec_fix_truncv16sfv16si2_mask_round,
"__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int)
V16SI_FTYPE_V16SF_V16SI_HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_EVEX512,
CODE_FOR_unspec_fixuns_truncv16sfv16si2_mask_round,
"__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int)
V16SI_FTYPE_V16SF_V16SI_HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_EVEX512,
CODE_FOR_floatunsv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask",
IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT)
BDESC (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, 0,
CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64",
IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_cvtusi2ss32_round,
"__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int)
V4SF_FTYPE_V4SF_UINT_INT)
BDESC (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, 0,
CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64",
IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT)
diff --git a/gcc/testsuite/gcc.target/i386/pr117304-1.c
b/gcc/testsuite/gcc.target/i386/pr117304-1.c
new file mode 100644
index 000000000000..fc1c5bfd3e35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr117304-1.c
@@ -0,0 +1,28 @@
+/* PR target/117304 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f -mno-evex512" } */
+
+typedef __attribute__((__vector_size__(32))) int __v8si;
+typedef __attribute__((__vector_size__(32))) unsigned int __v8su;
+typedef __attribute__((__vector_size__(64))) double __v8df;
+typedef __attribute__((__vector_size__(64))) int __v16si;
+typedef __attribute__((__vector_size__(64))) unsigned int __v16su;
+typedef __attribute__((__vector_size__(64))) float __v16sf;
+typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
+
+volatile __v8df df;
+volatile __v16sf sf;
+volatile __v8si hi;
+volatile __v8su hui;
+volatile __v16si i;
+volatile __v16su ui;
+
+void
+foo()
+{
+ hi ^= __builtin_ia32_cvttpd2dq512_mask(df, hi, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttpd2dq512_mask'; did you
mean '__builtin_ia32_cvttpd2dq128_mask'?" } */
+ hui ^= __builtin_ia32_cvttpd2udq512_mask(df, hui, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttpd2udq512_mask'; did you
mean '__builtin_ia32_cvttpd2udq128_mask'?" } */
+ ui ^= __builtin_ia32_cvttps2dq512_mask(sf, ui, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttps2dq512_mask'; did you
mean '__builtin_ia32_cvttps2dq128_mask'?" } */
+ ui ^= __builtin_ia32_cvttps2udq512_mask(sf, ui, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttps2udq512_mask'; did you
mean '__builtin_ia32_cvttps2udq128_mask'?" } */
+ __builtin_ia32_cvtudq2ps512_mask(ui, sf, 0, 4); /* { dg-error "implicit
declaration of function '__builtin_ia32_cvtudq2ps512_mask'; did you mean
'__builtin_ia32_cvtudq2ps128_mask'?" } */
+}
