[gcc r15-3955] tree-optimization/116850 - corrupt post-dom info

https://gcc.gnu.org/g:64163657ba7e70347087a63bb2b32d83b52ea7d9 commit r15-3955-g64163657ba7e70347087a63bb2b32d83b52ea7d9 Author: Richard Biener Date: Thu Sep 26 15:41:59 2024 +0200 tree-optimization/116850 - corrupt post-dom info Path isolation computes post-dominators on demand b

[gcc r15-3957] tree-optimization/116842 - vectorizer load hosting breaks UID order

https://gcc.gnu.org/g:71bf3daa8dabe45aa14e7315195a70ad0d883337 commit r15-3957-g71bf3daa8dabe45aa14e7315195a70ad0d883337 Author: Richard Biener Date: Sat Sep 28 14:02:18 2024 +0200 tree-optimization/116842 - vectorizer load hosting breaks UID order The following fixes the case whe

[gcc r15-3956] tree-optimization/116785 - relax volatile handling in PTA

https://gcc.gnu.org/g:85f5d0642184b68b38bf3daee5a1d04b753850b1 commit r15-3956-g85f5d0642184b68b38bf3daee5a1d04b753850b1 Author: Richard Biener Date: Fri Sep 27 13:50:31 2024 +0200 tree-optimization/116785 - relax volatile handling in PTA When there's volatile qualified stores we

[gcc r15-3950] cselib: Discard useless locs of preserved VALUEs [PR116627]

https://gcc.gnu.org/g:73726725ae03995ef8b61622c954f7ca70416f79 commit r15-3950-g73726725ae03995ef8b61622c954f7ca70416f79 Author: Jakub Jelinek Date: Sun Sep 29 21:52:32 2024 +0200 cselib: Discard useless locs of preserved VALUEs [PR116627] remove_useless_values iteratively discard

[gcc r15-3952] RISC-V: Add testcases for form 1 of scalar signed SAT_SUB

https://gcc.gnu.org/g:a2a78c0639dbebdab19d71f54edca99e7f9094fd commit r15-3952-ga2a78c0639dbebdab19d71f54edca99e7f9094fd Author: Pan Li Date: Wed Sep 25 09:42:31 2024 +0800 RISC-V: Add testcases for form 1 of scalar signed SAT_SUB Form 1: #define DEF_SAT_S_SUB_FMT_1(T, UT, M

[gcc r15-3951] RISC-V: Implement scalar SAT_SUB for signed integer

https://gcc.gnu.org/g:b6ea98bcaf1dad506fa643df8df50187feeb7e35 commit r15-3951-gb6ea98bcaf1dad506fa643df8df50187feeb7e35 Author: Pan Li Date: Wed Sep 25 09:36:05 2024 +0800 RISC-V: Implement scalar SAT_SUB for signed integer This patch would like to implement the sssub form 1. Ak

[gcc(refs/users/omachota/heads/rtl-ssa-dce)] rtl-ssa: dce fix mark compile and sweep sketch

https://gcc.gnu.org/g:96c7ea34796ff0c661209c4fa4caebb78ec3428f commit 96c7ea34796ff0c661209c4fa4caebb78ec3428f Author: Ondřej Machota Date: Sun Sep 29 22:17:46 2024 +0200 rtl-ssa: dce fix mark compile and sweep sketch Diff: --- gcc/dce.cc | 1658 +-

[gcc r14-10723] i386: Modernize AMD processor types

https://gcc.gnu.org/g:4697543b765dbfaa9dc12be0537861e586e48202 commit r14-10723-g4697543b765dbfaa9dc12be0537861e586e48202 Author: Uros Bizjak Date: Fri Sep 27 15:58:17 2024 +0200 i386: Modernize AMD processor types Use iterative PTA definitions for members of the same AMD processo

[gcc r15-3954] Match: Support form 1 for scalar signed integer SAT_SUB

https://gcc.gnu.org/g:3f8b1b21f377427adbdfa4cbfc21b979eb49c9d3 commit r15-3954-g3f8b1b21f377427adbdfa4cbfc21b979eb49c9d3 Author: Pan Li Date: Wed Sep 25 09:26:07 2024 +0800 Match: Support form 1 for scalar signed integer SAT_SUB This patch would like to support the form 1 of the s

[gcc r15-3945] doc: Document struct-layout-1.exp for ABI checks

https://gcc.gnu.org/g:a30a9d5da144d87bdfd60cfc485b46bb3a74842f commit r15-3945-ga30a9d5da144d87bdfd60cfc485b46bb3a74842f Author: Dimitar Dimitrov Date: Fri Sep 6 22:49:50 2024 +0300 doc: Document struct-layout-1.exp for ABI checks This test helped discover PR116621, so it is worth

[gcc r15-3946] [PATCH v2] RISC-V: Improve code generation for select of consecutive constants

https://gcc.gnu.org/g:a0f1f504b2c49a3695b91d3323d2e2419ef970db commit r15-3946-ga0f1f504b2c49a3695b91d3323d2e2419ef970db Author: Jovan Vukic Date: Sun Sep 29 10:06:43 2024 -0600 [PATCH v2] RISC-V: Improve code generation for select of consecutive constants Based on the valuable f

[gcc r15-3947] [PATCH] [PATCH] Avoid integer overflow in gcc.dg/cpp/charconst-3.c (PR testsuite/116806)

https://gcc.gnu.org/g:0cd24b06d130d99bd86e5e03a01c38047413a92e commit r15-3947-g0cd24b06d130d99bd86e5e03a01c38047413a92e Author: Mikael Pettersson Date: Sun Sep 29 10:15:55 2024 -0600 [PATCH] [PATCH] Avoid integer overflow in gcc.dg/cpp/charconst-3.c (PR testsuite/116806) The int

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_SUB

https://gcc.gnu.org/g:3980fecc0eae20a4993bcba9afb455cdd58346cd commit 3980fecc0eae20a4993bcba9afb455cdd58346cd Author: Pan Li Date: Wed Sep 25 13:55:22 2024 +0800 RISC-V: Refine the testcase of vector SAT_SUB Take scan-assembler-times for vssub insn check instead of function body,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_TRUNC

https://gcc.gnu.org/g:36b00f64d01622439f62501ea4f6c6c7c50f13e4 commit 36b00f64d01622439f62501ea4f6c6c7c50f13e4 Author: Pan Li Date: Wed Sep 25 14:37:46 2024 +0800 RISC-V: Refine the testcase of vector SAT_TRUNC Take scan-assembler-times for vnclip insn check instead of function bo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Fix SELECT_VL SLP fallout.

https://gcc.gnu.org/g:931ef37a209ca3b6fd5dd7158d207df64adffddb commit 931ef37a209ca3b6fd5dd7158d207df64adffddb Author: Robin Dapp Date: Thu Sep 19 05:08:47 2024 -0700 RISC-V: testsuite: Fix SELECT_VL SLP fallout. This fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d where we a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_ADD

https://gcc.gnu.org/g:52055ad7be1372f849f7ce04be91e3791591e1e8 commit 52055ad7be1372f849f7ce04be91e3791591e1e8 Author: Pan Li Date: Wed Sep 25 11:41:22 2024 +0800 RISC-V: Refine the testcase of vector SAT_ADD Take scan-assembler-times for vsadd insn check instead of function body,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD

https://gcc.gnu.org/g:7ec1234888e05ddb4a36877d2257ff6bf388c56d commit 7ec1234888e05ddb4a36877d2257ff6bf388c56d Author: Pan Li Date: Fri Sep 20 10:01:40 2024 +0800 RISC-V: Add testcases for form 3 of signed scalar SAT_ADD This patch would like to add testcases of the signed scalar

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement SAT_ADD for signed integer vector

https://gcc.gnu.org/g:e284213dc880f678994a36b8f24f22d8c2444588 commit e284213dc880f678994a36b8f24f22d8c2444588 Author: Pan Li Date: Thu Sep 12 10:43:46 2024 +0800 RISC-V: Implement SAT_ADD for signed integer vector This patch would like to implement the ssadd for vector integer.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix effective target check.

https://gcc.gnu.org/g:c9e63024a36590e2b84f446d0a0c27c95a9d4d56 commit c9e63024a36590e2b84f446d0a0c27c95a9d4d56 Author: Robin Dapp Date: Fri Aug 30 14:35:08 2024 +0200 RISC-V: Fix effective target check. The return value is inverted in check_effective_target_rvv_zvl256b_ok and

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of signed scalar SAT_ADD

https://gcc.gnu.org/g:40a62c2f831051f7b7dd4c56c1056591ec2926bd commit 40a62c2f831051f7b7dd4c56c1056591ec2926bd Author: Pan Li Date: Fri Sep 20 10:15:37 2024 +0800 RISC-V: Add testcases for form 4 of signed scalar SAT_ADD Form 4: #define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

https://gcc.gnu.org/g:81f5fff4ec670624603f1f687935d33f551abf25 commit 81f5fff4ec670624603f1f687935d33f551abf25 Author: Xianmiao Qu Date: Wed Sep 18 07:28:44 2024 -0600 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. The Combine Pass may generate zero_extract instruct

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

https://gcc.gnu.org/g:95e5c07ea48f3ff482141fe7b435321c97e533da commit 95e5c07ea48f3ff482141fe7b435321c97e533da Author: Pan Li Date: Sat Sep 21 12:51:58 2024 +0800 RISC-V: Add testcases for form 3 of signed vector SAT_ADD Form 3: #define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add more vector-vector extract cases.

https://gcc.gnu.org/g:62ce984524ec7da729c3ea2c044a2fcc5403 commit 62ce984524ec7da729c3ea2c044a2fcc5403 Author: Robin Dapp Date: Tue Sep 3 17:53:34 2024 +0200 RISC-V: Add more vector-vector extract cases. This adds a V16SI -> V4SI and related i.e. "quartering" vector-vector

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

https://gcc.gnu.org/g:91be221f94c98df38bea08c27695e18da357c9f0 commit 91be221f94c98df38bea08c27695e18da357c9f0 Author: Bohan Lei Date: Wed Sep 18 07:20:23 2024 -0600 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx The RISC-V vector machine description relies on the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

https://gcc.gnu.org/g:4f8885fd58ea8de22735b545205285c242b35c9f commit 4f8885fd58ea8de22735b545205285c242b35c9f Author: Pan Li Date: Wed Sep 11 07:00:13 2024 +0800 RISC-V: Fix asm check for Vector SAT_* due to middle-end change The middle-end change makes the effect on the layout o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass

https://gcc.gnu.org/g:7a987a1f5d78e5bb5b8bf2f16421a033a2a012cb commit 7a987a1f5d78e5bb5b8bf2f16421a033a2a012cb Author: garthlei Date: Wed Sep 11 17:09:37 2024 +0800 RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass This patch fixes a bug in the current vsetvl pass. The cur

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vector SAT_ADD dump check due to middle-end change

https://gcc.gnu.org/g:a934530a3f78989461de6e0e4dd30d7ea90664ee commit a934530a3f78989461de6e0e4dd30d7ea90664ee Author: Pan Li Date: Wed Sep 11 14:17:30 2024 +0800 RISC-V: Fix vector SAT_ADD dump check due to middle-end change This patch would like fix the dump check times of vecto

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

https://gcc.gnu.org/g:ab870d37a7d392d56872b7b56b58534495d16447 commit ab870d37a7d392d56872b7b56b58534495d16447 Author: Pan Li Date: Fri Sep 13 10:05:49 2024 +0800 RISC-V: Add testcases for form 2 of signed scalar SAT_ADD This patch would like to add testcases of the signed scalar

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] riscv: Fix duplicate assmbler label in @tlsdesc insn

https://gcc.gnu.org/g:8d6d5ffef9e0718948a4273defca990cf616e915 commit 8d6d5ffef9e0718948a4273defca990cf616e915 Author: Andreas Schwab Date: Thu Sep 12 13:55:09 2024 +0200 riscv: Fix duplicate assmbler label in @tlsdesc insn Use %= instead of maintaining a sequence number manually,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Eliminate latter vsetvl when fused

https://gcc.gnu.org/g:31b29d5c7d142bca046ebd16cb18867d2d2f6d43 commit 31b29d5c7d142bca046ebd16cb18867d2d2f6d43 Author: Bohan Lei Date: Thu Sep 12 10:28:03 2024 +0800 RISC-V: Eliminate latter vsetvl when fused Hi all, A simple assembly check has been added in this version.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model

https://gcc.gnu.org/g:977f633aa659530748befad2dbba8bd3b5f68258 commit 977f633aa659530748befad2dbba8bd3b5f68258 Author: Zhao Dingyi Date: Sat Sep 7 10:48:46 2024 -0600 [PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model This patch aims to add the missing inst

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector

https://gcc.gnu.org/g:ef057b44071884b86979d82a469d7eac2ec442a1 commit ef057b44071884b86979d82a469d7eac2ec442a1 Author: Jin Ma Date: Sat Sep 7 10:29:02 2024 -0600 [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector Since the THeadVec

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

https://gcc.gnu.org/g:11234fb5acfc524f6c4e0095a568faec75480332 commit 11234fb5acfc524f6c4e0095a568faec75480332 Author: Jin Ma Date: Wed Sep 18 08:56:23 2024 -0600 [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix signed SAT_ADD test case for int64_t

https://gcc.gnu.org/g:1e9292c84d6689c5dab618669dd050f5e1945f07 commit 1e9292c84d6689c5dab618669dd050f5e1945f07 Author: Pan Li Date: Fri Sep 13 09:16:48 2024 +0800 RISC-V: Fix signed SAT_ADD test case for int64_t The int8_t test for signed SAT_ADD is sat_s_add-1.c, the sat_s_add-4.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of signed vector SAT_ADD

https://gcc.gnu.org/g:3694b042a64488bf30c00f1daa0373d4bcc852c2 commit 3694b042a64488bf30c00f1daa0373d4bcc852c2 Author: Pan Li Date: Fri Sep 20 16:09:56 2024 +0800 RISC-V: Add testcases for form 2 of signed vector SAT_ADD Form 2: #define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Improve code generation for select of consecutive constants

https://gcc.gnu.org/g:68251c8c320a33ea36c4b16f50e67d12fa404908 commit 68251c8c320a33ea36c4b16f50e67d12fa404908 Author: Jovan Vukic Date: Sun Sep 29 10:06:43 2024 -0600 [PATCH v2] RISC-V: Improve code generation for select of consecutive constants Based on the valuable feedback I

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V/libgcc: Save/Restore routines for E goes with ABI.

https://gcc.gnu.org/g:c4446c881e52eb82d5a806f76adce75e71b1032a commit c4446c881e52eb82d5a806f76adce75e71b1032a Author: Jim Lin Date: Fri Sep 27 14:44:12 2024 +0800 RISC-V/libgcc: Save/Restore routines for E goes with ABI. That Save/Restore routines for E can be used for RVI with I

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

https://gcc.gnu.org/g:ab7ab5ce05edb5e6dcf21925651cd9ebc2142291 commit ab7ab5ce05edb5e6dcf21925651cd9ebc2142291 Author: Xianmiao Qu Date: Wed Sep 18 07:35:12 2024 -0600 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression. I think it is a typo. When c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register

https://gcc.gnu.org/g:672292e319c3f73ce2c26c019e59cfa0a65ea8ec commit 672292e319c3f73ce2c26c019e59cfa0a65ea8ec Author: Yixuan Chen Date: Tue Sep 24 09:15:00 2024 -0600 [PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register gcc/ChangeLog: * con

[gcc r15-3948] [PATCH] SH: Document extended asm operand modifers

https://gcc.gnu.org/g:01a42a07e52811164787d98cd463fe79c17fc911 commit r15-3948-g01a42a07e52811164787d98cd463fe79c17fc911 Author: Pietro Monteiro Date: Sun Sep 29 10:39:05 2024 -0600 [PATCH] SH: Document extended asm operand modifers From: Pietro Monteiro SH: Document ext

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup debug code for SAT_* testcases [NFC]

https://gcc.gnu.org/g:e58bd4fed07f7b095d3a8d1c442efbdd6f4901cd commit e58bd4fed07f7b095d3a8d1c442efbdd6f4901cd Author: Pan Li Date: Wed Sep 25 16:00:27 2024 +0800 RISC-V: Cleanup debug code for SAT_* testcases [NFC] Some print code for debugging is committed by mistake, remove the

[gcc r15-3949] testsuite: XFAIL gfortran.dg/initialization_25.f90 properly (again)

https://gcc.gnu.org/g:f4d0c6acc0ef43d7971f2d53afaa64ca05fb4718 commit r15-3949-gf4d0c6acc0ef43d7971f2d53afaa64ca05fb4718 Author: Sam James Date: Sun Sep 29 18:44:20 2024 +0100 testsuite: XFAIL gfortran.dg/initialization_25.f90 properly (again) dg-error needs an argument for "why"

[gcc(refs/users/omachota/heads/rtl-ssa-dce)] rtl-ssa: dce mark sketch

https://gcc.gnu.org/g:18c34785c85295f2366c0a0a110f33f4da260ba4 commit 18c34785c85295f2366c0a0a110f33f4da260ba4 Author: Ondřej Machota Date: Sun Sep 29 20:20:11 2024 +0200 rtl-ssa: dce mark sketch Diff: --- gcc/dce.cc | 57 + 1 file