[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_TRUNC

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:36b00f64d01622439f62501ea4f6c6c7c50f13e4

commit 36b00f64d01622439f62501ea4f6c6c7c50f13e4
Author: Pan Li <pan2...@intel.com>
Date:   Wed Sep 25 14:37:46 2024 +0800

    RISC-V: Refine the testcase of vector SAT_TRUNC
    
    Take scan-assembler-times for vnclip insn check instead of function body,
    as we only care about if we can generate the fixed point insn vnclip.
    
    The below test are passed for this patch.
    * The rv64gcv fully regression test.
    
    It is test only patch and obvious up to a point, will commit it
    directly if no comments in next 48H.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Remove
            func body check and take scan asm times instead.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.
    
    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 5b652b0132334e509c730311ac625c1dbe287282)

Diff:
---
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c      | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c     | 16 +---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c     | 12 +-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c     | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c     | 21 ++-------------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c     | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c      | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c     | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c     | 21 ++-------------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c     | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c     | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c      | 21 ++-------------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c      | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c      | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c      | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c      | 13 ++-----------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c      | 17 ++---------------
 .../riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c      | 21 ++-------------------
 24 files changed, 46 insertions(+), 328 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index 186005733ecd..3d29d26abff1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
index 6ee407dd04cd..c9634d383aee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
index bd3e108bd521..17e176b87dbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -1,22 +1,8 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
index 4821e13d0c1a..1ebf5c88d3a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
@@ -1,18 +1,8 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
index d83ce7f6b03e..04d12048bc24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
index 2098e8b17c3f..072d189224fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
index 1ffd507eecef..837551ca6b63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
@@ -1,26 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
index 99c6cedf82fc..3174f45fd60d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
index 8dd648854efd..f177f7bedd75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
index f3ab601a753f..32a30f3692af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
index f0104c7918af..dd14fad454cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
index f65b747ca119..5354717cc46f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
index 0c8988dd0d80..b77fcd4a5bca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
index 01fb666273bf..db788e19092d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
@@ -1,26 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
index 0d899b7d3293..8b27b69cf08b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
index 1a26484da8ad..df1752c05db2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
index 344f72049e00..200c559f8550 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
index 6bdab50242cf..15654b4bf8be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
@@ -1,26 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
index 4b1998c635fa..1e272aeb7262 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
index 048c3abd17c2..eb7d96197bb7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
index 79fdbb6937ca..fc43a8a58f83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
index 0d96c477a88e..b5a3fc3222d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
index 0eb3aedeba98..9ed21e21e334 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
@@ -1,22 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
index 97bcb182e2c4..d93453f68907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
@@ -1,26 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-*/
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */