[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:11234fb5acfc524f6c4e0095a568faec75480332

commit 11234fb5acfc524f6c4e0095a568faec75480332
Author: Jin Ma <ji...@linux.alibaba.com>
Date:   Wed Sep 18 08:56:23 2024 -0600

    [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern 
in the Zfa extension on rv32.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa 
extension on rv32.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
    
    (cherry picked from commit 85fcf740342e308da4776a45a4cd726987725a6a)

Diff:
---
 gcc/config/riscv/riscv.md                            | 16 +++++++++-------
 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c |  9 +++++++++
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index fd1cbebc435b..0410d990ec58 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -56,6 +56,8 @@
   UNSPEC_FLT_QUIET
   UNSPEC_FLE_QUIET
   UNSPEC_COPYSIGN
+  UNSPEC_FMV_X_W
+  UNSPEC_FMVH_X_D
   UNSPEC_RINT
   UNSPEC_ROUND
   UNSPEC_FLOOR
@@ -2626,8 +2628,9 @@
 
 (define_insn "movsidf2_low_rv32"
   [(set (match_operand:SI      0 "register_operand" "=  r")
-       (truncate:SI
-           (match_operand:DF 1 "register_operand"  "zmvf")))]
+       (unspec:SI
+           [(match_operand:DF 1 "register_operand" "zmvf")]
+       UNSPEC_FMV_X_W))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmv.x.w\t%0,%1"
   [(set_attr "move_type" "fmove")
@@ -2636,11 +2639,10 @@
 
 
 (define_insn "movsidf2_high_rv32"
-  [(set (match_operand:SI      0 "register_operand"    "=  r")
-       (truncate:SI
-            (lshiftrt:DF
-                (match_operand:DF 1 "register_operand" "zmvf")
-                (const_int 32))))]
+  [(set (match_operand:SI      0 "register_operand" "=  r")
+       (unspec:SI
+           [(match_operand:DF 1 "register_operand" "zmvf")]
+       UNSPEC_FMVH_X_D))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvh.x.d\t%0,%1"
   [(set_attr "move_type" "fmove")
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c 
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c
new file mode 100644
index 000000000000..e00047b09e3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c
@@ -0,0 +1,9 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zfa -mabi=ilp32d -O2 -g" } */
+
+unsigned int
+foo (double a) {
+  unsigned int tt = *(unsigned long long *)&a & 0xffff;
+  return tt;
+}